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Release 10.1 Map K.31 (lin)Xilinx Mapping Report File for Design 'CC3_top_x'Design Information------------------Command Line : map -ise/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise -intstyle ise-p xc2s100-pq208-5 -cm area -pr off -k 4 -c 100 -tx off -o CC3_top_x_map.ncdCC3_top_x.ngd CC3_top_x.pcfTarget Device : xc2s100Target Package : pq208Target Speed : -5Mapper Version : spartan2 -- $Revision: 1.46 $Mapped Date : Wed Dec 25 11:42:53 2013Design Summary--------------Number of errors: 0Number of warnings: 6Logic Utilization:Number of Slice Flip Flops: 301 out of 2,400 12%Number of 4 input LUTs: 2,239 out of 2,400 93%Logic Distribution:Number of occupied Slices: 1,198 out of 1,200 99%Number of Slices containing only related logic: 1,198 out of 1,198 100%Number of Slices containing unrelated logic: 0 out of 1,198 0%*See NOTES below for an explanation of the effects of unrelated logicTotal Number of 4 input LUTs: 2,291 out of 2,400 95%Number used as logic: 2,239Number used as a route-thru: 52Number of bonded IOBs: 26 out of 140 18%Number of Block RAMs: 1 out of 10 10%Number of GCLKs: 1 out of 4 25%Number of GCLKIOBs: 1 out of 4 25%Peak Memory Usage: 148 MBTotal REAL time to MAP completion: 2 secsTotal CPU time to MAP completion: 2 secsNOTES:Related logic is defined as being logic that shares connectivity - e.g. twoLUTs are "related" if they share common inputs. When assembling slices,Map gives priority to combine logic that is related. Doing so results inthe best timing performance.Unrelated logic shares no connectivity. Map will only begin packingunrelated logic into a slice once 99% of the slices are occupied throughrelated logic packing.Note that once logic distribution reaches the 99% level through relatedlogic packing, this does not mean the device is completely utilized.Unrelated logic packing will then begin, continuing until all usable LUTsand FFs are occupied. Depending on your timing budget, increased levels ofunrelated logic packing may adversely affect the overall timing performanceof your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group and Partition SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Control Set InformationSection 14 - Utilization by HierarchySection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:Pack:266 - The function generator cpu/k_pp_active_reg_mux0000<3>11failed to merge with F5 multiplexer cpu/state_mux0000<1>1_f5. There is aconflict for the FXMUX. The design will exhibit suboptimal timing.WARNING:Pack:249 - The following adjacent carry multiplexers occupy differentslice components. The resulting carry chain will have suboptimal timing.cpu/alu/Mmult_mul16_w_Madd1_cy<8>cpu/alu/Mmult_mul16_w_Madd1_cy<9>WARNING:Pack:249 - The following adjacent carry multiplexers occupy differentslice components. The resulting carry chain will have suboptimal timing.cpu/alu/Mmult_mul16_w_Madd_cy<7>cpu/alu/Mmult_mul16_w_Madd_cy<8>WARNING:Pack:249 - The following adjacent carry multiplexers occupy differentslice components. The resulting carry chain will have suboptimal timing.cpu/alu/Mmult_mul16_w_Madd3_cy<11>cpu/alu/Mmult_mul16_w_Madd3_cy<12>WARNING:Pack:249 - The following adjacent carry multiplexers occupy differentslice components. The resulting carry chain will have suboptimal timing.cpu/alu/Mmult_mul16_w_Madd5_cy<5>cpu/alu/Mmult_mul16_w_Madd5_cy<6>WARNING:Pack:249 - The following adjacent carry multiplexers occupy differentslice components. The resulting carry chain will have suboptimal timing.cpu/alu/Mmult_mul16_w_Madd2_cy<7>cpu/alu/Mmult_mul16_w_Madd2_cy<8>Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slewrate limited output drivers. The delay on speed critical single ended outputscan be dramatically reduced by designating them as fast outputs.Section 4 - Removed Logic Summary---------------------------------2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set thedetailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| clk32_i | GCLKIOB | INPUT | LVTTL | | | | | || mem_addr_o<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_addr_o<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_addr_o<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_addr_o<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_addr_o<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_addr_o<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_addr_o<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_addr_o<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_addr_o<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_addr_o<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_addr_o<10> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_addr_o<11> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_addr_o<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_addr_o<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_addr_o<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_addr_o<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_data_io<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_data_io<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_data_io<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_data_io<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_data_io<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_data_io<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_data_io<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_data_io<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_oe_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || mem_we_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group and Partition Summary--------------------------------------------Area Group Information----------------------No area groups were found in this design.----------------------Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------No timing report for this architecture.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Control Set Information------------------------------------No control set information for this architecture.