URL
https://opencores.org/ocsvn/8051/8051/trunk
Subversion Repositories 8051
[/] [8051/] [tags/] [rel0/] [syn/] [src/] [verilog/] [oc8051_rom.v] - Rev 186
Compare with Previous | Blame | View Log
////////////////////////////////////////////////////////////////////// //// //// //// 8051 program rom //// //// //// //// This file is part of the 8051 cores project //// //// http://www.opencores.org/cores/8051/ //// //// //// //// Description //// //// program rom //// //// //// //// To Do: //// //// nothing //// //// //// //// Author(s): //// //// - Simon Teran, simont@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // ver: 1 // // synopsys translate_off `include "oc8051_timescale.v" // synopsys translate_on //`include "oc8051_defines.v" module ROM32X1(O, A0, A1, A2, A3, A4); // synthesis syn_black_box syn_resources="luts=2" output O; input A0; input A1; input A2; input A3; input A4; endmodule //rom for 8051 processor module oc8051_rom (clk, rst, addr, data1, data2, data3); input clk, rst; input [15:0] addr; output [7:0] data1, data2, data3; reg [7:0] data1, data2, data3; reg [4:0] addr01; wire [15:0] addr_rst; wire [7:0] int_data0, int_data1, int_data2, int_data3; assign addr_rst = rst ? 16'h0000 : addr; rom0 rom_0 (.a(addr01), .o(int_data0)); rom1 rom_1 (.a(addr01), .o(int_data1)); rom2 rom_2 (.a(addr_rst[6:2]), .o(int_data2)); rom3 rom_3 (.a(addr_rst[6:2]), .o(int_data3)); always @(addr_rst) begin if (addr_rst[1]) addr01= addr_rst[6:2]+5'b00001; else addr01= addr_rst[6:2]; end // // always read tree bits in row always @(posedge clk) begin case(addr[1:0]) 2'b00: begin data1 <= #1 int_data0; data2 <= #1 int_data1; data3 <= #1 int_data2; end 2'b01:begin data1 <= #1 int_data1; data2 <= #1 int_data2; data3 <= #1 int_data3; end 2'b10:begin data1 <= #1 int_data2; data2 <= #1 int_data3; data3 <= #1 int_data0; end 2'b11:begin data1 <= #1 int_data3; data2 <= #1 int_data0; data3 <= #1 int_data1; end default: begin data1 <= #1 8'h00; data2 <= #1 8'h00; data3 <= #1 8'h00; end endcase end endmodule //rom0 module rom0 (o,a); input [4:0] a; output [7:0] o; ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00003810" */; ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=08047212" */; ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=04003e00" */; ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00043412" */; ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0c023c10" */; ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0c063f12" */; ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=04063d10" */; ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000634b2" */; endmodule //rom1 module rom1 (o,a); input [4:0] a; output [7:0] o; ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=040061c4" */; ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00061100" */; ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00100094" */; ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00027292" */; ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00123256" */; ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00147096" */; ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00107096" */; ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00006880" */; endmodule //rom2 module rom2 (o,a); input [4:0] a; output [7:0] o; ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02101c53" */; ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00023040" */; ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02005261" */; ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02023360" */; ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02005801" */; ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02023241" */; ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02023201" */; ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00023224" */; endmodule //rom3 module rom3 (o,a); input [4:0] a; output [7:0] o; ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02100b16" */; ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02200604" */; ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02103416" */; ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=02100846" */; ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00331c33" */; ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0033381a" */; ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0013181a" */; ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000061" */; endmodule