URL
https://opencores.org/ocsvn/8051/8051/trunk
Subversion Repositories 8051
[/] [8051/] [tags/] [rel_1/] [sim/] [rtl_sim/] [out/] [ncelab.out] - Rev 185
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Elaborating the design hierarchy:
Caching library 'worklib' ....... Done
Building instance overlay tables:
$readmemh("../src/oc8051_test.vec", buff);
|
ncelab: *W,MEMODR (/projects/oc8051/simont/oc8051/bench/verilog/oc8051_tb.v,133|41): $readmem default memory order incompatible with IEEE1364.
..............
$readmemh("../src/oc8051_rom.in", buff);
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ncelab: *W,MEMODR (../src/verilog/oc8051_rom.v,34|39): $readmem default memory order incompatible with IEEE1364.
...... Done
Generating native compiled code:
worklib.oc0851_int:v <0x42e3c287>
streams: 102, words: 76709
worklib.oc8051_acc:v <0x1240b0c4>
streams: 12, words: 9266
worklib.oc8051_alu:v <0x36548d1c>
streams: 19, words: 31722
worklib.oc8051_alu_src1_sel:v <0x49045171>
streams: 1, words: 1014
worklib.oc8051_alu_src2_sel:v <0x7e59f8f4>
streams: 1, words: 962
worklib.oc8051_alu_src3_sel:v <0x4a887dff>
streams: 1, words: 396
worklib.oc8051_b_register:v <0x7f8909e8>
streams: 9, words: 7095
worklib.oc8051_comp:v <0x32453df9>
streams: 1, words: 1188
worklib.oc8051_cy_select:v <0x3920b7c3>
streams: 1, words: 924
worklib.oc8051_decoder:v <0x28b2f0c5>
streams: 37, words: 374153
worklib.oc8051_divide:v <0x6c098db6>
streams: 15, words: 7930
worklib.oc8051_dptr:v <0x3105e8b6>
streams: 7, words: 5614
worklib.oc8051_ext_addr_sel:v <0x6603647c>
streams: 8, words: 4449
worklib.oc8051_immediate_sel:v <0x5b114496>
streams: 10, words: 8328
worklib.oc8051_indi_addr:v <0x4d1dae6d>
streams: 2, words: 5837
worklib.oc8051_multiply:v <0x2c1d9278>
streams: 10, words: 5525
worklib.oc8051_op_select:v <0x6dcc019b>
streams: 25, words: 14949
worklib.oc8051_pc:v <0x07ddc3c8>
streams: 19, words: 25611
worklib.oc8051_ports:v <0x0c7b97ea>
streams: 36, words: 32841
worklib.oc8051_psw:v <0x0ba437aa>
streams: 18, words: 16488
worklib.oc8051_ram:v <0x276638b3>
streams: 8, words: 4982
worklib.oc8051_ram_rd_sel:v <0x2da76cf3>
streams: 1, words: 1899
worklib.oc8051_ram_sel:v <0x2c8f228b>
streams: 2, words: 4403
worklib.oc8051_ram_top:v <0x4b18fe14>
streams: 10, words: 8226
worklib.oc8051_ram_wr_sel:v <0x61b65dfb>
streams: 10, words: 4203
worklib.oc8051_reg1:v <0x5eeb0e90>
streams: 3, words: 1141
worklib.oc8051_reg2:v <0x33db6894>
streams: 3, words: 1203
worklib.oc8051_reg3:v <0x68157157>
streams: 3, words: 1203
worklib.oc8051_reg3:v <0x788a669a>
streams: 3, words: 1339
worklib.oc8051_reg4:v <0x6ea93a4e>
streams: 3, words: 1211
worklib.oc8051_reg8:v <0x6d379d10>
streams: 3, words: 1203
worklib.oc8051_reg8:v <0x7dac9253>
streams: 3, words: 1335
worklib.oc8051_rom:v <0x08c719d5>
streams: 7, words: 3947
worklib.oc8051_rom_addr_sel:v <0x6c560c33>
streams: 1, words: 608
worklib.oc8051_sp:v <0x7c2e5f6c>
streams: 13, words: 7484
worklib.oc8051_tb:v <0x577c1173>
streams: 23, words: 11573
worklib.oc8051_tc:v <0x3c6915f1>
streams: 44, words: 32060
worklib.oc8051_top:v <0x5117fb59>
streams: 4, words: 1620
worklib.oc8051_uart:v <0x5c872655>
streams: 135, words: 100926
worklib.oc8051_uart_test:v <0x0cbc1f71>
streams: 8, words: 3386
worklib.oc8051_xram:v <0x322d2b1f>
streams: 8, words: 5421
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 51 39
Registers: 213 181
Scalar wires: 73 -
Expanded wires: 80 8
Vectored wires: 121 -
Always blocks: 114 94
Initial blocks: 6 6
Cont. assignments: 69 91
Pseudo assignments: 20 20
Simulation timescale: 10ps
Writing initial simulation snapshot: worklib.oc8051_tb:v
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