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https://opencores.org/ocsvn/8051/8051/trunk
Subversion Repositories 8051
[/] [8051/] [tags/] [rel_1/] [sim/] [rtl_sim/] [run/] [make] - Rev 57
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../../../bench/verilog/oc8051_tb.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src1_sel.v ../../../rtl/verilog/oc8051_alu_src2_sel.v ../../../rtl/verilog/oc8051_alu_src3_sel.v ../../../rtl/verilog/oc8051_alu.v ../../../rtl/verilog/oc8051_decoder.v ../../../rtl/verilog/oc8051_divide.v ../../../rtl/verilog/oc8051_immediate_sel.v ../../../rtl/verilog/oc8051_multiply.v ../../../rtl/verilog/oc8051_op_select.v ../../../rtl/verilog/oc8051_pc.v ../../../rtl/verilog/oc8051_reg8.v ../../../rtl/verilog/oc8051_reg2.v ../../../rtl/verilog/oc8051_reg1.v ../../../rtl/verilog/oc8051_reg4.v ../../../rtl/verilog/oc8051_ram_wr_sel.v ../../../rtl/verilog/oc8051_ram_rd_sel.v ../../../rtl/verilog/oc8051_ram_top.v ../../../sim/rtl_sim/src/verilog/oc8051_xram.v ../../../sim/rtl_sim/src/verilog/oc8051_ram.v ../../../rtl/verilog/oc8051_acc.v ../../../rtl/verilog/oc8051_comp.v ../../../rtl/verilog/oc8051_sp.v ../../../sim/rtl_sim/src/verilog/oc8051_uart_test.v ../../../sim/rtl_sim/src/verilog/oc8051_rom.v ../
../../sim/rtl_sim/src/verilog/oc8051_xrom.v ../../../rtl/verilog/oc8051_dptr.v ../../../rtl/verilog/oc8051_cy_select.v ../../../rtl/verilog/oc8051_psw.v ../../../rtl/verilog/oc8051_indi_addr.v ../../../rtl/verilog/oc8051_rom_addr_sel.v ../../../rtl/verilog/oc8051_ext_addr_sel.v ../../../rtl/verilog/oc8051_reg3.v ../../../rtl/verilog/oc8051_ram_sel.v ../../../rtl/verilog/oc8051_ports.v ../../../rtl/verilog/oc8051_b_register.v ../../../rtl/verilog/oc8051_uart.v ../../../rtl/verilog/oc8051_int.v ../../../rtl/verilog/oc8051_tc.v
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