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https://opencores.org/ocsvn/8051/8051/trunk
Subversion Repositories 8051
[/] [8051/] [tags/] [rel_1/] [sim/] [rtl_sim/] [run/] [run] - Rev 186
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#!/bin/csh -f
set failedi = 0;
set failedx = 0;
set all_testsi = 0;
set all_testsx = 0;
set internal_tests=(testall lcall negcnt gcd int2bin cast divmul fib sort sqroot div16u test_xram xram_m timer_test counter_test timer2_test interrupt_test serial_test r_bank)
set external_tests=(testall lcall negcnt gcd int2bin cast divmul fib sort sqroot div16u test_xram xram_m interrupt_test r_bank xrom_test)
# Prepare all .args files
iteration:
echo ""
echo ""
echo " preparing files"
echo ""
ncprep -f make > ../out/ncprep.out
if (`tail -1 ../out/ncprep.out | grep Failed` != "") then
echo ""
cat ../out/ncprep.out
exit
endif
# Run NC-Verilog compiler
echo ""
echo "\t@@@"
echo "\t@@@ Compiling sources"
echo "\t@@@"
ncvlog -NOCOPYRIGHT -f ncvlog.args > ../out/ncvlog.out
if ($status != 0) then
echo "\t@@@ FAILED"
echo ""
cat ../out/ncvlog.out
exit
else
echo "\t@@@ Passed"
endif
# Run the NC-Verilog elaborator (build the design hierarchy)
echo ""
echo "\t@@@"
echo "\t@@@ Building design hierarchy (elaboration)"
echo "\t@@@"
ncelab -NOTIMINGCHECKS -NOCOPYRIGHT -f ncelab.args > ../out/ncelab.out
if ($status != 0) then
echo "\t@@@ FAILED"
echo ""
cat ../out/ncelab.out
exit
else
echo "\t@@@ Passed"
endif
# Run the NC-Verilog simulator (simulate the design)
echo ""
echo "\t@@@"
echo "\t@@@ Tesing programs from internal rom"
echo "\t@@@"
cp ../oc8051_eai.in ../oc8051_ea.in
set i = 0;
foreach internal_test ($internal_tests)
@ i += 1;
echo ""
echo "\t###"
echo "\t### Running test ${i}: ${internal_test}"
echo "\t###"
cp ../../../asm/in/${internal_test}.in ../../../asm/in/oc8051_rom.in
cp ../../../asm/vec/${internal_test}.vec ../../../asm/vec/oc8051_test.vec
ncsim -NOCOPYRIGHT -f ncsim.args > ../out/ncsim.out
if ($status != 0) then
cat ../out/ncsim.out
exit
else if (`tail -4 ../out/ncsim.out | grep Done` == "") then
echo "\t### FAILED"
@ failedi += 1;
@ all_testsi += 1;
else
echo "\t### Passed"
@ all_testsi += 1;
endif
mv ../out/ncsim.out ../out/${internal_test}.out
end
echo ""
echo "\t@@@"
echo "\t@@@ tesing programs from external rom"
echo "\t@@@"
cp ../oc8051_eax.in ../oc8051_ea.in
set i = 0;
foreach external_test ($external_tests)
@ i += 1;
echo ""
echo "\t###"
echo "\t### Running test ${i}: ${external_test}"
echo "\t###"
cp ../../../asm/in/${external_test}.in ../../../asm/in/oc8051_xrom.in
cp ../../../asm/vec/${external_test}.vec ../../../asm/vec/oc8051_test.vec
cp ../oc8051_eax.in ../oc8051_ea.in
ncsim -NOCOPYRIGHT -f ncsim.args > ../out/ncsim.out
if ($status != 0) then
cat ../out/ncsim.out
exit
else if (`tail -4 ../out/ncsim.out | grep Done` == "") then
echo "\t### FAILED"
@ failedx += 1;
@ all_testsx += 1;
else
echo "\t### Passed"
@ all_testsx += 1;
endif
mv ../out/ncsim.out ../out/x_${external_test}.out
end
echo ""
echo "\t###"
echo "\t### Failed $failedi of $all_testsi internal tests"
echo "\t###"
echo "\t### Failed $failedx of $all_testsx external tests"
echo "\t###"
rm cds.lib hdl.var RUN_NC
rm nc*
rm -r INCA_libs