Subversion Repositories 8051

#-- Synplicity, Inc.
#-- Version 7.2        
#-- Project file /shared/projects/oc8051/simont/oc8051/syn/synplify/oc8051.prj
#-- Written on Thu Jun  5 11:22:01 2003


#add_file options
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_rom.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_acc.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_alu.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_alu_src_sel.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_b_register.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_comp.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_cy_select.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_decoder.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/memory/xilinx/rom_32x1/rom_32x1.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_defines.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_divide.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_dptr.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_icache.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_indi_addr.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_int.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_memory_interface.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_multiply.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_ports.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_psw.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_ram_top.v"
add_file -verilog "../../rtl/verilog/oc8051_sfr.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_sp.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_tc.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_tc2.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_timescale.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_top.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_uart.v"
add_file -verilog "/shared/projects/oc8051/simont/oc8051/rtl/verilog/oc8051_wb_iinterface.v"
add_file -verilog "/shared/projects/oc8051/simont/common/generic_memories/rtl/verilog/generic_dpram.v"


#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology VIRTEX
set_option -part XCV800
set_option -package BG432
set_option -speed_grade -6

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -use_fsm_explorer 0
set_option -top_module "oc8051_top"

#map options
set_option -frequency 30.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -modular 0
set_option -retiming 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/oc8051.edf"

#implementation attributes
set_option -vlog_std v2001
set_option -compiler_compatible 0
set_option -num_critical_paths 5
impl -active "rev_1"