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https://opencores.org/ocsvn/8051/8051/trunk
Subversion Repositories 8051
[/] [8051/] [tags/] [rel_2/] [sim/] [rtl_sim/] [run/] [run_sim.scr] - Rev 186
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#!/bin/csh -f if ( $# < 1 ) then echo "First argument must be a top level module name!" exit else set SIM_TOP = $1 endif set current_par = 1 set output_waveform = 0 while ( $current_par < $# ) @ current_par = $current_par + 1 case wave: @ output_waveform = 1 breaksw default: echo 'Unknown option "'$argv[$current_par]'"!' exit breaksw endsw end echo "-CDSLIB ../bin/cds.lib" > ncvlog.args echo "-HDLVAR ../bin/hdl.var" >> ncvlog.args echo "-MESSAGES" >> ncvlog.args echo "-INCDIR ../../../bench/verilog" >> ncvlog.args echo "-INCDIR ../../../rtl/verilog" >> ncvlog.args echo "-NOCOPYRIGHT" >> ncvlog.args echo "-LOGFILE ../log/ncvlog.log" >> ncvlog.args echo "../../../bench/verilog/oc8051_tb.v " >> ncvlog.args echo "../../../bench/verilog/oc8051_xram.v " >> ncvlog.args echo "../../../bench/verilog/oc8051_uart_test.v " >> ncvlog.args echo "../../../bench/verilog/oc8051_xrom.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_top.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_alu_src_sel.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_alu.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_decoder.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_divide.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_multiply.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_memory_interface.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_ram_top.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_acc.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_comp.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_sp.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_dptr.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_cy_select.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_psw.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_indi_addr.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_ports.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_b_register.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_uart.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_int.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_tc.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_tc2.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_icache.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_wb_iinterface.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_sfr.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_rom.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_ram_256x8_two_bist.v " >> ncvlog.args echo "../../../rtl/verilog/oc8051_ram_64x32_dual_bist.v " >> ncvlog.args echo "../../../../common/generic_memories/rtl/verilog/generic_dpram.v" >> ncvlog.args ncvlog -f ncvlog.args echo "-MESSAGES" > ncelab.args echo "-NOCOPYRIGHT" >> ncelab.args echo "-CDSLIB ../bin/cds.lib" >> ncelab.args echo "-HDLVAR ../bin/hdl.var" >> ncelab.args echo "-LOGFILE ../log/ncelab.log" >> ncelab.args echo "-SNAPSHOT worklib.bench:rtl" >> ncelab.args echo "-NO_TCHK_MSG" >> ncelab.args echo "-ACCESS +RWC" >> ncelab.args echo worklib.$SIM_TOP >> ncelab.args ncelab -f ncelab.args echo "-MESSAGES" > ncsim.args echo "-NOCOPYRIGHT" >> ncsim.args echo "-CDSLIB ../bin/cds.lib" >> ncsim.args echo "-HDLVAR ../bin/hdl.var" >> ncsim.args echo "-INPUT ncsim.tcl" >> ncsim.args echo "-LOGFILE ../log/ncsim.log" >> ncsim.args echo "worklib.bench:rtl" >> ncsim.args if ( $output_waveform ) then echo "database -open waves -shm -into ../out/waves.shm" > ./ncsim.tcl echo "probe -create -database waves $SIM_TOP -shm -all -depth all" >> ./ncsim.tcl echo "run" >> ./ncsim.tcl else echo "run" > ./ncsim.tcl endif echo "quit" >> ncsim.tcl ncsim -LICQUEUE -f ./ncsim.args