Subversion Repositories 8051

;
        mov tcon, #0afh         ;
        setb scon.0             ;
        mov 7fh, #007h          ; error 7
        mov a, #005h            ;
        acall wait              ;
        mov a, #01fh            ;
        acall test              ;
        mov 7fh, #008h          ; error 8
        mov a, #005h            ;
        acall test_tcon         ;

        mov p0, #001h           ;
;
; interrupt prioriti test
;
        mov b,#000h             ;
        mov ie, #08fh           ;
        mov ip, #003h           ;
        mov 20, #00ch           ;
        mov tcon, #0afh         ;
        mov 7fh, #009h          ; error 9
        mov a, #005h            ;
        acall wait              ;
        mov a, #00fh            ;
        acall test              ;
        mov 7fh, #00ah          ; error a
        mov a, #005h            ;
        acall test_tcon         ;

        mov b,#000h             ;
        mov ip, #00ch           ;
        mov 20, #003h           ;
        mov tcon, #0afh         ;
        mov 7fh, #00bh          ; error b
        mov a, #005h            ;
        acall wait              ;
        mov a, #00fh            ;
        acall test              ;
        mov 7fh, #00ch          ; error c
        mov a, #005h            ;
        acall test_tcon         ;

        mov p0, #002h           ;

///
/// created by oc8051 rom maker
/// author: Simon Teran (simont@opencores.org)
///
/// source file: D:\tmp\asm\TEMP\r_bank.hex
/// date: 16.7.02
/// time: 21:34:07
///

module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);

parameter INT_ROM_WID= 7;

input rst, clk;
input [15:0] addr;
output ea_int;
output [7:0] data1, data2, data3;
reg [7:0] data1, data2, data3;
reg [7:0] buff [65535:0];
integer i;

wire ea;

assign ea = | addr[15:INT_ROM_WID];
assign ea_int = ! ea;

initial
begin
    for (i=0; i<65536; i=i+1)
      buff [i] = 8'h00;
#2

    buff [16'h00_00] = 8'h01;
    buff [16'h00_01] = 8'h09;
    buff [16'h00_02] = 8'h85;
    buff [16'h00_03] = 8'hD0;
    buff [16'h00_04] = 8'h90;
    buff [16'h00_05] = 8'h00;
    buff [16'h00_06] = 8'h00;
    buff [16'h00_07] = 8'h01;
    buff [16'h00_08] = 8'h05;
    buff [16'h00_09] = 8'hE4;
    buff [16'h00_0a] = 8'hF8;
    buff [16'h00_0b] = 8'h7C;
    buff [16'h00_0c] = 8'h40;
    buff [16'h00_0d] = 8'h75;
    buff [16'h00_0e] = 8'hD0;
    buff [16'h00_0f] = 8'h08;
    buff [16'h00_10] = 8'h78;
    buff [16'h00_11] = 8'h01;
    buff [16'h00_12] = 8'h7C;
    buff [16'h00_13] = 8'h41;
    buff [16'h00_14] = 8'h75;
    buff [16'h00_15] = 8'hD0;
    buff [16'h00_16] = 8'h10;
    buff [16'h00_17] = 8'h78;
    buff [16'h00_18] = 8'h02;
    buff [16'h00_19] = 8'h7C;
    buff [16'h00_1a] = 8'h42;
    buff [16'h00_1b] = 8'h75;
    buff [16'h00_1c] = 8'hD0;
    buff [16'h00_1d] = 8'h18;
    buff [16'h00_1e] = 8'h78;
    buff [16'h00_1f] = 8'h03;
    buff [16'h00_20] =