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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_cy_select.v] - Rev 186
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////////////////////////////////////////////////////////////////////// //// //// //// 8051 alu carry select module //// //// //// //// This file is part of the 8051 cores project //// //// http://www.opencores.org/cores/8051/ //// //// //// //// Description //// //// Multiplexer wiht whitch we select carry in alu //// //// //// //// To Do: //// //// nothing //// //// //// //// Author(s): //// //// - Simon Teran, simont@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.3 2003/04/02 11:26:21 simont // updating... // // Revision 1.2 2002/09/30 17:33:59 simont // prepared header // // // synopsys translate_off `include "oc8051_timescale.v" // synopsys translate_on `include "oc8051_defines.v" module oc8051_cy_select (cy_sel, cy_in, data_in, data_out); // // cy_sel (in) carry select, from decoder (see defines.v) [oc8051_decoder.cy_sel -r] // cy_in (in) carry input [oc8051_psw.data_out[7] ] // data_in (in) ram data input [oc8051_ram_sel.bit_out] // data_out (out) data output [oc8051_alu.srcCy] // input [1:0] cy_sel; input cy_in, data_in; output data_out; reg data_out; always @(cy_sel or cy_in or data_in) begin case (cy_sel) /* synopsys full_case parallel_case */ `OC8051_CY_0: data_out = 1'b0; `OC8051_CY_PSW: data_out = cy_in; `OC8051_CY_RAM: data_out = data_in; `OC8051_CY_1: data_out = 1'b1; endcase end endmodule