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[/] [Aquarius/] [trunk/] [verilog/] [timescale.v] - Rev 12
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//====================================================== // Aquarius Project // SuperH-2 ISA Compatible RISC CPU //------------------------------------------------------ // Module : Time Scale Definition //------------------------------------------------------ // File : timescale.v // Library : none // Description : A definition of time scale // to be included into each source. // Simulator : Icarus Verilog (Cygwin) // Synthesizer : Xilinx XST (Windows XP) // Author : Thorn Aitch (xxxx@opencores.org) //------------------------------------------------------ // Revision Number : 1 // Date of Change : 15th April 2002 // Creator : Thorn Aitch (xxxx@opencores.org) // Description : Initial Design //------------------------------------------------------ // Revision Number : 2 // Date of Change : 30th April 2003 // Modifier : Thorn Aitch // Description : Release Version 1.0 //====================================================== // Copyright (C) 2002-2003, Thorn Aitch // // Designs can be altered while keeping list of // modifications "the same as in GNU" No money can // be earned by selling the designs themselves, but // anyone can get money by selling the implementation // of the design, such as ICs based on some cores, // boards based on some schematics or Layouts, and // even GUI interfaces to text mode drivers. // "The same as GPL SW" Any update to the design // should be documented and returned to the design. // Any derivative work based on the IP should be free // under OpenIP License. Derivative work means any // update, change or improvement on the design. // Any work based on the design can be either made // free under OpenIP license or protected by any other // license. Work based on the design means any work uses // the OpenIP Licensed core as a building black without // changing anything on it with any other blocks to // produce larger design. There is NO WARRANTY on the // functionality or performance of the design on the // real hardware implementation. // On the other hand, the SuperH-2 ISA (Instruction Set // Architecture) executed by Aquarius is rigidly // the property of Renesas Corp. Then you have all // responsibility to judge if there are not any // infringements to Renesas's rights regarding your // Aquarius adoption into your design. // By adopting Aquarius, the user assumes all // responsibility for its use. // This project may cause any damages around you, for // example, loss of properties, data, money, profits, // life, or business etc. By adopting this source, // the user assumes all responsibility for its use. //====================================================== // Timescale define `timescale 1ns/100ps //====================================================== // End of Module //======================================================