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[/] [FPz8.fit.rpt] - Rev 2
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Fitter report for FPz8Thu Nov 10 23:29:55 2016Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Fitter Summary3. Fitter Settings4. Parallel Compilation5. Pin-Out File6. Fitter Resource Usage Summary7. Input Pins8. Output Pins9. I/O Bank Usage10. All Package Pins11. Output Pin Default Load For Reported TCO12. Fitter Resource Utilization by Entity13. Delay Chain Summary14. Pad To Core Delay Chain Fanout15. Control Signals16. Global & Other Fast Signals17. Non-Global High Fan-Out Signals18. Fitter RAM Summary19. Fitter DSP Block Usage Summary20. DSP Block Details21. Interconnect Usage Summary22. LAB Logic Elements23. LAB-wide Signals24. LAB Signals Sourced25. LAB Signals Sourced Out26. LAB Distinct Inputs27. Fitter Device Options28. Operating Settings and Conditions29. Estimated Delay Added for Hold Timing30. Fitter Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2010 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+-----------------------------------------------------------------------------------+; Fitter Summary ;+------------------------------------+----------------------------------------------+; Fitter Status ; Successful - Thu Nov 10 23:29:55 2016 ;; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;; Revision Name ; FPz8 ;; Top-level Entity Name ; CPU ;; Family ; Cyclone II ;; Device ; EP2C8T144C6 ;; Timing Models ; Final ;; Total logic elements ; 4,910 / 8,256 ( 59 % ) ;; Total combinational functions ; 4,872 / 8,256 ( 59 % ) ;; Dedicated logic registers ; 495 / 8,256 ( 6 % ) ;; Total registers ; 495 ;; Total pins ; 12 / 85 ( 14 % ) ;; Total virtual pins ; 0 ;; Total memory bits ; 147,456 / 165,888 ( 89 % ) ;; Embedded Multiplier 9-bit elements ; 1 / 36 ( 3 % ) ;; Total PLLs ; 0 / 2 ( 0 % ) ;+------------------------------------+----------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Settings ;+----------------------------------------------------------------------------+--------------------------------+--------------------------------+; Option ; Setting ; Default Value ;+----------------------------------------------------------------------------+--------------------------------+--------------------------------+; Device ; AUTO ; ;; Use smart compilation ; On ; Off ;; Fit Attempts to Skip ; 0 ; 0.0 ;; Fitter Effort ; Standard Fit ; Auto Fit ;; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;; Enable compact report table ; Off ; Off ;; Use TimeQuest Timing Analyzer ; Off ; Off ;; Router Timing Optimization Level ; Normal ; Normal ;; Placement Effort Multiplier ; 1.0 ; 1.0 ;; Router Effort Multiplier ; 1.0 ; 1.0 ;; Always Enable Input Buffers ; Off ; Off ;; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;; Optimize Multi-Corner Timing ; Off ; Off ;; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;; Optimize Timing ; Normal compilation ; Normal compilation ;; Optimize Timing for ECOs ; Off ; Off ;; Regenerate full fit report during ECO compiles ; Off ; Off ;; Optimize IOC Register Placement for Timing ; On ; On ;; Limit to One Fitting Attempt ; Off ; Off ;; Final Placement Optimizations ; Automatically ; Automatically ;; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;; Fitter Initial Placement Seed ; 1 ; 1 ;; PCI I/O ; Off ; Off ;; Weak Pull-Up Resistor ; Off ; Off ;; Enable Bus-Hold Circuitry ; Off ; Off ;; Auto Global Memory Control Signals ; Off ; Off ;; Auto Packed Registers ; Auto ; Auto ;; Auto Delay Chains ; On ; On ;; Auto Merge PLLs ; On ; On ;; Ignore PLL Mode When Merging PLLs ; Off ; Off ;; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;; Perform Register Duplication for Performance ; Off ; Off ;; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;; Perform Register Retiming for Performance ; Off ; Off ;; Perform Asynchronous Signal Pipelining ; Off ; Off ;; Physical Synthesis Effort Level ; Normal ; Normal ;; Auto Global Clock ; On ; On ;; Auto Global Register Control Signals ; On ; On ;; Stop After Congestion Map Generation ; Off ; Off ;; Save Intermediate Fitting Results ; Off ; Off ;; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;; Use Best Effort Settings for Compilation ; Off ; Off ;+----------------------------------------------------------------------------+--------------------------------+--------------------------------+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.+-------------------------------------+; Parallel Compilation ;+----------------------------+--------+; Processors ; Number ;+----------------------------+--------+; Number detected on machine ; 4 ;; Maximum allowed ; 1 ;+----------------------------+--------++--------------+; Pin-Out File ;+--------------+The pin-out file can be found in E:/VHDL/FPZ8/FPz8.pin.+---------------------------------------------------------------------------+; Fitter Resource Usage Summary ;+---------------------------------------------+-----------------------------+; Resource ; Usage ;+---------------------------------------------+-----------------------------+; Total logic elements ; 4,910 / 8,256 ( 59 % ) ;; -- Combinational with no register ; 4415 ;; -- Register only ; 38 ;; -- Combinational with a register ; 457 ;; ; ;; Logic element usage by number of LUT inputs ; ;; -- 4 input functions ; 3102 ;; -- 3 input functions ; 1176 ;; -- <=2 input functions ; 594 ;; -- Register only ; 38 ;; ; ;; Logic elements by mode ; ;; -- normal mode ; 4438 ;; -- arithmetic mode ; 434 ;; ; ;; Total registers* ; 495 / 8,487 ( 6 % ) ;; -- Dedicated logic registers ; 495 / 8,256 ( 6 % ) ;; -- I/O registers ; 0 / 231 ( 0 % ) ;; ; ;; Total LABs: partially or completely used ; 341 / 516 ( 66 % ) ;; User inserted logic elements ; 0 ;; Virtual pins ; 0 ;; I/O pins ; 12 / 85 ( 14 % ) ;; -- Clock pins ; 1 / 4 ( 25 % ) ;; Global signals ; 2 ;; M4Ks ; 36 / 36 ( 100 % ) ;; Total block memory bits ; 147,456 / 165,888 ( 89 % ) ;; Total block memory implementation bits ; 165,888 / 165,888 ( 100 % ) ;; Embedded Multiplier 9-bit elements ; 1 / 36 ( 3 % ) ;; PLLs ; 0 / 2 ( 0 % ) ;; Global clocks ; 2 / 8 ( 25 % ) ;; JTAGs ; 0 / 1 ( 0 % ) ;; ASMI blocks ; 0 / 1 ( 0 % ) ;; CRC blocks ; 0 / 1 ( 0 % ) ;; Average interconnect usage (total/H/V) ; 25% / 24% / 26% ;; Peak interconnect usage (total/H/V) ; 37% / 35% / 39% ;; Maximum fan-out node ; CLOCK~clkctrl ;; Maximum fan-out ; 531 ;; Highest non-global fan-out signal ; fpz8_cpu_v1:inst|Mux34~24 ;; Highest non-global fan-out ; 209 ;; Total fan-out ; 19569 ;; Average fan-out ; 3.59 ;+---------------------------------------------+-----------------------------+* Register count does not include registers inside RAM blocks or DSP blocks.+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Input Pins ;+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+; CLOCK ; 17 ; 1 ; 0 ; 9 ; 0 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; DBG_RX ; 134 ; 2 ; 9 ; 19 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; RESET ; 18 ; 1 ; 0 ; 9 ; 1 ; 2 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Output Pins ;+----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;+----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+; DBG_TX ; 137 ; 2 ; 3 ; 19 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; PAOUT[0] ; 133 ; 2 ; 9 ; 19 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; PAOUT[1] ; 52 ; 4 ; 12 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; PAOUT[2] ; 55 ; 4 ; 16 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; PAOUT[3] ; 132 ; 2 ; 9 ; 19 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; PAOUT[4] ; 57 ; 4 ; 16 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; PAOUT[5] ; 51 ; 4 ; 9 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; PAOUT[6] ; 53 ; 4 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;; PAOUT[7] ; 129 ; 2 ; 14 ; 19 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;+----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------++-----------------------------------------------------------+; I/O Bank Usage ;+----------+-----------------+---------------+--------------+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;+----------+-----------------+---------------+--------------+; 1 ; 4 / 17 ( 24 % ) ; 3.3V ; -- ;; 2 ; 5 / 23 ( 22 % ) ; 3.3V ; -- ;; 3 ; 1 / 21 ( 5 % ) ; 3.3V ; -- ;; 4 ; 5 / 24 ( 21 % ) ; 3.3V ; -- ;+----------+-----------------+---------------+--------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; All Package Pins ;+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+; 1 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;; 2 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;; 3 ; 2 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 4 ; 3 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 5 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 7 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 8 ; 18 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 9 ; 19 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 10 ; 20 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;; 11 ; 21 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;; 12 ; 22 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;; 13 ; 23 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;; 14 ; 24 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;; 15 ; 25 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;; 16 ; 26 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;; 17 ; 27 ; 1 ; CLOCK ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 18 ; 28 ; 1 ; RESET ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 20 ; 29 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;; 21 ; 30 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; 22 ; 31 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; 23 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 24 ; 32 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 25 ; 33 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 26 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 28 ; 39 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 29 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 30 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 31 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 32 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 33 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 34 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;; 35 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 36 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;; 37 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 38 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;; 39 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 40 ; 54 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 41 ; 55 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 42 ; 56 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 43 ; 57 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 44 ; 58 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 45 ; 59 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 46 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 47 ; 60 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 48 ; 61 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 49 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 50 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 51 ; 69 ; 4 ; PAOUT[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 52 ; 70 ; 4 ; PAOUT[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 53 ; 74 ; 4 ; PAOUT[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 54 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 55 ; 75 ; 4 ; PAOUT[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 56 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 57 ; 76 ; 4 ; PAOUT[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 58 ; 77 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 59 ; 78 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 60 ; 79 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 61 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 62 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 63 ; 89 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 64 ; 92 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 65 ; 93 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 66 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 67 ; 96 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 68 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 69 ; 97 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 70 ; 98 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 71 ; 99 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 72 ; 100 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 73 ; 101 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 74 ; 102 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 75 ; 105 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 76 ; 106 ; 3 ; ~LVDS54p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; 77 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 78 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 79 ; 114 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 80 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 81 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 82 ; 121 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;; 83 ; 122 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;; 84 ; 123 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;; 85 ; 124 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;; 86 ; 125 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 87 ; 126 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 88 ; 127 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; 89 ; 128 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; 90 ; 129 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; 91 ; 130 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;; 92 ; 131 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 93 ; 132 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 94 ; 133 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 95 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 96 ; 134 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 97 ; 135 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 98 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 99 ; 143 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 100 ; 149 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 101 ; 150 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 102 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 103 ; 153 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 104 ; 154 ; 3 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; 105 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 106 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;; 107 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 108 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;; 109 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 110 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;; 111 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 112 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 113 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 114 ; 157 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 115 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 116 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 117 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 118 ; 161 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 119 ; 162 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 120 ; 163 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 121 ; 164 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 122 ; 165 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 123 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 124 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 125 ; 173 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 126 ; 174 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 127 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 128 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 129 ; 180 ; 2 ; PAOUT[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 130 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 131 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; 132 ; 185 ; 2 ; PAOUT[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 133 ; 186 ; 2 ; PAOUT[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 134 ; 187 ; 2 ; DBG_RX ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 135 ; 195 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 136 ; 196 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 137 ; 197 ; 2 ; DBG_TX ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; 138 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; 139 ; 198 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; 141 ; 199 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 142 ; 200 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 143 ; 201 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; 144 ; 202 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;+----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+Note: Pin directions (input, output or bidir) are based on device operating in user mode.+-------------------------------------------------------------------------------+; Output Pin Default Load For Reported TCO ;+----------------------------------+-------+------------------------------------+; I/O Standard ; Load ; Termination Resistance ;+----------------------------------+-------+------------------------------------+; 3.3-V LVTTL ; 0 pF ; Not Available ;; 3.3-V LVCMOS ; 0 pF ; Not Available ;; 2.5 V ; 0 pF ; Not Available ;; 1.8 V ; 0 pF ; Not Available ;; 1.5 V ; 0 pF ; Not Available ;; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ;; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ;; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ;; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ;; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ;; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ;; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ;; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;; LVDS ; 0 pF ; 100 Ohm (Differential) ;; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ;; RSDS ; 0 pF ; 100 Ohm (Differential) ;; Simple RSDS ; 0 pF ; Not Available ;; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ;+----------------------------------+-------+------------------------------------+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Resource Utilization by Entity ;+-------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------+--------------+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;+-------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------+--------------+; |CPU ; 4910 (2) ; 495 (0) ; 0 (0) ; 147456 ; 36 ; 1 ; 1 ; 0 ; 12 ; 0 ; 4415 (2) ; 38 (0) ; 457 (0) ; |CPU ; work ;; |altsyncram1:inst7| ; 0 (0) ; 0 (0) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |CPU|altsyncram1:inst7 ; work ;; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |CPU|altsyncram1:inst7|altsyncram:altsyncram_component ; work ;; |altsyncram_bua1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |CPU|altsyncram1:inst7|altsyncram:altsyncram_component|altsyncram_bua1:auto_generated ; work ;; |altsyncram2:inst1| ; 24 (0) ; 2 (0) ; 0 (0) ; 131072 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (0) ; 0 (0) ; 2 (0) ; |CPU|altsyncram2:inst1 ; work ;; |altsyncram:altsyncram_component| ; 24 (0) ; 2 (0) ; 0 (0) ; 131072 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (0) ; 0 (0) ; 2 (0) ; |CPU|altsyncram2:inst1|altsyncram:altsyncram_component ; work ;; |altsyncram_lge1:auto_generated| ; 24 (2) ; 2 (2) ; 0 (0) ; 131072 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (0) ; 0 (0) ; 2 (0) ; |CPU|altsyncram2:inst1|altsyncram:altsyncram_component|altsyncram_lge1:auto_generated ; work ;; |decode_4oa:decode3| ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; |CPU|altsyncram2:inst1|altsyncram:altsyncram_component|altsyncram_lge1:auto_generated|decode_4oa:decode3 ; work ;; |mux_kib:mux2| ; 16 (16) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 2 (2) ; |CPU|altsyncram2:inst1|altsyncram:altsyncram_component|altsyncram_lge1:auto_generated|mux_kib:mux2 ; work ;; |fpz8_cpu_v1:inst| ; 4884 (4884) ; 493 (493) ; 0 (0) ; 0 ; 0 ; 1 ; 1 ; 0 ; 0 ; 0 ; 4391 (4391) ; 38 (38) ; 455 (455) ; |CPU|fpz8_cpu_v1:inst ; work ;; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |CPU|fpz8_cpu_v1:inst|lpm_mult:Mult0 ; work ;; |mult_o5t:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |CPU|fpz8_cpu_v1:inst|lpm_mult:Mult0|mult_o5t:auto_generated ; work ;+-------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------+--------------+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.+-----------------------------------------------------------------------------------+; Delay Chain Summary ;+----------+----------+---------------+---------------+-----------------------+-----+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;+----------+----------+---------------+---------------+-----------------------+-----+; CLOCK ; Input ; (0) 299 ps ; (0) 299 ps ; -- ; -- ;; RESET ; Input ; (0) 299 ps ; (0) 299 ps ; -- ; -- ;; DBG_RX ; Input ; (6) 4114 ps ; (6) 4114 ps ; -- ; -- ;; DBG_TX ; Output ; -- ; -- ; -- ; -- ;; PAOUT[7] ; Output ; -- ; -- ; -- ; -- ;; PAOUT[6] ; Output ; -- ; -- ; -- ; -- ;; PAOUT[5] ; Output ; -- ; -- ; -- ; -- ;; PAOUT[4] ; Output ; -- ; -- ; -- ; -- ;; PAOUT[3] ; Output ; -- ; -- ; -- ; -- ;; PAOUT[2] ; Output ; -- ; -- ; -- ; -- ;; PAOUT[1] ; Output ; -- ; -- ; -- ; -- ;; PAOUT[0] ; Output ; -- ; -- ; -- ; -- ;+----------+----------+---------------+---------------+-----------------------+-----++-----------------------------------------------------------------+; Pad To Core Delay Chain Fanout ;+-----------------------------------+-------------------+---------+; Source Pin / Fanout ; Pad To Core Index ; Setting ;+-----------------------------------+-------------------+---------+; CLOCK ; ; ;; RESET ; ; ;; DBG_RX ; ; ;; - fpz8_cpu_v1:inst|RXSYNC2~0 ; 0 ; 6 ;+-----------------------------------+-------------------+---------++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Control Signals ;+----------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;+----------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+; CLOCK ; PIN_17 ; 531 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ;; RESET ; PIN_18 ; 185 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ;; altsyncram2:inst1|altsyncram:altsyncram_component|altsyncram_lge1:auto_generated|decode_4oa:decode3|w_anode221w[2] ; LCCOMB_X12_Y12_N22 ; 8 ; Write enable ; no ; -- ; -- ; -- ;; altsyncram2:inst1|altsyncram:altsyncram_component|altsyncram_lge1:auto_generated|decode_4oa:decode3|w_anode221w[2]~0 ; LCCOMB_X12_Y12_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; altsyncram2:inst1|altsyncram:altsyncram_component|altsyncram_lge1:auto_generated|decode_4oa:decode3|w_anode234w[2] ; LCCOMB_X12_Y12_N20 ; 8 ; Write enable ; no ; -- ; -- ; -- ;; altsyncram2:inst1|altsyncram:altsyncram_component|altsyncram_lge1:auto_generated|decode_4oa:decode3|w_anode234w[2]~0 ; LCCOMB_X12_Y12_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; altsyncram2:inst1|altsyncram:altsyncram_component|altsyncram_lge1:auto_generated|decode_4oa:decode3|w_anode242w[2] ; LCCOMB_X12_Y12_N30 ; 8 ; Write enable ; no ; -- ; -- ; -- ;; altsyncram2:inst1|altsyncram:altsyncram_component|altsyncram_lge1:auto_generated|decode_4oa:decode3|w_anode242w[2]~0 ; LCCOMB_X12_Y12_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; altsyncram2:inst1|altsyncram:altsyncram_component|altsyncram_lge1:auto_generated|decode_4oa:decode3|w_anode250w[2] ; LCCOMB_X12_Y12_N14 ; 8 ; Write enable ; no ; -- ; -- ; -- ;; altsyncram2:inst1|altsyncram:altsyncram_component|altsyncram_lge1:auto_generated|decode_4oa:decode3|w_anode250w[2]~0 ; LCCOMB_X12_Y12_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|ALU_FLAGS.C~6 ; LCCOMB_X6_Y9_N22 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|CPU_FLAGS.F1~8 ; LCCOMB_X12_Y6_N18 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|CPU_FLAGS.H~1 ; LCCOMB_X8_Y7_N26 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|CPU_STATE~385 ; LCCOMB_X29_Y5_N22 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|DBG_UART~51 ; LCCOMB_X5_Y14_N6 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|DBG_UART~65 ; LCCOMB_X5_Y14_N14 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|Equal0~0 ; LCCOMB_X14_Y16_N24 ; 120 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|FCTL[0]~10 ; LCCOMB_X14_Y6_N20 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|IAB[0]~35 ; LCCOMB_X14_Y16_N2 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|IAB[13]~32 ; LCCOMB_X10_Y13_N8 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|IRQ0ENH[4]~2 ; LCCOMB_X12_Y3_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|IRQ0ENL[4]~2 ; LCCOMB_X12_Y3_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|MAB[11]~250 ; LCCOMB_X19_Y8_N4 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|MAB[3]~460 ; LCCOMB_X22_Y6_N4 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|MAB[7]~383 ; LCCOMB_X23_Y7_N18 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|MODB[0]~0 ; LCCOMB_X7_Y9_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|PAOUT[7]~15 ; LCCOMB_X13_Y5_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|RP[0]~45 ; LCCOMB_X12_Y3_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|RXSYNC1 ; LCFF_X7_Y16_N23 ; 18 ; Sync. clear ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|SP[0]~76 ; LCCOMB_X16_Y4_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|SP[8]~78 ; LCCOMB_X16_Y4_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|Selector121~0 ; LCCOMB_X10_Y10_N2 ; 138 ; Sync. load ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|Selector131~0 ; LCCOMB_X13_Y10_N0 ; 32 ; Sync. load ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|Selector153~0 ; LCCOMB_X10_Y7_N2 ; 25 ; Sync. load ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|Selector164~0 ; LCCOMB_X14_Y9_N16 ; 24 ; Sync. load ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|Selector189~7 ; LCCOMB_X26_Y16_N24 ; 9 ; Sync. load ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|Selector200~7 ; LCCOMB_X26_Y16_N6 ; 9 ; Sync. load ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|Selector211~10 ; LCCOMB_X26_Y16_N14 ; 9 ; Sync. load ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|Selector213~6 ; LCCOMB_X26_Y16_N28 ; 9 ; Sync. load ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|Selector221~9 ; LCCOMB_X26_Y16_N8 ; 9 ; Sync. load ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|Selector234~9 ; LCCOMB_X26_Y16_N18 ; 9 ; Sync. load ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|Selector241~4 ; LCCOMB_X24_Y16_N0 ; 9 ; Sync. load ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|Selector249~4 ; LCCOMB_X24_Y16_N14 ; 9 ; Sync. load ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_WAIT_CMD~0 ; LCCOMB_X10_Y13_N24 ; 208 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMERX[7]~1 ; LCCOMB_X6_Y14_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:DBG_UART.RXSHIFTREG[8]~0 ; LCCOMB_X6_Y15_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:DBG_UART.RX_STATE.DBGST_RECEIVING ; LCFF_X4_Y14_N13 ; 18 ; Sync. load ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:DBG_UART.SIZE[0]~2 ; LCCOMB_X9_Y13_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:DBG_UART.SIZE[6]~1 ; LCCOMB_X8_Y14_N28 ; 8 ; Sync. load ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:DBG_UART.SIZE[8]~2 ; LCCOMB_X8_Y13_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[0]~0 ; LCCOMB_X6_Y14_N28 ; 12 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:DBG_UART.TX_DATA[1]~4 ; LCCOMB_X9_Y15_N2 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15]~8 ; LCCOMB_X16_Y15_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:DEST_ADDR16[7]~11 ; LCCOMB_X17_Y12_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:DEST_ADDR16[7]~3 ; LCCOMB_X10_Y10_N0 ; 159 ; Sync. clear ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:DEST_ADDR[11]~65 ; LCCOMB_X21_Y11_N20 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:DEST_ADDR[3]~4 ; LCCOMB_X18_Y10_N30 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:DEST_ADDR[7]~1 ; LCCOMB_X15_Y9_N10 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:RESULT[3]~3 ; LCCOMB_X18_Y12_N10 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; fpz8_cpu_v1:inst|\main:RESULT[7]~5 ; LCCOMB_X6_Y9_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;; inst8 ; LCCOMB_X10_Y9_N22 ; 4 ; Write enable ; no ; -- ; -- ; -- ;+----------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------++--------------------------------------------------------------------------------------------------+; Global & Other Fast Signals ;+-------+----------+---------+----------------------+------------------+---------------------------+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;+-------+----------+---------+----------------------+------------------+---------------------------+; CLOCK ; PIN_17 ; 531 ; Global Clock ; GCLK2 ; -- ;; RESET ; PIN_18 ; 185 ; Global Clock ; GCLK1 ; -- ;+-------+----------+---------+----------------------+------------------+---------------------------++-----------------------------------------------------------------+; Non-Global High Fan-Out Signals ;+-------------------------------------------------------+---------+; Name ; Fan-Out ;+-------------------------------------------------------+---------+; fpz8_cpu_v1:inst|Mux34~24 ; 209 ;; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_WAIT_CMD~0 ; 208 ;; fpz8_cpu_v1:inst|Mux36~6 ; 189 ;; fpz8_cpu_v1:inst|\main:DEST_ADDR16[7]~3 ; 159 ;; fpz8_cpu_v1:inst|Mux37~6 ; 150 ;; fpz8_cpu_v1:inst|Mux31~6 ; 149 ;; fpz8_cpu_v1:inst|Selector121~0 ; 138 ;; fpz8_cpu_v1:inst|Mux30~18 ; 125 ;; fpz8_cpu_v1:inst|Mux35~6 ; 123 ;; fpz8_cpu_v1:inst|Mux32~6 ; 122 ;; fpz8_cpu_v1:inst|IQUEUE~0 ; 121 ;; fpz8_cpu_v1:inst|Equal0~0 ; 120 ;; fpz8_cpu_v1:inst|\main:DBG_UART.RX_STATE.DBGST_NOSYNC ; 120 ;; fpz8_cpu_v1:inst|LessThan3~0 ; 115 ;; fpz8_cpu_v1:inst|LessThan2~0 ; 100 ;; fpz8_cpu_v1:inst|Mux33~14 ; 100 ;; fpz8_cpu_v1:inst|\main:DBG_UART.SIZE[0]~0 ; 78 ;; fpz8_cpu_v1:inst|main~23 ; 74 ;; fpz8_cpu_v1:inst|\main:TEMP_OP[0] ; 73 ;; fpz8_cpu_v1:inst|Selector150~5 ; 71 ;; fpz8_cpu_v1:inst|MAB~69 ; 69 ;; fpz8_cpu_v1:inst|\main:TEMP_OP[3] ; 68 ;; fpz8_cpu_v1:inst|Selector353~11 ; 65 ;; fpz8_cpu_v1:inst|CPU_STATE~132 ; 59 ;; fpz8_cpu_v1:inst|IQUEUE~2 ; 53 ;; fpz8_cpu_v1:inst|DATAREAD~6 ; 50 ;; fpz8_cpu_v1:inst|Equal13~2 ; 49 ;; fpz8_cpu_v1:inst|\main:TEMP_OP[1] ; 47 ;; fpz8_cpu_v1:inst|\main:DBG_UART.SIZE[1]~0 ; 47 ;; fpz8_cpu_v1:inst|Mux45~1 ; 46 ;; fpz8_cpu_v1:inst|\main:TEMP_OP[2] ; 46 ;; fpz8_cpu_v1:inst|DATAREAD~43 ; 45 ;; fpz8_cpu_v1:inst|DATAREAD~37 ; 45 ;; fpz8_cpu_v1:inst|IQUEUE~3 ; 45 ;; fpz8_cpu_v1:inst|DATAREAD~49 ; 44 ;; fpz8_cpu_v1:inst|Mux38~1 ; 44 ;; fpz8_cpu_v1:inst|\main:DBG_UART.SIZE[4]~0 ; 43 ;; fpz8_cpu_v1:inst|Mux485~5 ; 42 ;; fpz8_cpu_v1:inst|DATAREAD~55 ; 42 ;; fpz8_cpu_v1:inst|\main:DBG_UART.SIZE[2]~0 ; 41 ;; fpz8_cpu_v1:inst|\main:DBG_UART.SIZE[3]~0 ; 41 ;; fpz8_cpu_v1:inst|\main:DEST_ADDR[6]~0 ; 40 ;; fpz8_cpu_v1:inst|\main:DEST_ADDR[4]~0 ; 39 ;; fpz8_cpu_v1:inst|\main:DEST_ADDR[5]~0 ; 39 ;; fpz8_cpu_v1:inst|Selector148~0 ; 39 ;; fpz8_cpu_v1:inst|\main:IQUEUE.FETCH_STATE ; 38 ;; fpz8_cpu_v1:inst|\main:WORD_DATA ; 37 ;; fpz8_cpu_v1:inst|Selector143~0 ; 37 ;; fpz8_cpu_v1:inst|Selector13~3 ; 36 ;; fpz8_cpu_v1:inst|Selector150~6 ; 36 ;+-------------------------------------------------------+---------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter RAM Summary ;+---------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;+---------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; altsyncram1:inst7|altsyncram:altsyncram_component|altsyncram_bua1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 2048 ; 8 ; -- ; -- ; yes ; no ; -- ; -- ; 16384 ; 2048 ; 8 ; -- ; -- ; 16384 ; 4 ; None ; M4K_X11_Y3, M4K_X11_Y2, M4K_X11_Y1, M4K_X11_Y4 ;; altsyncram2:inst1|altsyncram:altsyncram_component|altsyncram_lge1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 16384 ; 8 ; -- ; -- ; yes ; no ; -- ; -- ; 131072 ; 16384 ; 8 ; -- ; -- ; 131072 ; 32 ; ../../vhdl/fpz8/FPZ8_test.mif ; M4K_X27_Y7, M4K_X27_Y3, M4K_X11_Y14, M4K_X11_Y5, M4K_X27_Y1, M4K_X27_Y9, M4K_X27_Y11, M4K_X27_Y13, M4K_X27_Y17, M4K_X27_Y16, M4K_X27_Y12, M4K_X27_Y4, M4K_X11_Y9, M4K_X11_Y13, M4K_X11_Y11, M4K_X11_Y10, M4K_X11_Y16, M4K_X27_Y15, M4K_X11_Y15, M4K_X11_Y18, M4K_X27_Y5, M4K_X27_Y8, M4K_X27_Y10, M4K_X27_Y6, M4K_X11_Y17, M4K_X27_Y2, M4K_X27_Y14, M4K_X27_Y18, M4K_X11_Y7, M4K_X11_Y8, M4K_X11_Y12, M4K_X11_Y6 ;+---------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+-------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.+-----------------------------------------------------------------------------------------------+; Fitter DSP Block Usage Summary ;+---------------------------------------+-------------+---------------------+-------------------+; Statistic ; Number Used ; Available per Block ; Maximum Available ;+---------------------------------------+-------------+---------------------+-------------------+; Simple Multipliers (9-bit) ; 1 ; 2 ; 36 ;; Simple Multipliers (18-bit) ; 0 ; 1 ; 18 ;; Embedded Multiplier Blocks ; 1 ; -- ; 18 ;; Embedded Multiplier 9-bit elements ; 1 ; 2 ; 36 ;; Signed Embedded Multipliers ; 0 ; -- ; -- ;; Unsigned Embedded Multipliers ; 1 ; -- ; -- ;; Mixed Sign Embedded Multipliers ; 0 ; -- ; -- ;; Variable Sign Embedded Multipliers ; 0 ; -- ; -- ;; Dedicated Input Shift Register Chains ; 0 ; -- ; -- ;+---------------------------------------+-------------+---------------------+-------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; DSP Block Details ;+----------------------------------------------------------------------+---------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+; Name ; Mode ; Location ; Sign Representation ; Has Input Shift Register Chain ; Data A Input Register ; Data B Input Register ; Pipeline Register ; Output Register ;+----------------------------------------------------------------------+---------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+; fpz8_cpu_v1:inst|lpm_mult:Mult0|mult_o5t:auto_generated|mac_out2 ; Simple Multiplier (9-bit) ; DSPOUT_X20_Y12_N2 ; ; No ; ; ; ; no ;; fpz8_cpu_v1:inst|lpm_mult:Mult0|mult_o5t:auto_generated|mac_mult1 ; ; DSPMULT_X20_Y12_N0 ; Variable ; ; no ; no ; no ; ;+----------------------------------------------------------------------+---------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------++------------------------------------------------------+; Interconnect Usage Summary ;+----------------------------+-------------------------+; Interconnect Resource Type ; Usage ;+----------------------------+-------------------------+; Block interconnects ; 8,759 / 26,052 ( 34 % ) ;; C16 interconnects ; 77 / 1,156 ( 7 % ) ;; C4 interconnects ; 4,673 / 17,952 ( 26 % ) ;; Direct links ; 952 / 26,052 ( 4 % ) ;; Global clocks ; 2 / 8 ( 25 % ) ;; Local interconnects ; 2,682 / 8,256 ( 32 % ) ;; R24 interconnects ; 132 / 1,020 ( 13 % ) ;; R4 interconnects ; 5,359 / 22,440 ( 24 % ) ;+----------------------------+-------------------------++-----------------------------------------------------------------------------+; LAB Logic Elements ;+---------------------------------------------+-------------------------------+; Number of Logic Elements (Average = 14.40) ; Number of LABs (Total = 341) ;+---------------------------------------------+-------------------------------+; 1 ; 6 ;; 2 ; 1 ;; 3 ; 3 ;; 4 ; 3 ;; 5 ; 2 ;; 6 ; 0 ;; 7 ; 2 ;; 8 ; 6 ;; 9 ; 1 ;; 10 ; 7 ;; 11 ; 10 ;; 12 ; 11 ;; 13 ; 15 ;; 14 ; 30 ;; 15 ; 31 ;; 16 ; 213 ;+---------------------------------------------+-------------------------------++--------------------------------------------------------------------+; LAB-wide Signals ;+------------------------------------+-------------------------------+; LAB-wide Signals (Average = 1.23) ; Number of LABs (Total = 341) ;+------------------------------------+-------------------------------+; 1 Async. clear ; 77 ;; 1 Clock ; 160 ;; 1 Clock enable ; 118 ;; 1 Sync. load ; 38 ;; 2 Clock enables ; 27 ;+------------------------------------+-------------------------------++------------------------------------------------------------------------------+; LAB Signals Sourced ;+----------------------------------------------+-------------------------------+; Number of Signals Sourced (Average = 15.83) ; Number of LABs (Total = 341) ;+----------------------------------------------+-------------------------------+; 0 ; 0 ;; 1 ; 6 ;; 2 ; 1 ;; 3 ; 3 ;; 4 ; 1 ;; 5 ; 0 ;; 6 ; 2 ;; 7 ; 3 ;; 8 ; 2 ;; 9 ; 3 ;; 10 ; 5 ;; 11 ; 4 ;; 12 ; 9 ;; 13 ; 11 ;; 14 ; 19 ;; 15 ; 21 ;; 16 ; 140 ;; 17 ; 36 ;; 18 ; 19 ;; 19 ; 19 ;; 20 ; 14 ;; 21 ; 6 ;; 22 ; 4 ;; 23 ; 3 ;; 24 ; 5 ;; 25 ; 0 ;; 26 ; 0 ;; 27 ; 4 ;; 28 ; 0 ;; 29 ; 0 ;; 30 ; 1 ;+----------------------------------------------+-------------------------------++---------------------------------------------------------------------------------+; LAB Signals Sourced Out ;+-------------------------------------------------+-------------------------------+; Number of Signals Sourced Out (Average = 8.86) ; Number of LABs (Total = 341) ;+-------------------------------------------------+-------------------------------+; 0 ; 0 ;; 1 ; 10 ;; 2 ; 6 ;; 3 ; 15 ;; 4 ; 14 ;; 5 ; 21 ;; 6 ; 28 ;; 7 ; 31 ;; 8 ; 44 ;; 9 ; 40 ;; 10 ; 21 ;; 11 ; 17 ;; 12 ; 23 ;; 13 ; 21 ;; 14 ; 18 ;; 15 ; 13 ;; 16 ; 19 ;+-------------------------------------------------+-------------------------------++------------------------------------------------------------------------------+; LAB Distinct Inputs ;+----------------------------------------------+-------------------------------+; Number of Distinct Inputs (Average = 23.24) ; Number of LABs (Total = 341) ;+----------------------------------------------+-------------------------------+; 0 ; 0 ;; 1 ; 0 ;; 2 ; 1 ;; 3 ; 0 ;; 4 ; 6 ;; 5 ; 2 ;; 6 ; 1 ;; 7 ; 0 ;; 8 ; 1 ;; 9 ; 3 ;; 10 ; 1 ;; 11 ; 5 ;; 12 ; 8 ;; 13 ; 4 ;; 14 ; 6 ;; 15 ; 8 ;; 16 ; 7 ;; 17 ; 17 ;; 18 ; 9 ;; 19 ; 13 ;; 20 ; 11 ;; 21 ; 12 ;; 22 ; 14 ;; 23 ; 9 ;; 24 ; 28 ;; 25 ; 22 ;; 26 ; 24 ;; 27 ; 27 ;; 28 ; 19 ;; 29 ; 20 ;; 30 ; 23 ;; 31 ; 23 ;; 32 ; 17 ;+----------------------------------------------+-------------------------------++-------------------------------------------------------------------------+; Fitter Device Options ;+----------------------------------------------+--------------------------+; Option ; Setting ;+----------------------------------------------+--------------------------+; Enable user-supplied start-up clock (CLKUSR) ; Off ;; Enable device-wide reset (DEV_CLRn) ; Off ;; Enable device-wide output enable (DEV_OE) ; Off ;; Enable INIT_DONE output ; Off ;; Configuration scheme ; Active Serial ;; Error detection CRC ; Off ;; nCEO ; As output driving ground ;; ASDO,nCSO ; As input tri-stated ;; Reserve all unused pins ; As output driving ground ;; Base pin-out file on sameframe device ; Off ;+----------------------------------------------+--------------------------++------------------------------------+; Operating Settings and Conditions ;+---------------------------+--------+; Setting ; Value ;+---------------------------+--------+; Nominal Core Voltage ; 1.20 V ;+---------------------------+--------++------------------------------------------------------------+; Estimated Delay Added for Hold Timing ;+-----------------+----------------------+-------------------+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;+-----------------+----------------------+-------------------++-----------------+; Fitter Messages ;+-----------------+Info: *******************************************************************Info: Running Quartus II FitterInfo: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web EditionInfo: Processing started: Thu Nov 10 23:29:22 2016Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off FPz8 -c FPz8Info: Automatically selected device EP2C8T144C6 for design FPz8Info: Fitting design with smaller device may be possible, but smaller device must be specifiedInfo: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performanceWarning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devicesInfo: Device EP2C5T144C6 is compatibleInfo: Fitter converted 3 user pins into dedicated programming pinsInfo: Pin ~ASDO~ is reserved at location 1Info: Pin ~nCSO~ is reserved at location 2Info: Pin ~LVDS54p/nCEO~ is reserved at location 76Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.Critical Warning: No exact pin location assignment(s) for 12 pins of 12 total pinsInfo: Pin DBG_TX not assigned to an exact location on the deviceInfo: Pin PAOUT[7] not assigned to an exact location on the deviceInfo: Pin PAOUT[6] not assigned to an exact location on the deviceInfo: Pin PAOUT[5] not assigned to an exact location on the deviceInfo: Pin PAOUT[4] not assigned to an exact location on the deviceInfo: Pin PAOUT[3] not assigned to an exact location on the deviceInfo: Pin PAOUT[2] not assigned to an exact location on the deviceInfo: Pin PAOUT[1] not assigned to an exact location on the deviceInfo: Pin PAOUT[0] not assigned to an exact location on the deviceInfo: Pin CLOCK not assigned to an exact location on the deviceInfo: Pin RESET not assigned to an exact location on the deviceInfo: Pin DBG_RX not assigned to an exact location on the deviceInfo: Timing-driven compilation is using the Classic Timing AnalyzerInfo: Timing requirements not specified -- optimizing circuit to achieve the following default global requirementsInfo: Assuming a global fmax requirement of 1000 MHzInfo: Not setting a global tsu requirementInfo: Not setting a global tco requirementInfo: Not setting a global tpd requirementInfo: Automatically promoted node CLOCK (placed in PIN 17 (CLK0, LVDSCLK0p, Input))Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2Info: Automatically promoted node RESET (placed in PIN 18 (CLK1, LVDSCLK0n, Input))Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1Info: Following destination nodes may be non-global or may not use global or regional clocksInfo: Destination node fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_WAIT_CMD~0Info: Starting register packingExtra Info: Performing register packing on registers with non-logic cell location assignmentsExtra Info: Completed register packing on registers with non-logic cell location assignmentsExtra Info: Started Fast Input/Output/OE register processingExtra Info: Finished Fast Input/Output/OE register processingExtra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and densityExtra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocksInfo: Finished register packingExtra Info: No registers were packed into other blocksInfo: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placementInfo: Number of I/O pins in group: 10 (unused VREF, 3.3V VCCIO, 1 input, 9 output, 0 bidirectional)Info: I/O standards used: 3.3-V LVTTL.Info: I/O bank details before I/O pin placementInfo: Statistics of I/O banksInfo: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 13 pins availableInfo: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 23 pins availableInfo: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 20 pins availableInfo: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 24 pins availableInfo: Fitter preparation operations ending: elapsed time is 00:00:01Info: Fitter placement preparation operations beginningInfo: Fitter placement preparation operations ending: elapsed time is 00:00:03Info: Fitter placement operations beginningInfo: Fitter placement was successfulInfo: Fitter placement operations ending: elapsed time is 00:00:12Info: Estimated most critical path is register to register delay of 28.406 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y14; Fanout = 2; REG Node = 'fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1]'Info: 2: + IC(0.203 ns) + CELL(0.420 ns) = 0.623 ns; Loc. = LAB_X14_Y14; Fanout = 4; COMB Node = 'fpz8_cpu_v1:inst|Equal2~0'Info: 3: + IC(1.635 ns) + CELL(0.414 ns) = 2.672 ns; Loc. = LAB_X5_Y15; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add5~1'Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 2.743 ns; Loc. = LAB_X5_Y15; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add5~3'Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 2.814 ns; Loc. = LAB_X5_Y15; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add5~5'Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 2.885 ns; Loc. = LAB_X5_Y15; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add5~7'Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 2.956 ns; Loc. = LAB_X5_Y15; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add5~9'Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 3.366 ns; Loc. = LAB_X5_Y15; Fanout = 6; COMB Node = 'fpz8_cpu_v1:inst|Add5~10'Info: 9: + IC(0.625 ns) + CELL(0.415 ns) = 4.406 ns; Loc. = LAB_X5_Y16; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Equal5~4'Info: 10: + IC(0.317 ns) + CELL(0.437 ns) = 5.160 ns; Loc. = LAB_X4_Y16; Fanout = 1; COMB Node = 'fpz8_cpu_v1:inst|Equal5~6'Info: 11: + IC(0.605 ns) + CELL(0.150 ns) = 5.915 ns; Loc. = LAB_X3_Y16; Fanout = 17; COMB Node = 'fpz8_cpu_v1:inst|Equal5~7'Info: 12: + IC(0.415 ns) + CELL(0.150 ns) = 6.480 ns; Loc. = LAB_X3_Y16; Fanout = 1; COMB Node = 'fpz8_cpu_v1:inst|Selector189~4'Info: 13: + IC(1.112 ns) + CELL(0.150 ns) = 7.742 ns; Loc. = LAB_X9_Y16; Fanout = 12; COMB Node = 'fpz8_cpu_v1:inst|Selector189~5'Info: 14: + IC(1.353 ns) + CELL(0.438 ns) = 9.533 ns; Loc. = LAB_X24_Y16; Fanout = 10; COMB Node = 'fpz8_cpu_v1:inst|Mux34~11'Info: 15: + IC(0.290 ns) + CELL(0.275 ns) = 10.098 ns; Loc. = LAB_X24_Y16; Fanout = 8; COMB Node = 'fpz8_cpu_v1:inst|Mux34~12'Info: 16: + IC(1.042 ns) + CELL(0.275 ns) = 11.415 ns; Loc. = LAB_X28_Y13; Fanout = 149; COMB Node = 'fpz8_cpu_v1:inst|Mux31~6'Info: 17: + IC(0.127 ns) + CELL(0.437 ns) = 11.979 ns; Loc. = LAB_X28_Y13; Fanout = 1; COMB Node = 'fpz8_cpu_v1:inst|Mux485~3'Info: 18: + IC(0.290 ns) + CELL(0.275 ns) = 12.544 ns; Loc. = LAB_X28_Y13; Fanout = 1; COMB Node = 'fpz8_cpu_v1:inst|Mux485~4'Info: 19: + IC(0.415 ns) + CELL(0.150 ns) = 13.109 ns; Loc. = LAB_X28_Y13; Fanout = 42; COMB Node = 'fpz8_cpu_v1:inst|Mux485~5'Info: 20: + IC(0.624 ns) + CELL(0.393 ns) = 14.126 ns; Loc. = LAB_X29_Y12; Fanout = 13; COMB Node = 'fpz8_cpu_v1:inst|IQUEUE~15'Info: 21: + IC(0.607 ns) + CELL(0.438 ns) = 15.171 ns; Loc. = LAB_X29_Y13; Fanout = 1; COMB Node = 'fpz8_cpu_v1:inst|Mux801~0'Info: 22: + IC(0.290 ns) + CELL(0.271 ns) = 15.732 ns; Loc. = LAB_X29_Y13; Fanout = 7; COMB Node = 'fpz8_cpu_v1:inst|Mux801~1'Info: 23: + IC(0.618 ns) + CELL(0.438 ns) = 16.788 ns; Loc. = LAB_X29_Y15; Fanout = 4; COMB Node = 'fpz8_cpu_v1:inst|Equal76~1'Info: 24: + IC(0.911 ns) + CELL(0.150 ns) = 17.849 ns; Loc. = LAB_X29_Y12; Fanout = 10; COMB Node = 'fpz8_cpu_v1:inst|Equal75~0'Info: 25: + IC(0.607 ns) + CELL(0.438 ns) = 18.894 ns; Loc. = LAB_X30_Y11; Fanout = 5; COMB Node = 'fpz8_cpu_v1:inst|NUM_BYTES~24'Info: 26: + IC(0.415 ns) + CELL(0.150 ns) = 19.459 ns; Loc. = LAB_X30_Y11; Fanout = 1; COMB Node = 'fpz8_cpu_v1:inst|NUM_BYTES~27'Info: 27: + IC(0.607 ns) + CELL(0.438 ns) = 20.504 ns; Loc. = LAB_X29_Y10; Fanout = 3; COMB Node = 'fpz8_cpu_v1:inst|NUM_BYTES~31'Info: 28: + IC(0.605 ns) + CELL(0.150 ns) = 21.259 ns; Loc. = LAB_X30_Y10; Fanout = 1; COMB Node = 'fpz8_cpu_v1:inst|NUM_BYTES~59'Info: 29: + IC(0.895 ns) + CELL(0.149 ns) = 22.303 ns; Loc. = LAB_X29_Y11; Fanout = 1; COMB Node = 'fpz8_cpu_v1:inst|NUM_BYTES~114'Info: 30: + IC(0.145 ns) + CELL(0.420 ns) = 22.868 ns; Loc. = LAB_X29_Y11; Fanout = 1; COMB Node = 'fpz8_cpu_v1:inst|NUM_BYTES~63'Info: 31: + IC(0.145 ns) + CELL(0.419 ns) = 23.432 ns; Loc. = LAB_X29_Y11; Fanout = 1; COMB Node = 'fpz8_cpu_v1:inst|NUM_BYTES~91'Info: 32: + IC(0.127 ns) + CELL(0.438 ns) = 23.997 ns; Loc. = LAB_X29_Y11; Fanout = 7; COMB Node = 'fpz8_cpu_v1:inst|NUM_BYTES~92'Info: 33: + IC(1.676 ns) + CELL(0.414 ns) = 26.087 ns; Loc. = LAB_X15_Y14; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add33~1'Info: 34: + IC(0.000 ns) + CELL(0.071 ns) = 26.158 ns; Loc. = LAB_X15_Y14; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add33~3'Info: 35: + IC(0.000 ns) + CELL(0.071 ns) = 26.229 ns; Loc. = LAB_X15_Y14; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add33~5'Info: 36: + IC(0.000 ns) + CELL(0.071 ns) = 26.300 ns; Loc. = LAB_X15_Y14; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add33~7'Info: 37: + IC(0.000 ns) + CELL(0.071 ns) = 26.371 ns; Loc. = LAB_X15_Y14; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add33~9'Info: 38: + IC(0.000 ns) + CELL(0.071 ns) = 26.442 ns; Loc. = LAB_X15_Y14; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add33~11'Info: 39: + IC(0.000 ns) + CELL(0.071 ns) = 26.513 ns; Loc. = LAB_X15_Y14; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add33~13'Info: 40: + IC(0.000 ns) + CELL(0.071 ns) = 26.584 ns; Loc. = LAB_X15_Y14; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add33~15'Info: 41: + IC(0.000 ns) + CELL(0.071 ns) = 26.655 ns; Loc. = LAB_X15_Y14; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add33~17'Info: 42: + IC(0.000 ns) + CELL(0.071 ns) = 26.726 ns; Loc. = LAB_X15_Y14; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add33~19'Info: 43: + IC(0.000 ns) + CELL(0.071 ns) = 26.797 ns; Loc. = LAB_X15_Y14; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add33~21'Info: 44: + IC(0.000 ns) + CELL(0.071 ns) = 26.868 ns; Loc. = LAB_X15_Y14; Fanout = 2; COMB Node = 'fpz8_cpu_v1:inst|Add33~23'Info: 45: + IC(0.000 ns) + CELL(0.410 ns) = 27.278 ns; Loc. = LAB_X15_Y14; Fanout = 1; COMB Node = 'fpz8_cpu_v1:inst|Add33~24'Info: 46: + IC(0.625 ns) + CELL(0.419 ns) = 28.322 ns; Loc. = LAB_X16_Y13; Fanout = 1; COMB Node = 'fpz8_cpu_v1:inst|Selector443~4'Info: 47: + IC(0.000 ns) + CELL(0.084 ns) = 28.406 ns; Loc. = LAB_X16_Y13; Fanout = 3; REG Node = 'fpz8_cpu_v1:inst|\main:PC[12]'Info: Total cell delay = 11.080 ns ( 39.01 % )Info: Total interconnect delay = 17.326 ns ( 60.99 % )Info: Fitter routing operations beginningInfo: Average interconnect usage is 22% of the available device resourcesInfo: Peak interconnect usage is 32% of the available device resources in the region that extends from location X11_Y0 to location X22_Y9Info: Fitter routing operations ending: elapsed time is 00:00:10Info: Started post-fitting delay annotationWarning: Found 9 output pins without output pin load capacitance assignmentInfo: Pin "DBG_TX" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "PAOUT[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "PAOUT[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "PAOUT[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "PAOUT[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "PAOUT[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "PAOUT[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "PAOUT[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "PAOUT[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Delay annotation completed successfullyInfo: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.Info: Quartus II Fitter was successful. 0 errors, 4 warningsInfo: Peak virtual memory: 265 megabytesInfo: Processing ended: Thu Nov 10 23:29:56 2016Info: Elapsed time: 00:00:34Info: Total CPU time (on all processors): 00:00:32