Subversion Repositories fpz8

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors.  Please refer to the
# applicable agreement for further details.


# The default values for assignments are stored in the file
#               FPz8_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#               assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE AUTO
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY CPU
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:50:09  NOVEMBER 03, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
set_global_assignment -name INCREMENTAL_COMPILATION OFF
set_global_assignment -name BDF_FILE CPU.bdf
set_global_assignment -name MISC_FILE "E:/VHDL/AHMES_IO2/AHMES.dpf"
set_global_assignment -name VECTOR_WAVEFORM_FILE cpu.vwf
set_global_assignment -name VHDL_FILE fpz8_cpu_v1.vhd
set_global_assignment -name QIP_FILE altsyncram0.qip
set_global_assignment -name MIF_FILE FPZ8_test.mif
set_global_assignment -name QIP_FILE altsyncram1.qip
set_global_assignment -name END_TIME "500 ns"
set_global_assignment -name QIP_FILE altsyncram2.qip
set_global_assignment -name MIF_FILE FPZ8_test_LDX_IRR2_IR1.mif
set_global_assignment -name MIF_FILE FPZ8_test_DJNZ_JR.mif
set_global_assignment -name MIF_FILE FPZ8_test_CALL_RET.mif
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE cpu.vwf
set_global_assignment -name MIF_FILE FPZ8_test_INTERRUPT.mif
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name MIF_FILE FPZ8_test_TRAP.mif
set_global_assignment -name MIF_FILE FPZ8_test_LDC.mif
set_global_assignment -name MIF_FILE FPZ8_test_LDCI.mif
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name SOURCE_FILE altsyncram0.cmp
set_global_assignment -name VHDL_FILE altsyncram0.vhd
set_global_assignment -name SOURCE_FILE altsyncram1.cmp
set_global_assignment -name VHDL_FILE altsyncram1.vhd
set_global_assignment -name SOURCE_FILE altsyncram2.cmp
set_global_assignment -name VHDL_FILE altsyncram2.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF