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[/] [FPz8_Cyclone_IV.sta.rpt] - Rev 2
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TimeQuest Timing Analyzer report for FPz8_Cyclone_IVFri Nov 11 10:25:14 2016Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. TimeQuest Timing Analyzer Summary3. Parallel Compilation4. SDC File List5. Clocks6. Slow 1200mV 85C Model Fmax Summary7. Slow 1200mV 85C Model Setup Summary8. Slow 1200mV 85C Model Hold Summary9. Slow 1200mV 85C Model Recovery Summary10. Slow 1200mV 85C Model Removal Summary11. Slow 1200mV 85C Model Minimum Pulse Width Summary12. Slow 1200mV 85C Model Setup: 'CLOCK'13. Slow 1200mV 85C Model Hold: 'CLOCK'14. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK'15. Setup Times16. Hold Times17. Clock to Output Times18. Minimum Clock to Output Times19. Slow 1200mV 85C Model Metastability Report20. Slow 1200mV 0C Model Fmax Summary21. Slow 1200mV 0C Model Setup Summary22. Slow 1200mV 0C Model Hold Summary23. Slow 1200mV 0C Model Recovery Summary24. Slow 1200mV 0C Model Removal Summary25. Slow 1200mV 0C Model Minimum Pulse Width Summary26. Slow 1200mV 0C Model Setup: 'CLOCK'27. Slow 1200mV 0C Model Hold: 'CLOCK'28. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK'29. Setup Times30. Hold Times31. Clock to Output Times32. Minimum Clock to Output Times33. Slow 1200mV 0C Model Metastability Report34. Fast 1200mV 0C Model Setup Summary35. Fast 1200mV 0C Model Hold Summary36. Fast 1200mV 0C Model Recovery Summary37. Fast 1200mV 0C Model Removal Summary38. Fast 1200mV 0C Model Minimum Pulse Width Summary39. Fast 1200mV 0C Model Setup: 'CLOCK'40. Fast 1200mV 0C Model Hold: 'CLOCK'41. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK'42. Setup Times43. Hold Times44. Clock to Output Times45. Minimum Clock to Output Times46. Fast 1200mV 0C Model Metastability Report47. Multicorner Timing Analysis Summary48. Setup Times49. Hold Times50. Clock to Output Times51. Minimum Clock to Output Times52. Board Trace Model Assignments53. Input Transition Times54. Slow Corner Signal Integrity Metrics55. Fast Corner Signal Integrity Metrics56. Setup Transfers57. Hold Transfers58. Report TCCS59. Report RSKM60. Unconstrained Paths61. TimeQuest Timing Analyzer Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2010 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+-------------------------------------------------------------------------------------+; TimeQuest Timing Analyzer Summary ;+--------------------+----------------------------------------------------------------+; Quartus II Version ; Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition ;; Revision Name ; FPz8_Cyclone_IV ;; Device Family ; Cyclone IV E ;; Device Name ; EP4CE6E22C8 ;; Timing Models ; Preliminary ;; Delay Model ; Combined ;; Rise/Fall Delays ; Enabled ;+--------------------+----------------------------------------------------------------+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.+-------------------------------------+; Parallel Compilation ;+----------------------------+--------+; Processors ; Number ;+----------------------------+--------+; Number detected on machine ; 4 ;; Maximum allowed ; 1 ;+----------------------------+--------++-------------------------------------------------------------+; SDC File List ;+-------------------------+--------+--------------------------+; SDC File Path ; Status ; Read at ;+-------------------------+--------+--------------------------+; FPz8_Cyclone_IV.out.sdc ; OK ; Fri Nov 11 10:25:03 2016 ;+-------------------------+--------+--------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Clocks ;+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+; CLOCK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { CLOCK } ;+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------++-------------------------------------------------+; Slow 1200mV 85C Model Fmax Summary ;+-----------+-----------------+------------+------+; Fmax ; Restricted Fmax ; Clock Name ; Note ;+-----------+-----------------+------------+------+; 21.13 MHz ; 21.13 MHz ; CLOCK ; ;+-----------+-----------------+------------+------+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.+-------------------------------------+; Slow 1200mV 85C Model Setup Summary ;+-------+---------+-------------------+; Clock ; Slack ; End Point TNS ;+-------+---------+-------------------+; CLOCK ; -26.441 ; -8505.086 ;+-------+---------+-------------------++------------------------------------+; Slow 1200mV 85C Model Hold Summary ;+-------+-------+--------------------+; Clock ; Slack ; End Point TNS ;+-------+-------+--------------------+; CLOCK ; 0.432 ; 0.000 ;+-------+-------+--------------------+------------------------------------------; Slow 1200mV 85C Model Recovery Summary ;------------------------------------------No paths to report.-----------------------------------------; Slow 1200mV 85C Model Removal Summary ;-----------------------------------------No paths to report.+---------------------------------------------------+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;+-------+--------+----------------------------------+; Clock ; Slack ; End Point TNS ;+-------+--------+----------------------------------+; CLOCK ; -3.201 ; -910.432 ;+-------+--------+----------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Slow 1200mV 85C Model Setup: 'CLOCK' ;+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+; -26.441 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.081 ; 27.361 ;; -26.305 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.081 ; 27.225 ;; -25.869 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 26.788 ;; -25.822 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 26.741 ;; -25.770 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.081 ; 26.690 ;; -25.758 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 26.653 ;; -25.705 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[2] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 26.624 ;; -25.668 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.081 ; 26.588 ;; -25.631 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.092 ; 26.540 ;; -25.622 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 26.517 ;; -25.569 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 26.496 ;; -25.545 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.081 ; 26.465 ;; -25.511 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 26.430 ;; -25.493 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.104 ; 26.390 ;; -25.489 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.092 ; 26.398 ;; -25.434 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 26.329 ;; -25.433 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 26.360 ;; -25.401 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[6] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 26.320 ;; -25.396 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 26.315 ;; -25.393 ; fpz8_cpu_v1:inst|IRQ0ENH[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.091 ; 26.303 ;; -25.378 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.091 ; 26.288 ;; -25.366 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[14] ; CLOCK ; CLOCK ; 1.000 ; -0.104 ; 26.263 ;; -25.357 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.104 ; 26.254 ;; -25.355 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[0] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 26.271 ;; -25.352 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[13] ; CLOCK ; CLOCK ; 1.000 ; -0.088 ; 26.265 ;; -25.343 ; fpz8_cpu_v1:inst|IRQ0[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.093 ; 26.251 ;; -25.328 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[10] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 26.246 ;; -25.299 ; fpz8_cpu_v1:inst|IRQ0ENL[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.092 ; 26.208 ;; -25.298 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 26.193 ;; -25.260 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 26.179 ;; -25.236 ; fpz8_cpu_v1:inst|IRQ0[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.093 ; 26.144 ;; -25.232 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[7] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 26.158 ;; -25.230 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[14] ; CLOCK ; CLOCK ; 1.000 ; -0.104 ; 26.127 ;; -25.219 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[0] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 26.135 ;; -25.216 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[13] ; CLOCK ; CLOCK ; 1.000 ; -0.088 ; 26.129 ;; -25.212 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[12] ; CLOCK ; CLOCK ; 1.000 ; -0.104 ; 26.109 ;; -25.200 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 26.118 ;; -25.195 ; fpz8_cpu_v1:inst|IRQ0[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.093 ; 26.103 ;; -25.192 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[10] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 26.110 ;; -25.191 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[4] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 26.119 ;; -25.186 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 26.080 ;; -25.177 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[12] ; CLOCK ; CLOCK ; 1.000 ; -0.101 ; 26.077 ;; -25.139 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 26.033 ;; -25.132 ; fpz8_cpu_v1:inst|IRQ0[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.093 ; 26.040 ;; -25.126 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[6] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 26.053 ;; -25.121 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[14] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 26.039 ;; -25.107 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[8] ; CLOCK ; CLOCK ; 1.000 ; -0.090 ; 26.018 ;; -25.098 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[10] ; CLOCK ; CLOCK ; 1.000 ; -0.101 ; 25.998 ;; -25.096 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[7] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 26.022 ;; -25.087 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 25.982 ;; -25.076 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[12] ; CLOCK ; CLOCK ; 1.000 ; -0.104 ; 25.973 ;; -25.064 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 25.982 ;; -25.055 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[4] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 25.983 ;; -25.041 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[12] ; CLOCK ; CLOCK ; 1.000 ; -0.101 ; 25.941 ;; -25.029 ; fpz8_cpu_v1:inst|IRQ0ENL[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.093 ; 25.937 ;; -25.027 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[5] ; CLOCK ; CLOCK ; 1.000 ; -0.086 ; 25.942 ;; -25.026 ; fpz8_cpu_v1:inst|IRQ0ENH[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.091 ; 25.936 ;; -25.025 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[5] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 25.953 ;; -25.022 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[2] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 25.916 ;; -25.019 ; fpz8_cpu_v1:inst|IRQ0ENL[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.092 ; 25.928 ;; -25.013 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 25.929 ;; -25.011 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[9] ; CLOCK ; CLOCK ; 1.000 ; -0.087 ; 25.925 ;; -24.997 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 25.923 ;; -24.996 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[8] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 25.914 ;; -24.994 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[7] ; CLOCK ; CLOCK ; 1.000 ; -0.088 ; 25.907 ;; -24.990 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[6] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 25.917 ;; -24.985 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[14] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 25.903 ;; -24.985 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[5] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 25.880 ;; -24.979 ; fpz8_cpu_v1:inst|\main:CAN_FETCH ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.058 ; 25.922 ;; -24.972 ; fpz8_cpu_v1:inst|\main:IQUEUE.FULL ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 25.891 ;; -24.971 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[8] ; CLOCK ; CLOCK ; 1.000 ; -0.090 ; 25.882 ;; -24.962 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[10] ; CLOCK ; CLOCK ; 1.000 ; -0.101 ; 25.862 ;; -24.950 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 25.876 ;; -24.945 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.117 ; 25.829 ;; -24.944 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[10] ; CLOCK ; CLOCK ; 1.000 ; -0.086 ; 25.859 ;; -24.944 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[1] ; CLOCK ; CLOCK ; 1.000 ; -0.079 ; 25.866 ;; -24.926 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[8] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 25.845 ;; -24.922 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[11] ; CLOCK ; CLOCK ; 1.000 ; -0.087 ; 25.836 ;; -24.921 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.105 ; 25.817 ;; -24.907 ; fpz8_cpu_v1:inst|IRQ0[3] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.093 ; 25.815 ;; -24.898 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[1] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 25.825 ;; -24.891 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[5] ; CLOCK ; CLOCK ; 1.000 ; -0.086 ; 25.806 ;; -24.889 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[5] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 25.817 ;; -24.882 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[9] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 25.801 ;; -24.875 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[9] ; CLOCK ; CLOCK ; 1.000 ; -0.087 ; 25.789 ;; -24.874 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.105 ; 25.770 ;; -24.871 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 25.787 ;; -24.862 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[4] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 25.757 ;; -24.862 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 25.756 ;; -24.860 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[8] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 25.778 ;; -24.858 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[7] ; CLOCK ; CLOCK ; 1.000 ; -0.088 ; 25.771 ;; -24.833 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[2] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 25.759 ;; -24.828 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[7] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 25.722 ;; -24.824 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 25.742 ;; -24.822 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[1] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.104 ; 25.719 ;; -24.821 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[7] ; CLOCK ; CLOCK ; 1.000 ; -0.091 ; 25.731 ;; -24.817 ; fpz8_cpu_v1:inst|IRQ0ENH[6] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.091 ; 25.727 ;; -24.815 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 25.709 ;; -24.808 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[10] ; CLOCK ; CLOCK ; 1.000 ; -0.086 ; 25.723 ;; -24.808 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[1] ; CLOCK ; CLOCK ; 1.000 ; -0.079 ; 25.730 ;+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Slow 1200mV 85C Model Hold: 'CLOCK' ;+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+; 0.432 ; fpz8_cpu_v1:inst|IRQ0[7] ; fpz8_cpu_v1:inst|IRQ0[7] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|IRQ0[4] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|IRQ0[5] ; fpz8_cpu_v1:inst|IRQ0[5] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|IRQ0[6] ; fpz8_cpu_v1:inst|IRQ0[6] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|IRQ0[1] ; fpz8_cpu_v1:inst|IRQ0[1] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|IRQ0[3] ; fpz8_cpu_v1:inst|IRQ0[3] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|IRQ0[2] ; fpz8_cpu_v1:inst|IRQ0[2] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|IRQ0[0] ; fpz8_cpu_v1:inst|IRQ0[0] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDW2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDW2 ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|CPU_FLAGS.V ; fpz8_cpu_v1:inst|CPU_FLAGS.V ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|CPU_FLAGS.S ; fpz8_cpu_v1:inst|CPU_FLAGS.S ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|\main:TEMP_OP[1] ; fpz8_cpu_v1:inst|\main:TEMP_OP[1] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|\main:TEMP_OP[3] ; fpz8_cpu_v1:inst|\main:TEMP_OP[3] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IMTOIRR ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IMTOIRR ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IRRS ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IRRS ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|DBG_TX ; fpz8_cpu_v1:inst|DBG_TX ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|\main:DBG_UART.TX_STATE.DBGTX_IDLE ; fpz8_cpu_v1:inst|\main:DBG_UART.TX_STATE.DBGTX_IDLE ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[7] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[7] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[4] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[4] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[5] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[5] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[1] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[2] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|\main:ATM_COUNTER[0] ; fpz8_cpu_v1:inst|\main:ATM_COUNTER[0] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|\main:ATM_COUNTER[1] ; fpz8_cpu_v1:inst|\main:ATM_COUNTER[1] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_REV2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_REV2 ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_PC2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_PC2 ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|CPU_FLAGS.C ; fpz8_cpu_v1:inst|CPU_FLAGS.C ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|FCTL[2] ; fpz8_cpu_v1:inst|FCTL[2] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDPTOIM2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDPTOIM2 ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.432 ; fpz8_cpu_v1:inst|ALU_FLAGS.H ; fpz8_cpu_v1:inst|ALU_FLAGS.H ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[3] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[0] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[0] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[2] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[1] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[3] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[4] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[4] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_EXEC2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_EXEC2 ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[3] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_HALTED ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_HALTED ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_ILLEGAL ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_ILLEGAL ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STORE ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STORE ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:OCDCR.RST ; fpz8_cpu_v1:inst|\main:OCDCR.RST ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][5] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][5] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][5] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][5] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][2] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][2] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][2] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][2] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][2] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][2] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][2] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][7] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][7] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][7] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][6] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][6] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][6] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][6] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][1] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][1] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][1] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][1] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][5] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][5] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][5] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][0] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][0] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][0] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][0] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][4] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][4] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][4] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][7] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][7] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][6] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][1] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][1] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][1] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][0] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][0] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][0] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][6] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][6] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][4] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][4] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_DMAB ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_DMAB ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDPTOM2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDPTOM2 ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][4] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][4] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][7] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK' ;+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------+; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_we_reg ;; -3.000 ; 1.000 ; 4.000 ; Port Rate ; CLOCK ; Rise ; CLOCK ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|address_reg_a[0] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.C ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.H ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.S ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.V ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.Z ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.C ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.D ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.F1 ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.F2 ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.H ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.S ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.V ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|DBG_TX ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[0] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[1] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[2] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[7] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[0] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[10] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[11] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[12] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[13] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[1] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[2] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[3] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[4] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[5] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[6] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[7] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[8] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[9] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[0] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[1] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[2] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[3] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[4] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[5] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[6] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[7] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[0] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[1] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[2] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[3] ;+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------+; Setup Times ;+-----------+------------+-------+-------+------------+-----------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-----------+------------+-------+-------+------------+-----------------+; DBG_RX ; CLOCK ; 0.279 ; 0.485 ; Rise ; CLOCK ;; RESET ; CLOCK ; 7.699 ; 8.228 ; Rise ; CLOCK ;+-----------+------------+-------+-------+------------+-----------------++-------------------------------------------------------------------------+; Hold Times ;+-----------+------------+--------+--------+------------+-----------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-----------+------------+--------+--------+------------+-----------------+; DBG_RX ; CLOCK ; 0.206 ; -0.008 ; Rise ; CLOCK ;; RESET ; CLOCK ; -1.507 ; -1.769 ; Rise ; CLOCK ;+-----------+------------+--------+--------+------------+-----------------++-----------------------------------------------------------------------+; Clock to Output Times ;+-----------+------------+-------+-------+------------+-----------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-----------+------------+-------+-------+------------+-----------------+; DBG_TX ; CLOCK ; 7.165 ; 7.071 ; Rise ; CLOCK ;; PAOUT[*] ; CLOCK ; 9.070 ; 9.000 ; Rise ; CLOCK ;; PAOUT[0] ; CLOCK ; 7.699 ; 7.560 ; Rise ; CLOCK ;; PAOUT[1] ; CLOCK ; 7.832 ; 7.656 ; Rise ; CLOCK ;; PAOUT[2] ; CLOCK ; 7.578 ; 7.452 ; Rise ; CLOCK ;; PAOUT[3] ; CLOCK ; 7.472 ; 7.354 ; Rise ; CLOCK ;; PAOUT[4] ; CLOCK ; 9.070 ; 9.000 ; Rise ; CLOCK ;; PAOUT[5] ; CLOCK ; 7.332 ; 7.221 ; Rise ; CLOCK ;; PAOUT[6] ; CLOCK ; 7.464 ; 7.309 ; Rise ; CLOCK ;; PAOUT[7] ; CLOCK ; 7.445 ; 7.306 ; Rise ; CLOCK ;+-----------+------------+-------+-------+------------+-----------------++-----------------------------------------------------------------------+; Minimum Clock to Output Times ;+-----------+------------+-------+-------+------------+-----------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-----------+------------+-------+-------+------------+-----------------+; DBG_TX ; CLOCK ; 6.915 ; 6.825 ; Rise ; CLOCK ;; PAOUT[*] ; CLOCK ; 7.073 ; 6.965 ; Rise ; CLOCK ;; PAOUT[0] ; CLOCK ; 7.429 ; 7.295 ; Rise ; CLOCK ;; PAOUT[1] ; CLOCK ; 7.556 ; 7.387 ; Rise ; CLOCK ;; PAOUT[2] ; CLOCK ; 7.313 ; 7.191 ; Rise ; CLOCK ;; PAOUT[3] ; CLOCK ; 7.211 ; 7.098 ; Rise ; CLOCK ;; PAOUT[4] ; CLOCK ; 8.799 ; 8.735 ; Rise ; CLOCK ;; PAOUT[5] ; CLOCK ; 7.073 ; 6.965 ; Rise ; CLOCK ;; PAOUT[6] ; CLOCK ; 7.200 ; 7.050 ; Rise ; CLOCK ;; PAOUT[7] ; CLOCK ; 7.181 ; 7.047 ; Rise ; CLOCK ;+-----------+------------+-------+-------+------------+-----------------+----------------------------------------------; Slow 1200mV 85C Model Metastability Report ;----------------------------------------------No synchronizer chains to report.+-------------------------------------------------+; Slow 1200mV 0C Model Fmax Summary ;+-----------+-----------------+------------+------+; Fmax ; Restricted Fmax ; Clock Name ; Note ;+-----------+-----------------+------------+------+; 22.45 MHz ; 22.45 MHz ; CLOCK ; ;+-----------+-----------------+------------+------+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.+------------------------------------+; Slow 1200mV 0C Model Setup Summary ;+-------+---------+------------------+; Clock ; Slack ; End Point TNS ;+-------+---------+------------------+; CLOCK ; -24.794 ; -7986.414 ;+-------+---------+------------------++-----------------------------------+; Slow 1200mV 0C Model Hold Summary ;+-------+-------+-------------------+; Clock ; Slack ; End Point TNS ;+-------+-------+-------------------+; CLOCK ; 0.380 ; 0.000 ;+-------+-------+-------------------+-----------------------------------------; Slow 1200mV 0C Model Recovery Summary ;-----------------------------------------No paths to report.----------------------------------------; Slow 1200mV 0C Model Removal Summary ;----------------------------------------No paths to report.+--------------------------------------------------+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;+-------+--------+---------------------------------+; Clock ; Slack ; End Point TNS ;+-------+--------+---------------------------------+; CLOCK ; -3.201 ; -910.432 ;+-------+--------+---------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Slow 1200mV 0C Model Setup: 'CLOCK' ;+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+; -24.794 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 25.723 ;; -24.709 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 25.638 ;; -24.428 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 25.347 ;; -24.309 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 25.237 ;; -24.216 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 25.135 ;; -24.187 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 25.116 ;; -24.187 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 25.115 ;; -24.107 ; fpz8_cpu_v1:inst|IRQ0[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 25.024 ;; -24.104 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.097 ; 25.009 ;; -24.094 ; fpz8_cpu_v1:inst|IRQ0ENH[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 25.014 ;; -24.083 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[2] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 25.011 ;; -24.077 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 24.997 ;; -24.048 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 24.977 ;; -24.019 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.097 ; 24.924 ;; -24.007 ; fpz8_cpu_v1:inst|IRQ0[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 24.924 ;; -23.945 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 24.874 ;; -23.944 ; fpz8_cpu_v1:inst|IRQ0ENL[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 24.863 ;; -23.919 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 24.847 ;; -23.886 ; fpz8_cpu_v1:inst|IRQ0[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 24.803 ;; -23.869 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.067 ; 24.804 ;; -23.828 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[6] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 24.756 ;; -23.825 ; fpz8_cpu_v1:inst|IRQ0ENL[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.084 ; 24.743 ;; -23.825 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 24.752 ;; -23.784 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.067 ; 24.719 ;; -23.783 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.095 ; 24.690 ;; -23.768 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.097 ; 24.673 ;; -23.754 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[0] ; CLOCK ; CLOCK ; 1.000 ; -0.078 ; 24.678 ;; -23.748 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.077 ; 24.673 ;; -23.740 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 24.667 ;; -23.731 ; fpz8_cpu_v1:inst|IRQ0[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 24.648 ;; -23.701 ; fpz8_cpu_v1:inst|IRQ0ENH[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 24.621 ;; -23.698 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.095 ; 24.605 ;; -23.697 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 24.592 ;; -23.685 ; fpz8_cpu_v1:inst|IRQ0ENL[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.084 ; 24.603 ;; -23.683 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.097 ; 24.588 ;; -23.669 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[0] ; CLOCK ; CLOCK ; 1.000 ; -0.078 ; 24.593 ;; -23.668 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[10] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 24.595 ;; -23.663 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[13] ; CLOCK ; CLOCK ; 1.000 ; -0.080 ; 24.585 ;; -23.661 ; fpz8_cpu_v1:inst|IRQ0[3] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 24.578 ;; -23.619 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.098 ; 24.523 ;; -23.583 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[10] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 24.510 ;; -23.578 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[13] ; CLOCK ; CLOCK ; 1.000 ; -0.080 ; 24.500 ;; -23.572 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[14] ; CLOCK ; CLOCK ; 1.000 ; -0.095 ; 24.479 ;; -23.562 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[7] ; CLOCK ; CLOCK ; 1.000 ; -0.068 ; 24.496 ;; -23.548 ; fpz8_cpu_v1:inst|\main:IQUEUE.FULL ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.072 ; 24.478 ;; -23.539 ; fpz8_cpu_v1:inst|IRQ0ENH[6] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 24.459 ;; -23.536 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.077 ; 24.461 ;; -23.534 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[6] ; CLOCK ; CLOCK ; 1.000 ; -0.067 ; 24.469 ;; -23.527 ; fpz8_cpu_v1:inst|\main:CAN_FETCH ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 24.478 ;; -23.520 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[8] ; CLOCK ; CLOCK ; 1.000 ; -0.076 ; 24.446 ;; -23.497 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.097 ; 24.402 ;; -23.497 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.098 ; 24.401 ;; -23.494 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[4] ; CLOCK ; CLOCK ; 1.000 ; -0.067 ; 24.429 ;; -23.487 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[14] ; CLOCK ; CLOCK ; 1.000 ; -0.095 ; 24.394 ;; -23.485 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 24.380 ;; -23.483 ; fpz8_cpu_v1:inst|IRQ0[2] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 24.403 ;; -23.477 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[7] ; CLOCK ; CLOCK ; 1.000 ; -0.068 ; 24.411 ;; -23.466 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[12] ; CLOCK ; CLOCK ; 1.000 ; -0.092 ; 24.376 ;; -23.454 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[10] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 24.371 ;; -23.452 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 24.369 ;; -23.449 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[6] ; CLOCK ; CLOCK ; 1.000 ; -0.067 ; 24.384 ;; -23.441 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[7] ; CLOCK ; CLOCK ; 1.000 ; -0.078 ; 24.365 ;; -23.440 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[8] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 24.368 ;; -23.438 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[12] ; CLOCK ; CLOCK ; 1.000 ; -0.095 ; 24.345 ;; -23.435 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[8] ; CLOCK ; CLOCK ; 1.000 ; -0.076 ; 24.361 ;; -23.427 ; fpz8_cpu_v1:inst|IRQ0[1] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.079 ; 24.350 ;; -23.424 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.077 ; 24.349 ;; -23.414 ; fpz8_cpu_v1:inst|IRQ0ENH[5] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.076 ; 24.340 ;; -23.413 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[6] ; CLOCK ; CLOCK ; 1.000 ; -0.077 ; 24.338 ;; -23.409 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[4] ; CLOCK ; CLOCK ; 1.000 ; -0.067 ; 24.344 ;; -23.407 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[5] ; CLOCK ; CLOCK ; 1.000 ; -0.078 ; 24.331 ;; -23.405 ; fpz8_cpu_v1:inst|IRQ0ENL[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 24.324 ;; -23.402 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 24.297 ;; -23.397 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.076 ; 24.323 ;; -23.397 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[14] ; CLOCK ; CLOCK ; 1.000 ; -0.077 ; 24.322 ;; -23.393 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[2] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.098 ; 24.297 ;; -23.384 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.068 ; 24.318 ;; -23.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[12] ; CLOCK ; CLOCK ; 1.000 ; -0.092 ; 24.291 ;; -23.376 ; fpz8_cpu_v1:inst|IRQ0[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.109 ; 24.269 ;; -23.372 ; fpz8_cpu_v1:inst|IRQ0ENH[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 24.291 ;; -23.366 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[7] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 24.286 ;; -23.365 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[8] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 24.285 ;; -23.363 ; fpz8_cpu_v1:inst|IRQ0ENH[5] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 24.259 ;; -23.363 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[9] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 24.291 ;; -23.362 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[9] ; CLOCK ; CLOCK ; 1.000 ; -0.079 ; 24.285 ;; -23.358 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[5] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.097 ; 24.263 ;; -23.353 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[12] ; CLOCK ; CLOCK ; 1.000 ; -0.095 ; 24.260 ;; -23.346 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 24.242 ;; -23.341 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[10] ; CLOCK ; CLOCK ; 1.000 ; -0.092 ; 24.251 ;; -23.340 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.076 ; 24.266 ;; -23.339 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.077 ; 24.264 ;; -23.327 ; fpz8_cpu_v1:inst|IRQ0[5] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.079 ; 24.250 ;; -23.325 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.115 ; 24.212 ;; -23.322 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[5] ; CLOCK ; CLOCK ; 1.000 ; -0.078 ; 24.246 ;; -23.316 ; fpz8_cpu_v1:inst|IRQ0ENL[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 24.235 ;; -23.312 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[14] ; CLOCK ; CLOCK ; 1.000 ; -0.077 ; 24.237 ;; -23.298 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.096 ; 24.204 ;; -23.293 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[1] ; CLOCK ; CLOCK ; 1.000 ; -0.072 ; 24.223 ;; -23.292 ; fpz8_cpu_v1:inst|\main:IQUEUE.WRPOS[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.061 ; 24.233 ;; -23.283 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.098 ; 24.187 ;+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Slow 1200mV 0C Model Hold: 'CLOCK' ;+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+; 0.380 ; fpz8_cpu_v1:inst|IRQ0[7] ; fpz8_cpu_v1:inst|IRQ0[7] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;; 0.380 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|IRQ0[4] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;; 0.380 ; fpz8_cpu_v1:inst|IRQ0[5] ; fpz8_cpu_v1:inst|IRQ0[5] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;; 0.380 ; fpz8_cpu_v1:inst|IRQ0[6] ; fpz8_cpu_v1:inst|IRQ0[6] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;; 0.380 ; fpz8_cpu_v1:inst|IRQ0[1] ; fpz8_cpu_v1:inst|IRQ0[1] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;; 0.380 ; fpz8_cpu_v1:inst|IRQ0[3] ; fpz8_cpu_v1:inst|IRQ0[3] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;; 0.380 ; fpz8_cpu_v1:inst|IRQ0[2] ; fpz8_cpu_v1:inst|IRQ0[2] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;; 0.380 ; fpz8_cpu_v1:inst|IRQ0[0] ; fpz8_cpu_v1:inst|IRQ0[0] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;; 0.380 ; fpz8_cpu_v1:inst|CPU_FLAGS.V ; fpz8_cpu_v1:inst|CPU_FLAGS.V ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;; 0.380 ; fpz8_cpu_v1:inst|CPU_FLAGS.S ; fpz8_cpu_v1:inst|CPU_FLAGS.S ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;; 0.380 ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;; 0.380 ; fpz8_cpu_v1:inst|FCTL[2] ; fpz8_cpu_v1:inst|FCTL[2] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;; 0.380 ; fpz8_cpu_v1:inst|ALU_FLAGS.H ; fpz8_cpu_v1:inst|ALU_FLAGS.H ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[0] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[0] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[2] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[3] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[3] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_EXEC2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_EXEC2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDW2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDW2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][3] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][3] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][5] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][3] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][2] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][2] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][2] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][7] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][6] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][5] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][0] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][0] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][4] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][4] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][7] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][0] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][6] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][4] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][4] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:TEMP_OP[1] ; fpz8_cpu_v1:inst|\main:TEMP_OP[1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:TEMP_OP[3] ; fpz8_cpu_v1:inst|\main:TEMP_OP[3] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][4] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][4] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][7] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRTORR2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRTORR2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IMTOIRR ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IMTOIRR ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IRRS ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IRRS ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_MUL1 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_MUL1 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_MTOXAD ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_MTOXAD ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRTORR ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRTORR ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRD ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRD ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|DBG_TX ; fpz8_cpu_v1:inst|DBG_TX ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.TX_STATE.DBGTX_IDLE ; fpz8_cpu_v1:inst|\main:DBG_UART.TX_STATE.DBGTX_IDLE ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[7] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[7] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[8] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[8] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_REG4 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_REG4 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.WRT ; fpz8_cpu_v1:inst|\main:DBG_UART.WRT ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[0] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[0] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[4] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[4] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[5] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[5] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[2] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[0] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[0] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[2] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.DBG_SYNC ; fpz8_cpu_v1:inst|\main:DBG_UART.DBG_SYNC ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[7] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[7] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:ATM_COUNTER[0] ; fpz8_cpu_v1:inst|\main:ATM_COUNTER[0] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:ATM_COUNTER[1] ; fpz8_cpu_v1:inst|\main:ATM_COUNTER[1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_PROGMEM5 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_PROGMEM5 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:OCDCR.DBGACK ; fpz8_cpu_v1:inst|\main:OCDCR.DBGACK ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_WRITE_PC2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_WRITE_PC2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_REV2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_REV2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_PC2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_PC2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[2] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[5] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[5] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDMTOP2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDMTOP2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[6] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[6] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|CPU_FLAGS.C ; fpz8_cpu_v1:inst|CPU_FLAGS.C ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_REG2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_REG2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRS3 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRS3 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][3] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][2] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][7] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][5] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][4] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][6] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][0] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_VECTOR ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_VECTOR ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDPTOM4 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDPTOM4 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_MTOXAD2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_MTOXAD2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRD3 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRD3 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_MUL2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_MUL2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRS2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRS2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IRRS2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IRRS2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK' ;+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------+; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_we_reg ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_address_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_datain_reg0 ;; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_we_reg ;; -3.000 ; 1.000 ; 4.000 ; Port Rate ; CLOCK ; Rise ; CLOCK ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|address_reg_a[0] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.C ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.H ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.S ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.V ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.Z ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.C ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.D ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.F1 ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.F2 ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.H ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.S ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.V ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|DBG_TX ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[0] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[1] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[2] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[7] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[0] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[10] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[11] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[12] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[13] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[1] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[2] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[3] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[4] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[5] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[6] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[7] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[8] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[9] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[0] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[1] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[2] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[3] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[4] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[5] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[6] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[7] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[0] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[1] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[2] ;; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[3] ;+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------+; Setup Times ;+-----------+------------+-------+-------+------------+-----------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-----------+------------+-------+-------+------------+-----------------+; DBG_RX ; CLOCK ; 0.243 ; 0.565 ; Rise ; CLOCK ;; RESET ; CLOCK ; 6.928 ; 7.992 ; Rise ; CLOCK ;+-----------+------------+-------+-------+------------+-----------------++-------------------------------------------------------------------------+; Hold Times ;+-----------+------------+--------+--------+------------+-----------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-----------+------------+--------+--------+------------+-----------------+; DBG_RX ; CLOCK ; 0.189 ; -0.129 ; Rise ; CLOCK ;; RESET ; CLOCK ; -1.364 ; -1.806 ; Rise ; CLOCK ;+-----------+------------+--------+--------+------------+-----------------++-----------------------------------------------------------------------+; Clock to Output Times ;+-----------+------------+-------+-------+------------+-----------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-----------+------------+-------+-------+------------+-----------------+; DBG_TX ; CLOCK ; 6.868 ; 6.718 ; Rise ; CLOCK ;; PAOUT[*] ; CLOCK ; 8.797 ; 8.602 ; Rise ; CLOCK ;; PAOUT[0] ; CLOCK ; 7.426 ; 7.133 ; Rise ; CLOCK ;; PAOUT[1] ; CLOCK ; 7.563 ; 7.230 ; Rise ; CLOCK ;; PAOUT[2] ; CLOCK ; 7.268 ; 7.037 ; Rise ; CLOCK ;; PAOUT[3] ; CLOCK ; 7.183 ; 6.968 ; Rise ; CLOCK ;; PAOUT[4] ; CLOCK ; 8.797 ; 8.602 ; Rise ; CLOCK ;; PAOUT[5] ; CLOCK ; 7.042 ; 6.832 ; Rise ; CLOCK ;; PAOUT[6] ; CLOCK ; 7.172 ; 6.916 ; Rise ; CLOCK ;; PAOUT[7] ; CLOCK ; 7.146 ; 6.915 ; Rise ; CLOCK ;+-----------+------------+-------+-------+------------+-----------------++-----------------------------------------------------------------------+; Minimum Clock to Output Times ;+-----------+------------+-------+-------+------------+-----------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-----------+------------+-------+-------+------------+-----------------+; DBG_TX ; CLOCK ; 6.623 ; 6.479 ; Rise ; CLOCK ;; PAOUT[*] ; CLOCK ; 6.788 ; 6.585 ; Rise ; CLOCK ;; PAOUT[0] ; CLOCK ; 7.159 ; 6.878 ; Rise ; CLOCK ;; PAOUT[1] ; CLOCK ; 7.291 ; 6.971 ; Rise ; CLOCK ;; PAOUT[2] ; CLOCK ; 7.008 ; 6.786 ; Rise ; CLOCK ;; PAOUT[3] ; CLOCK ; 6.926 ; 6.720 ; Rise ; CLOCK ;; PAOUT[4] ; CLOCK ; 8.530 ; 8.346 ; Rise ; CLOCK ;; PAOUT[5] ; CLOCK ; 6.788 ; 6.585 ; Rise ; CLOCK ;; PAOUT[6] ; CLOCK ; 6.912 ; 6.666 ; Rise ; CLOCK ;; PAOUT[7] ; CLOCK ; 6.886 ; 6.663 ; Rise ; CLOCK ;+-----------+------------+-------+-------+------------+-----------------+---------------------------------------------; Slow 1200mV 0C Model Metastability Report ;---------------------------------------------No synchronizer chains to report.+------------------------------------+; Fast 1200mV 0C Model Setup Summary ;+-------+---------+------------------+; Clock ; Slack ; End Point TNS ;+-------+---------+------------------+; CLOCK ; -10.913 ; -3387.206 ;+-------+---------+------------------++-----------------------------------+; Fast 1200mV 0C Model Hold Summary ;+-------+-------+-------------------+; Clock ; Slack ; End Point TNS ;+-------+-------+-------------------+; CLOCK ; 0.166 ; 0.000 ;+-------+-------+-------------------+-----------------------------------------; Fast 1200mV 0C Model Recovery Summary ;-----------------------------------------No paths to report.----------------------------------------; Fast 1200mV 0C Model Removal Summary ;----------------------------------------No paths to report.+--------------------------------------------------+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;+-------+--------+---------------------------------+; Clock ; Slack ; End Point TNS ;+-------+--------+---------------------------------+; CLOCK ; -3.000 ; -587.993 ;+-------+--------+---------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fast 1200mV 0C Model Setup: 'CLOCK' ;+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+; -10.913 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.045 ; 11.855 ;; -10.860 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.045 ; 11.802 ;; -10.674 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.046 ; 11.615 ;; -10.672 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.049 ; 11.610 ;; -10.652 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.046 ; 11.593 ;; -10.627 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.049 ; 11.565 ;; -10.627 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.045 ; 11.569 ;; -10.607 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.050 ; 11.544 ;; -10.594 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[2] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.046 ; 11.535 ;; -10.583 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.045 ; 11.525 ;; -10.577 ; fpz8_cpu_v1:inst|IRQ0ENH[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.049 ; 11.515 ;; -10.538 ; fpz8_cpu_v1:inst|IRQ0[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.474 ;; -10.519 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.045 ; 11.461 ;; -10.511 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.046 ; 11.452 ;; -10.498 ; fpz8_cpu_v1:inst|IRQ0[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.434 ;; -10.461 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.397 ;; -10.458 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[6] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.046 ; 11.399 ;; -10.429 ; fpz8_cpu_v1:inst|IRQ0[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.365 ;; -10.428 ; fpz8_cpu_v1:inst|IRQ0ENL[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.364 ;; -10.417 ; fpz8_cpu_v1:inst|IRQ0ENL[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.050 ; 11.354 ;; -10.417 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[0] ; CLOCK ; CLOCK ; 1.000 ; -0.042 ; 11.362 ;; -10.409 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.036 ; 11.360 ;; -10.408 ; fpz8_cpu_v1:inst|IRQ0[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.344 ;; -10.408 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.344 ;; -10.398 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.041 ; 11.344 ;; -10.394 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[14] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.330 ;; -10.385 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[13] ; CLOCK ; CLOCK ; 1.000 ; -0.044 ; 11.328 ;; -10.364 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[0] ; CLOCK ; CLOCK ; 1.000 ; -0.042 ; 11.309 ;; -10.360 ; fpz8_cpu_v1:inst|IRQ0ENH[6] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.049 ; 11.298 ;; -10.356 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.036 ; 11.307 ;; -10.348 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[10] ; CLOCK ; CLOCK ; 1.000 ; -0.039 ; 11.296 ;; -10.347 ; fpz8_cpu_v1:inst|\main:IQUEUE.FULL ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.044 ; 11.290 ;; -10.346 ; fpz8_cpu_v1:inst|IRQ0ENL[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.282 ;; -10.345 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.041 ; 11.291 ;; -10.341 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[14] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.277 ;; -10.332 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[13] ; CLOCK ; CLOCK ; 1.000 ; -0.044 ; 11.275 ;; -10.321 ; fpz8_cpu_v1:inst|IRQ0[3] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.257 ;; -10.320 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[12] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.256 ;; -10.314 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[4] ; CLOCK ; CLOCK ; 1.000 ; -0.035 ; 11.266 ;; -10.314 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.039 ; 11.262 ;; -10.298 ; fpz8_cpu_v1:inst|\main:CAN_FETCH ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.030 ; 11.255 ;; -10.298 ; fpz8_cpu_v1:inst|IRQ0[2] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.049 ; 11.236 ;; -10.295 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[10] ; CLOCK ; CLOCK ; 1.000 ; -0.039 ; 11.243 ;; -10.290 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.056 ; 11.221 ;; -10.289 ; fpz8_cpu_v1:inst|IRQ0ENH[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.049 ; 11.227 ;; -10.285 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[6] ; CLOCK ; CLOCK ; 1.000 ; -0.036 ; 11.236 ;; -10.280 ; fpz8_cpu_v1:inst|IRQ0ENH[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.050 ; 11.217 ;; -10.279 ; fpz8_cpu_v1:inst|IRQ0ENL[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.050 ; 11.216 ;; -10.267 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[12] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.203 ;; -10.264 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[10] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.200 ;; -10.261 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[8] ; CLOCK ; CLOCK ; 1.000 ; -0.044 ; 11.204 ;; -10.261 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[4] ; CLOCK ; CLOCK ; 1.000 ; -0.035 ; 11.213 ;; -10.261 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.039 ; 11.209 ;; -10.240 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.040 ; 11.187 ;; -10.237 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.056 ; 11.168 ;; -10.232 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[6] ; CLOCK ; CLOCK ; 1.000 ; -0.036 ; 11.183 ;; -10.231 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[9] ; CLOCK ; CLOCK ; 1.000 ; -0.043 ; 11.175 ;; -10.229 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.055 ; 11.161 ;; -10.228 ; fpz8_cpu_v1:inst|\main:IQUEUE.WRPOS[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.038 ; 11.177 ;; -10.224 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[8] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.046 ; 11.165 ;; -10.223 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[5] ; CLOCK ; CLOCK ; 1.000 ; -0.035 ; 11.175 ;; -10.222 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.052 ; 11.157 ;; -10.218 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[7] ; CLOCK ; CLOCK ; 1.000 ; -0.037 ; 11.168 ;; -10.215 ; fpz8_cpu_v1:inst|IRQ0ENL[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.050 ; 11.152 ;; -10.211 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[10] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.147 ;; -10.208 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[8] ; CLOCK ; CLOCK ; 1.000 ; -0.044 ; 11.151 ;; -10.205 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[5] ; CLOCK ; CLOCK ; 1.000 ; -0.041 ; 11.151 ;; -10.200 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.053 ; 11.134 ;; -10.200 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.052 ; 11.135 ;; -10.195 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.040 ; 11.142 ;; -10.188 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[9] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.046 ; 11.129 ;; -10.178 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[9] ; CLOCK ; CLOCK ; 1.000 ; -0.043 ; 11.122 ;; -10.178 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[0] ; CLOCK ; CLOCK ; 1.000 ; -0.043 ; 11.122 ;; -10.176 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.055 ; 11.108 ;; -10.175 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.041 ; 11.121 ;; -10.175 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[1] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.111 ;; -10.170 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[8] ; CLOCK ; CLOCK ; 1.000 ; -0.039 ; 11.118 ;; -10.170 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.037 ; 11.120 ;; -10.170 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[5] ; CLOCK ; CLOCK ; 1.000 ; -0.035 ; 11.122 ;; -10.168 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[7] ; CLOCK ; CLOCK ; 1.000 ; -0.044 ; 11.111 ;; -10.165 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[7] ; CLOCK ; CLOCK ; 1.000 ; -0.037 ; 11.115 ;; -10.161 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|MAB[10] ; CLOCK ; CLOCK ; 1.000 ; -0.043 ; 11.105 ;; -10.161 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[12] ; CLOCK ; CLOCK ; 1.000 ; -0.050 ; 11.098 ;; -10.159 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.042 ; 11.104 ;; -10.156 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.063 ; 11.080 ;; -10.156 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|MAB[0] ; CLOCK ; CLOCK ; 1.000 ; -0.043 ; 11.100 ;; -10.155 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.053 ; 11.089 ;; -10.155 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|\main:PC[14] ; CLOCK ; CLOCK ; 1.000 ; -0.052 ; 11.090 ;; -10.152 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[5] ; CLOCK ; CLOCK ; 1.000 ; -0.041 ; 11.098 ;; -10.151 ; fpz8_cpu_v1:inst|\main:IQUEUE.RDPOS[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.034 ; 11.104 ;; -10.150 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[14] ; CLOCK ; CLOCK ; 1.000 ; -0.041 ; 11.096 ;; -10.149 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|\main:PC[14] ; CLOCK ; CLOCK ; 1.000 ; -0.063 ; 11.073 ;; -10.149 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[11] ; CLOCK ; CLOCK ; 1.000 ; -0.042 ; 11.094 ;; -10.148 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.037 ; 11.098 ;; -10.146 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|\main:PC[13] ; CLOCK ; CLOCK ; 1.000 ; -0.045 ; 11.088 ;; -10.145 ; fpz8_cpu_v1:inst|IRQ0ENH[5] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.040 ; 11.092 ;; -10.142 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[2] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.052 ; 11.077 ;; -10.137 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.042 ; 11.082 ;; -10.135 ; fpz8_cpu_v1:inst|\main:IQUEUE.WRPOS[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.038 ; 11.084 ;; -10.135 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.054 ; 11.068 ;+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fast 1200mV 0C Model Hold: 'CLOCK' ;+-------+-----------------------------------------------+-----------------------------------------------+--------------+-------------+--------------+------------+------------+; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;+-------+-----------------------------------------------+-----------------------------------------------+--------------+-------------+--------------+------------+------------+; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[3] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|IRQ0[7] ; fpz8_cpu_v1:inst|IRQ0[7] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[4] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[4] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|IRQ0[4] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|IRQ0[5] ; fpz8_cpu_v1:inst|IRQ0[5] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|IRQ0[6] ; fpz8_cpu_v1:inst|IRQ0[6] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|IRQ0[1] ; fpz8_cpu_v1:inst|IRQ0[1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|IRQ0[3] ; fpz8_cpu_v1:inst|IRQ0[3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|IRQ0[2] ; fpz8_cpu_v1:inst|IRQ0[2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|IRQ0[0] ; fpz8_cpu_v1:inst|IRQ0[0] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[3] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDW2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDW2 ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|CPU_FLAGS.V ; fpz8_cpu_v1:inst|CPU_FLAGS.V ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|CPU_FLAGS.S ; fpz8_cpu_v1:inst|CPU_FLAGS.S ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][5] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][5] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][7] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][7] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][6] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][6] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][6] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][5] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][5] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][5] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][0] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][4] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][4] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][7] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][0] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][0] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][6] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:TEMP_OP[1] ; fpz8_cpu_v1:inst|\main:TEMP_OP[1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:TEMP_OP[3] ; fpz8_cpu_v1:inst|\main:TEMP_OP[3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][4] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][4] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][7] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][7] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IMTOIRR ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IMTOIRR ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IRRS ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IRRS ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|DBG_TX ; fpz8_cpu_v1:inst|DBG_TX ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[8] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[8] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[0] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[0] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[0] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[0] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.DBG_SYNC ; fpz8_cpu_v1:inst|\main:DBG_UART.DBG_SYNC ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[7] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[7] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:OCDCR.DBGACK ; fpz8_cpu_v1:inst|\main:OCDCR.DBGACK ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_REV2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_REV2 ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_PC2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_PC2 ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[5] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[5] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STACK3 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STACK3 ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[6] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[6] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STACK2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STACK2 ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|CPU_FLAGS.C ; fpz8_cpu_v1:inst|CPU_FLAGS.C ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STACK1 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STACK1 ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][7] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][5] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][4] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][6] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][0] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRTORR4 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRTORR4 ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDPTOIM2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDPTOIM2 ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.166 ; fpz8_cpu_v1:inst|ALU_FLAGS.H ; fpz8_cpu_v1:inst|ALU_FLAGS.H ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;; 0.167 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[0] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[0] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;; 0.167 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[2] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;; 0.167 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[1] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;; 0.167 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[3] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[3] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;; 0.167 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_EXEC2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_EXEC2 ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;; 0.167 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_HALTED ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_HALTED ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;; 0.167 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_ILLEGAL ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_ILLEGAL ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;; 0.167 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STORE ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STORE ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;; 0.167 ; fpz8_cpu_v1:inst|\main:OCDCR.RST ; fpz8_cpu_v1:inst|\main:OCDCR.RST ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;; 0.167 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][3] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;; 0.167 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][3] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;; 0.167 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][5] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;; 0.167 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][5] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;; 0.167 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][3] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;; 0.167 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][2] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;+-------+-----------------------------------------------+-----------------------------------------------+--------------+-------------+--------------+------------+------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK' ;+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------+; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------+; -3.000 ; 1.000 ; 4.000 ; Port Rate ; CLOCK ; Rise ; CLOCK ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|address_reg_a[0] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_address_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_datain_reg0 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_we_reg ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.C ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.H ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.S ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.V ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.Z ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.C ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.D ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.F1 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.F2 ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.H ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.S ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.V ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|DBG_TX ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[0] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[1] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[2] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[7] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[0] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[10] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[11] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[12] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[13] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[1] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[2] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[3] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[4] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[5] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[6] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[7] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[8] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[9] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[0] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[1] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[2] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[3] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[4] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[5] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[6] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[7] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[0] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[1] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[2] ;; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[3] ;+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------++-----------------------------------------------------------------------+; Setup Times ;+-----------+------------+-------+-------+------------+-----------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-----------+------------+-------+-------+------------+-----------------+; DBG_RX ; CLOCK ; 0.157 ; 0.449 ; Rise ; CLOCK ;; RESET ; CLOCK ; 3.725 ; 3.615 ; Rise ; CLOCK ;+-----------+------------+-------+-------+------------+-----------------++-------------------------------------------------------------------------+; Hold Times ;+-----------+------------+--------+--------+------------+-----------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-----------+------------+--------+--------+------------+-----------------+; DBG_RX ; CLOCK ; 0.057 ; -0.247 ; Rise ; CLOCK ;; RESET ; CLOCK ; -0.714 ; -0.959 ; Rise ; CLOCK ;+-----------+------------+--------+--------+------------+-----------------++-----------------------------------------------------------------------+; Clock to Output Times ;+-----------+------------+-------+-------+------------+-----------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-----------+------------+-------+-------+------------+-----------------+; DBG_TX ; CLOCK ; 3.352 ; 3.451 ; Rise ; CLOCK ;; PAOUT[*] ; CLOCK ; 4.455 ; 4.617 ; Rise ; CLOCK ;; PAOUT[0] ; CLOCK ; 3.563 ; 3.689 ; Rise ; CLOCK ;; PAOUT[1] ; CLOCK ; 3.637 ; 3.749 ; Rise ; CLOCK ;; PAOUT[2] ; CLOCK ; 3.520 ; 3.637 ; Rise ; CLOCK ;; PAOUT[3] ; CLOCK ; 3.481 ; 3.595 ; Rise ; CLOCK ;; PAOUT[4] ; CLOCK ; 4.455 ; 4.617 ; Rise ; CLOCK ;; PAOUT[5] ; CLOCK ; 3.422 ; 3.498 ; Rise ; CLOCK ;; PAOUT[6] ; CLOCK ; 3.446 ; 3.545 ; Rise ; CLOCK ;; PAOUT[7] ; CLOCK ; 3.463 ; 3.555 ; Rise ; CLOCK ;+-----------+------------+-------+-------+------------+-----------------++-----------------------------------------------------------------------+; Minimum Clock to Output Times ;+-----------+------------+-------+-------+------------+-----------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-----------+------------+-------+-------+------------+-----------------+; DBG_TX ; CLOCK ; 3.247 ; 3.343 ; Rise ; CLOCK ;; PAOUT[*] ; CLOCK ; 3.312 ; 3.386 ; Rise ; CLOCK ;; PAOUT[0] ; CLOCK ; 3.450 ; 3.572 ; Rise ; CLOCK ;; PAOUT[1] ; CLOCK ; 3.521 ; 3.630 ; Rise ; CLOCK ;; PAOUT[2] ; CLOCK ; 3.408 ; 3.522 ; Rise ; CLOCK ;; PAOUT[3] ; CLOCK ; 3.372 ; 3.482 ; Rise ; CLOCK ;; PAOUT[4] ; CLOCK ; 4.341 ; 4.500 ; Rise ; CLOCK ;; PAOUT[5] ; CLOCK ; 3.312 ; 3.386 ; Rise ; CLOCK ;; PAOUT[6] ; CLOCK ; 3.336 ; 3.431 ; Rise ; CLOCK ;; PAOUT[7] ; CLOCK ; 3.352 ; 3.441 ; Rise ; CLOCK ;+-----------+------------+-------+-------+------------+-----------------+---------------------------------------------; Fast 1200mV 0C Model Metastability Report ;---------------------------------------------No synchronizer chains to report.+---------------------------------------------------------------------------------+; Multicorner Timing Analysis Summary ;+------------------+-----------+-------+----------+---------+---------------------+; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;+------------------+-----------+-------+----------+---------+---------------------+; Worst-case Slack ; -26.441 ; 0.166 ; N/A ; N/A ; -3.201 ;; CLOCK ; -26.441 ; 0.166 ; N/A ; N/A ; -3.201 ;; Design-wide TNS ; -8505.086 ; 0.0 ; 0.0 ; 0.0 ; -910.432 ;; CLOCK ; -8505.086 ; 0.000 ; N/A ; N/A ; -910.432 ;+------------------+-----------+-------+----------+---------+---------------------++-----------------------------------------------------------------------+; Setup Times ;+-----------+------------+-------+-------+------------+-----------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-----------+------------+-------+-------+------------+-----------------+; DBG_RX ; CLOCK ; 0.279 ; 0.565 ; Rise ; CLOCK ;; RESET ; CLOCK ; 7.699 ; 8.228 ; Rise ; CLOCK ;+-----------+------------+-------+-------+------------+-----------------++-------------------------------------------------------------------------+; Hold Times ;+-----------+------------+--------+--------+------------+-----------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-----------+------------+--------+--------+------------+-----------------+; DBG_RX ; CLOCK ; 0.206 ; -0.008 ; Rise ; CLOCK ;; RESET ; CLOCK ; -0.714 ; -0.959 ; Rise ; CLOCK ;+-----------+------------+--------+--------+------------+-----------------++-----------------------------------------------------------------------+; Clock to Output Times ;+-----------+------------+-------+-------+------------+-----------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-----------+------------+-------+-------+------------+-----------------+; DBG_TX ; CLOCK ; 7.165 ; 7.071 ; Rise ; CLOCK ;; PAOUT[*] ; CLOCK ; 9.070 ; 9.000 ; Rise ; CLOCK ;; PAOUT[0] ; CLOCK ; 7.699 ; 7.560 ; Rise ; CLOCK ;; PAOUT[1] ; CLOCK ; 7.832 ; 7.656 ; Rise ; CLOCK ;; PAOUT[2] ; CLOCK ; 7.578 ; 7.452 ; Rise ; CLOCK ;; PAOUT[3] ; CLOCK ; 7.472 ; 7.354 ; Rise ; CLOCK ;; PAOUT[4] ; CLOCK ; 9.070 ; 9.000 ; Rise ; CLOCK ;; PAOUT[5] ; CLOCK ; 7.332 ; 7.221 ; Rise ; CLOCK ;; PAOUT[6] ; CLOCK ; 7.464 ; 7.309 ; Rise ; CLOCK ;; PAOUT[7] ; CLOCK ; 7.445 ; 7.306 ; Rise ; CLOCK ;+-----------+------------+-------+-------+------------+-----------------++-----------------------------------------------------------------------+; Minimum Clock to Output Times ;+-----------+------------+-------+-------+------------+-----------------+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;+-----------+------------+-------+-------+------------+-----------------+; DBG_TX ; CLOCK ; 3.247 ; 3.343 ; Rise ; CLOCK ;; PAOUT[*] ; CLOCK ; 3.312 ; 3.386 ; Rise ; CLOCK ;; PAOUT[0] ; CLOCK ; 3.450 ; 3.572 ; Rise ; CLOCK ;; PAOUT[1] ; CLOCK ; 3.521 ; 3.630 ; Rise ; CLOCK ;; PAOUT[2] ; CLOCK ; 3.408 ; 3.522 ; Rise ; CLOCK ;; PAOUT[3] ; CLOCK ; 3.372 ; 3.482 ; Rise ; CLOCK ;; PAOUT[4] ; CLOCK ; 4.341 ; 4.500 ; Rise ; CLOCK ;; PAOUT[5] ; CLOCK ; 3.312 ; 3.386 ; Rise ; CLOCK ;; PAOUT[6] ; CLOCK ; 3.336 ; 3.431 ; Rise ; CLOCK ;; PAOUT[7] ; CLOCK ; 3.352 ; 3.441 ; Rise ; CLOCK ;+-----------+------------+-------+-------+------------+-----------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Board Trace Model Assignments ;+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ;+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+; DBG_TX ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;; PAOUT[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;; PAOUT[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;; PAOUT[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;; PAOUT[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;; PAOUT[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;; PAOUT[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;; PAOUT[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;; PAOUT[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------++----------------------------------------------------------------------------+; Input Transition Times ;+-------------------------+--------------+-----------------+-----------------+; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;+-------------------------+--------------+-----------------+-----------------+; CLOCK ; 2.5 V ; 2000 ps ; 2000 ps ;; RESET ; 2.5 V ; 2000 ps ; 2000 ps ;; DBG_RX ; 2.5 V ; 2000 ps ; 2000 ps ;; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;+-------------------------+--------------+-----------------+-----------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Slow Corner Signal Integrity Metrics ;+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; DBG_TX ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ;; PAOUT[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.35 V ; -0.00735 V ; 0.126 V ; 0.011 V ; 4.7e-010 s ; 4.63e-010 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.35 V ; -0.00735 V ; 0.126 V ; 0.011 V ; 4.7e-010 s ; 4.63e-010 s ; Yes ; Yes ;; PAOUT[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.35 V ; -0.00735 V ; 0.126 V ; 0.011 V ; 4.7e-010 s ; 4.63e-010 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.35 V ; -0.00735 V ; 0.126 V ; 0.011 V ; 4.7e-010 s ; 4.63e-010 s ; Yes ; Yes ;; PAOUT[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.35 V ; -0.00735 V ; 0.126 V ; 0.011 V ; 4.7e-010 s ; 4.63e-010 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.35 V ; -0.00735 V ; 0.126 V ; 0.011 V ; 4.7e-010 s ; 4.63e-010 s ; Yes ; Yes ;; PAOUT[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.33 V ; -0.00219 V ; 0.108 V ; 0.043 V ; 3.76e-009 s ; 3.48e-009 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.33 V ; -0.00219 V ; 0.108 V ; 0.043 V ; 3.76e-009 s ; 3.48e-009 s ; Yes ; Yes ;; PAOUT[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ;; PAOUT[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ;; PAOUT[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ;; PAOUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ;; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.53e-007 V ; 2.35 V ; -0.00333 V ; 0.096 V ; 0.006 V ; 4.5e-010 s ; 3.85e-010 s ; Yes ; Yes ; 2.32 V ; 1.53e-007 V ; 2.35 V ; -0.00333 V ; 0.096 V ; 0.006 V ; 4.5e-010 s ; 3.85e-010 s ; Yes ; Yes ;; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.51e-007 V ; 2.34 V ; -0.00726 V ; 0.108 V ; 0.026 V ; 6.58e-010 s ; 8.2e-010 s ; Yes ; Yes ; 2.32 V ; 2.51e-007 V ; 2.34 V ; -0.00726 V ; 0.108 V ; 0.026 V ; 6.58e-010 s ; 8.2e-010 s ; Yes ; Yes ;+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fast Corner Signal Integrity Metrics ;+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; DBG_TX ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ;; PAOUT[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.72 V ; -0.0401 V ; 0.163 V ; 0.091 V ; 2.71e-010 s ; 2.61e-010 s ; Yes ; Yes ; 2.62 V ; 2.7e-008 V ; 2.72 V ; -0.0401 V ; 0.163 V ; 0.091 V ; 2.71e-010 s ; 2.61e-010 s ; Yes ; Yes ;; PAOUT[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.72 V ; -0.0401 V ; 0.163 V ; 0.091 V ; 2.71e-010 s ; 2.61e-010 s ; Yes ; Yes ; 2.62 V ; 2.7e-008 V ; 2.72 V ; -0.0401 V ; 0.163 V ; 0.091 V ; 2.71e-010 s ; 2.61e-010 s ; Yes ; Yes ;; PAOUT[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.72 V ; -0.0401 V ; 0.163 V ; 0.091 V ; 2.71e-010 s ; 2.61e-010 s ; Yes ; Yes ; 2.62 V ; 2.7e-008 V ; 2.72 V ; -0.0401 V ; 0.163 V ; 0.091 V ; 2.71e-010 s ; 2.61e-010 s ; Yes ; Yes ;; PAOUT[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.64 V ; -0.0118 V ; 0.201 V ; 0.173 V ; 2.38e-009 s ; 2.19e-009 s ; No ; Yes ; 2.62 V ; 2.7e-008 V ; 2.64 V ; -0.0118 V ; 0.201 V ; 0.173 V ; 2.38e-009 s ; 2.19e-009 s ; No ; Yes ;; PAOUT[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ;; PAOUT[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ;; PAOUT[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ;; PAOUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ;; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.2e-008 V ; 2.74 V ; -0.061 V ; 0.159 V ; 0.078 V ; 2.7e-010 s ; 2.2e-010 s ; No ; Yes ; 2.62 V ; 2.2e-008 V ; 2.74 V ; -0.061 V ; 0.159 V ; 0.078 V ; 2.7e-010 s ; 2.2e-010 s ; No ; Yes ;; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.52e-008 V ; 2.7 V ; -0.012 V ; 0.274 V ; 0.034 V ; 3.18e-010 s ; 4.96e-010 s ; No ; Yes ; 2.62 V ; 3.52e-008 V ; 2.7 V ; -0.012 V ; 0.274 V ; 0.034 V ; 3.18e-010 s ; 4.96e-010 s ; No ; Yes ;+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------++-----------------------------------------------------------------------+; Setup Transfers ;+------------+----------+--------------+----------+----------+----------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+------------+----------+--------------+----------+----------+----------+; CLOCK ; CLOCK ; > 2147483647 ; 15094538 ; 339 ; 0 ;+------------+----------+--------------+----------+----------+----------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.+-----------------------------------------------------------------------+; Hold Transfers ;+------------+----------+--------------+----------+----------+----------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+------------+----------+--------------+----------+----------+----------+; CLOCK ; CLOCK ; > 2147483647 ; 15094538 ; 339 ; 0 ;+------------+----------+--------------+----------+----------+----------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.---------------; Report TCCS ;---------------No dedicated SERDES Transmitter circuitry present in device or used in design---------------; Report RSKM ;---------------No dedicated SERDES Receiver circuitry present in device or used in design+------------------------------------------------+; Unconstrained Paths ;+---------------------------------+-------+------+; Property ; Setup ; Hold ;+---------------------------------+-------+------+; Illegal Clocks ; 0 ; 0 ;; Unconstrained Clocks ; 0 ; 0 ;; Unconstrained Input Ports ; 2 ; 2 ;; Unconstrained Input Port Paths ; 494 ; 494 ;; Unconstrained Output Ports ; 9 ; 9 ;; Unconstrained Output Port Paths ; 9 ; 9 ;+---------------------------------+-------+------++------------------------------------+; TimeQuest Timing Analyzer Messages ;+------------------------------------+Info: *******************************************************************Info: Running Quartus II TimeQuest Timing AnalyzerInfo: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web EditionInfo: Processing started: Fri Nov 11 10:25:00 2016Info: Command: quartus_sta FPz8 -c FPz8_Cyclone_IVInfo: qsta_default_script.tcl version: #1Info: Core supply voltage is 1.2VInfo: Low junction temperature is 0 degrees CInfo: High junction temperature is 85 degrees CInfo: Reading SDC File: 'FPz8_Cyclone_IV.out.sdc'Info: Deriving ClocksInfo: create_clock -period 1.000 -name CLOCK CLOCKInfo: Clock uncertainty calculation is delayed until the next update_timing_netlist callInfo: Deriving Clock UncertaintyInfo: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -setup 0.020Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -setup 0.020Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -setup 0.020Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -setup 0.020Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -hold 0.020Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -hold 0.020Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -hold 0.020Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -hold 0.020Info: Analyzing Slow 1200mV 85C ModelCritical Warning: Timing requirements not metInfo: Worst-case setup slack is -26.441Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: -26.441 -8505.086 CLOCKInfo: Worst-case hold slack is 0.432Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: 0.432 0.000 CLOCKInfo: No Recovery paths to reportInfo: No Removal paths to reportInfo: Worst-case minimum pulse width slack is -3.201Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: -3.201 -910.432 CLOCKInfo: Analyzing Slow 1200mV 0C ModelInfo: Started post-fitting delay annotationWarning: Timing characteristics of device EP4CE6E22C8 are preliminaryInfo: Delay annotation completed successfullyInfo: Deriving Clock UncertaintyInfo: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -setup 0.020Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -setup 0.020Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -setup 0.020Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -setup 0.020Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -hold 0.020Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -hold 0.020Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -hold 0.020Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -hold 0.020Critical Warning: Timing requirements not metInfo: Worst-case setup slack is -24.794Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: -24.794 -7986.414 CLOCKInfo: Worst-case hold slack is 0.380Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: 0.380 0.000 CLOCKInfo: No Recovery paths to reportInfo: No Removal paths to reportInfo: Worst-case minimum pulse width slack is -3.201Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: -3.201 -910.432 CLOCKInfo: Analyzing Fast 1200mV 0C ModelInfo: Started post-fitting delay annotationWarning: Timing characteristics of device EP4CE6E22C8 are preliminaryInfo: Delay annotation completed successfullyInfo: Deriving Clock UncertaintyInfo: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -setup 0.020Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -setup 0.020Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -setup 0.020Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -setup 0.020Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -hold 0.020Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -hold 0.020Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -hold 0.020Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -hold 0.020Critical Warning: Timing requirements not metInfo: Worst-case setup slack is -10.913Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: -10.913 -3387.206 CLOCKInfo: Worst-case hold slack is 0.166Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: 0.166 0.000 CLOCKInfo: No Recovery paths to reportInfo: No Removal paths to reportInfo: Worst-case minimum pulse width slack is -3.000Info: Slack End Point TNS ClockInfo: ========= ============= =====================Info: -3.000 -587.993 CLOCKInfo: Design is not fully constrained for setup requirementsInfo: Design is not fully constrained for hold requirementsInfo: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 5 warningsInfo: Peak virtual memory: 258 megabytesInfo: Processing ended: Fri Nov 11 10:25:14 2016Info: Elapsed time: 00:00:14Info: Total CPU time (on all processors): 00:00:11