Subversion Repositories System09

-- $Id: ram16k_b16.vhd,v 1.2 2008/03/14 15:52:43 dilbert57 Exp $
--===========================================================================--
--                                                                           --
--  ram16k_b16.vhd - 16KByte Block RAM Component for Spartan 3/3E            --
--                                                                           --
--===========================================================================--
--
--  File name      : ram16k_b16.vhd
--
--  Entity name    : ram_16k
--
--  Purpose        : Implements 16K of Synchronous Static RAM 
--                   using 16 x Spartan 3/3E RAMB16_S9 block rams
--                   Used in the Digilent Spartan 3E500 System09 design
--                  
--  Dependencies   : ieee.Std_Logic_1164
--                   ieee.std_logic_arith
--                   unisim.vcomponents
--
--  Uses           : RAMB16_S9
--
--  Author         : John E. Kent
--
--  Email          : dilbert57@opencores.org      
--
--  Web            : http://opencores.org/project,system09
--
--
--  Copyright (C) 2005 - 2010 John Kent
--
--  This program is free software: you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation, either version 3 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
--                                                                           --
--                              Revision  History                            --
--                                                                           --
--===========================================================================--
--
-- Version Author      Date          Changes
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
  use unisim.vcomponents.all;
 
entity ram_16k is
  port (
    clk      : in  std_logic;
    rst      : in  std_logic;
    cs       : in  std_logic;
    addr     : in  std_logic_vector (13 downto 0);
    rw       : in  std_logic;
    data_in  : in  std_logic_vector (7 downto 0);
    data_out : out std_logic_vector (7 downto 0)
  );
end ram_16k;
 
architecture rtl of ram_16k is
 
  signal we         : std_logic;
  signal dp         : std_logic_vector(15 downto 0);
  signal ce         : std_logic_vector(15 downto 0);
  signal data_out_0 : std_logic_vector(7 downto 0);
  signal data_out_1 : std_logic_vector(7 downto 0);
  signal data_out_2 : std_logic_vector(7 downto 0);
  signal data_out_3 : std_logic_vector(7 downto 0);
  signal data_out_4 : std_logic_vector(7 downto 0);
  signal data_out_5 : std_logic_vector(7 downto 0);
  signal data_out_6 : std_logic_vector(7 downto 0);
  signal data_out_7 : std_logic_vector(7 downto 0);
 
begin
 
  RAM0 : RAMB16_S9
    port map (
      do   => data_out_0,
      dop(0) => dp(0),
      addr => addr(10 downto 0),
      clk  => clk,
      di   => data_in,
      dip(0) => dp(0),
      en   => ce(0),
      ssr  => rst,
      we   => we
    );
 
  RAM1 : RAMB16_S9
    port map (
      do   => data_out_1,
      dop(0) => dp(1),
      addr => addr(10 downto 0),
      clk  => clk,
      di   => data_in,
      dip(0) => dp(1),
      en   => ce(1),
      ssr  => rst,
      we   => we
    );
 
  RAM2 : RAMB16_S9
    port map (
      do   => data_out_2,
      dop(0) => dp(2),
      addr => addr(10 downto 0),
      clk  => clk,
      di   => data_in,
      dip(0) => dp(2),
      en   => ce(2),
      ssr  => rst,
      we   => we
    );
 
  RAM3 : RAMB16_S9
    port map (
      do   => data_out_3,
      dop(0) => dp(3),
      addr => addr(10 downto 0),
      clk  => clk,
      di   => data_in,
      dip(0) => dp(3),
      en   => ce(3),
      ssr  => rst,
      we   => we
    );
 
  RAM4 : RAMB16_S9
    port map (
      do   => data_out_4,
      dop(0) => dp(4),
      addr => addr(10 downto 0),
      clk  => clk,
      di   => data_in,
      dip(0) => dp(4),
      en   => ce(4),
      ssr  => rst,
      we   => we
    );
 
  RAM5 : RAMB16_S9
    port map (
      do   => data_out_5,
      dop(0) => dp(5),
      addr => addr(10 downto 0),
      clk  => clk,
      di   => data_in,
      dip(0) => dp(5),
      en   => ce(5),
      ssr  => rst,
      we   => we
    );
 
  RAM6 : RAMB16_S9
    port map (
      do   => data_out_6,
      dop(0) => dp(6),
      addr => addr(10 downto 0),
      clk  => clk,
      di   => data_in,
      dip(0) => dp(6),
      en   => ce(6),
      ssr  => rst,
      we   => we
    );
 
  RAM7 : RAMB16_S9
    port map (
      do   => data_out_7,
      dop(0) => dp(7),
      addr => addr(10 downto 0),
      clk  => clk,
      di   => data_in,
      dip(0) => dp(7),
      en   => ce(7),
      ssr  => rst,
      we   => we
    );
 
my_ram_32k : process ( cs, rw, addr,
                       data_out_0, data_out_1, data_out_2, data_out_3,
                       data_out_4, data_out_5, data_out_6, data_out_7)
begin
	 we <= not rw;
 
	 case addr(13 downto 11) is
	 when "000" =>
	     data_out <= data_out_0;
	 when "001" =>
	     data_out <= data_out_1;
	 when "010" =>
	     data_out <= data_out_2;
	 when "011" =>
	     data_out <= data_out_3;
	 when "100" =>
	     data_out <= data_out_4;
	 when "101" =>
	     data_out <= data_out_5;
	 when "110" =>
	     data_out <= data_out_6;
	 when "111" =>
	     data_out <= data_out_7;
	 when others =>
	     null;
    end case;
 
    ce(0)  <= cs and not( addr(13) ) and not( addr(12) ) and not( addr(11) );
    ce(1)  <= cs and not( addr(13) ) and not( addr(12) ) and      addr(11)  ;
    ce(2)  <= cs and not( addr(13) ) and      addr(12)   and not( addr(11) );
    ce(3)  <= cs and not( addr(13) ) and      addr(12)   and      addr(11)  ;
    ce(4)  <= cs and      addr(13)   and not( addr(12) ) and not( addr(11) );
    ce(5)  <= cs and      addr(13)   and not( addr(12) ) and      addr(11)  ;
    ce(6)  <= cs and      addr(13)   and      addr(12)   and not( addr(11) );
    ce(7)  <= cs and      addr(13)   and      addr(12)   and      addr(11)  ;
end process;
 
end architecture rtl;