Subversion Repositories System09

--===========================================================================----
--
--  S Y N T H E Z I A B L E    System09 - SOC.
--
--  www.OpenCores.Org - February 2007
--  This core adheres to the GNU public license  
--
-- File name      : System09_Xess_XSA-3S1000.vhd
--
-- Purpose        : Top level file for 6809 compatible system on a chip
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
--                  Implemented With XESS XSA-3S1000 FPGA board.
--                  *** Note ***
--                  This configuration can run Flex9 however it only has
--                  32k bytes of user memory and the VDU is monochrome
--                  The design needs to be updated to use the SDRAM on 
--                  the XSA-3S1000 board.
--                  This configuration also lacks a DAT so cannot use
--                  the RAM Disk features of SYS09BUG.
--
-- Dependencies   : ieee.Std_Logic_1164
--                  ieee.std_logic_unsigned
--                  ieee.std_logic_arith
--                  ieee.numeric_std
--                  unisim.vcomponents
--
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
--                  cpu09      (cpu09.vhd)          CPU core
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
--                  timer      (timer.vhd)            Interrupt timer
--                  trap       (trap.vhd)             Bus condition trap logic
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
--                  
-- 
-- Author         : John E. Kent      
--                  dilbert57@opencores.org      
--
-- Memory Map     :
--
-- $0000 - User program RAM (32K Bytes)
-- $C000 - Flex Operating System memory (8K Bytes)
-- $E000 - ACIA (SWTPc)
-- $E010 - Reserved for FD1771 FDC (SWTPc)
-- $E050 - Timer
-- $E060 - Bus trap
-- $E070 - Reserced for Parallel I/O (B5-X300)
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
-- $F000 - Sys09Bug monitor Program (4K Bytes)
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
-- Version 0.1 - 20 March 2003
-- Version 0.2 - 30 March 2003
-- Version 0.3 - 29 April 2003
-- Version 0.4 - 29 June 2003
--
-- Version 0.5 - 19 July 2003
-- prints out "Hello World"
--
-- Version 0.6 - 5 September 2003
-- Runs SBUG
--
-- Version 1.0- 6 Sep 2003 - John Kent
-- Inverted SysClk
-- Initial release to Open Cores
--
-- Version 1.1 - 17 Jan 2004 - John Kent
-- Updated miniUart.
--
-- Version 1.2 - 25 Jan 2004 - John Kent
-- removed signals "test_alu" and "test_cc" 
-- Trap hardware re-instated.
--
-- Version 1.3 - 11 Feb 2004 - John Kent
-- Designed forked off to produce System09_VDU
-- Added VDU component
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
-- UART Runs at 57.6 Kbps
--
-- Version 2.0 - 2 September 2004 - John Kent
-- ported to Digilent Xilinx Spartan3 starter board
-- removed Compact Flash and Trap Logic.
-- Replaced SBUG with KBug9s
--
-- Version 3.0 - 29th August 2006 - John Kent
-- Adapted to XSA-3S1000 board.
-- Removed DAT and miniUART.
-- Used 32KBytes of Block RAM.
--
-- Version 3.1 - 15th January 2007 - John Kent
-- Modified vdu8 interface
-- Added a clock divider
--
-- Version 3.2 - 25th February 2007 - John Kent
-- reinstated ACIA_6850 and ACIA_Clock
-- Updated VDU8 & Keyboard with generic parameters
-- Defined Constants for clock speed calculations
--
-- Version 3.3 - 1st July 2007 - John Kent
-- Made VDU mono to save on one RAMB16
-- Used distributed memory for Key Map ROM to save one RAMB16
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
-- Added timer and trap logic
-- Added IDE Interface for Compact Flash
-- Replaced KBug9s and stack with Sys09Bug.
--
-- Version 4.0 - 1st February 2008 - John kent
-- Replaced Block RAM with SDRAM Interface
-- Modified Hold timing for SDRAM
-- Added CF and Ethernet interface 
-- via the 16 bit peripheral bus at $E100
--
--===========================================================================--
library ieee;
   use ieee.std_logic_1164.all;
   use IEEE.STD_LOGIC_ARITH.ALL;
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
   use ieee.numeric_std.all;
library work;
   use work.common.all;
library unisim;
   use unisim.vcomponents.all;
 
entity system09 is
  port(
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
    SW2_N        : in  Std_logic;  -- Master Reset input (active low)
    SW3_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
 
    -- RS232 Port
    RS232_RXD    : in  Std_Logic;
    RS232_TXD    : out Std_Logic;
 
    -- Status 7 segment LED
    S            : out std_logic_vector(7 downto 0)
 
-- CPU Debug Interface signals
--    cpu_reset_o     : out Std_Logic;
--    cpu_clk_o       : out Std_Logic;
--    cpu_rw_o        : out std_logic;
--    cpu_vma_o       : out std_logic;
--    cpu_halt_o      : out std_logic;
--    cpu_hold_o      : out std_logic;
--    cpu_firq_o      : out std_logic;
--    cpu_irq_o       : out std_logic;
--    cpu_nmi_o       : out std_logic;
--    cpu_addr_o      : out std_logic_vector(15 downto 0);
--    cpu_data_in_o   : out std_logic_vector(7 downto 0);
--    cpu_data_out_o  : out std_logic_vector(7 downto 0);
 
  );
end system09;
 
-------------------------------------------------------------------------------
-- Architecture for System09
-------------------------------------------------------------------------------
architecture rtl of system09 is
 
  -----------------------------------------------------------------------------
  -- constants
  -----------------------------------------------------------------------------
 
  -- SDRAM
  constant MEM_CLK_FREQ         : natural := 100_000; -- operating frequency of Memory in KHz
  constant SYS_CLK_DIV          : real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
  constant PIPE_EN              : boolean := false;  -- if true, enable pipelined read operations
  constant MAX_NOP              : natural := 10000;  -- number of NOPs before entering self-refresh
  constant MULTIPLE_ACTIVE_ROWS : boolean := false;  -- if true, allow an active row in each bank
  constant DATA_WIDTH           : natural := 16;     -- host & SDRAM data width
  constant NROWS                : natural := 8192;   -- number of rows in SDRAM array
  constant NCOLS                : natural := 512;    -- number of columns in SDRAM array
  constant HADDR_WIDTH          : natural := 24;     -- host-side address width
  constant SADDR_WIDTH          : natural := 13;     -- SDRAM-side address width
 
  constant SYS_CLK_FREQ         : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000;  -- FPGA System Clock
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
 
  constant TRESET               : natural := 300;      -- min initialization interval (us)
  constant RST_CYCLES           : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000));  -- SDRAM power-on initialization interval
 
  type hold_state_type is ( hold_release_state, hold_request_state );
 
  -----------------------------------------------------------------------------
  -- Signals
  -----------------------------------------------------------------------------
  -- BOOT ROM
  signal rom_cs         : Std_logic;
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
 
  -- Flex Memory & Monitor Stack
  signal flex_cs        : Std_logic;
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
 
  -- ACIA/UART Interface signals
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);  
  signal acia_cs        : Std_Logic;
  signal acia_irq       : Std_Logic;
  signal acia_clk       : Std_Logic;
  signal rxd            : Std_Logic;
  signal txd            : Std_Logic;
  signal DCD_n          : Std_Logic;
  signal RTS_n          : Std_Logic;
  signal CTS_n          : Std_Logic;
 
  -- RAM
  signal ram_cs         : std_logic; -- memory chip select
  signal ram_data_out   : std_logic_vector(7 downto 0);
  signal ram_rd_req     : std_logic; -- ram read request (asynch set on ram read, cleared falling CPU clock edge)
  signal ram_wr_req     : std_logic; -- ram write request (set on rising CPU clock edge, asynch clear on acknowledge) 
  signal ram_hold       : std_logic; -- hold off slow accesses
  signal ram_release    : std_logic; -- Release ram hold
 
  -- CPU Interface signals
  signal cpu_reset      : Std_Logic;
  signal cpu_clk        : Std_Logic;
  signal cpu_rw         : std_logic;
  signal cpu_vma        : std_logic;
  signal cpu_halt       : std_logic;
  signal cpu_hold       : std_logic;
  signal cpu_firq       : std_logic;
  signal cpu_irq        : std_logic;
  signal cpu_nmi        : std_logic;
  signal cpu_addr       : std_logic_vector(15 downto 0);
  signal cpu_data_in    : std_logic_vector(7 downto 0);
  signal cpu_data_out   : std_logic_vector(7 downto 0);
 
  -- Dynamic Address Translation
  signal dat_cs       : std_logic;
  signal dat_addr     : std_logic_vector(7 downto 0);
 
  -- timer
  signal timer_data_out : std_logic_vector(7 downto 0);
  signal timer_cs       : std_logic;
  signal timer_irq      : std_logic;
 
  -- trap
  signal trap_cs        : std_logic;
  signal trap_data_out  : std_logic_vector(7 downto 0);
  signal trap_irq       : std_logic;
 
  -- Peripheral Bus port
  signal pb_data_out   : std_logic_vector(7 downto 0);
  signal pb_cs         : std_logic;	  -- peripheral bus chip select
  signal pb_wru        : std_logic;	  -- upper byte write strobe
  signal pb_wrl        : std_logic;	  -- lower byte write strobe
  signal pb_rdu        : std_logic;	  -- upper byte read strobe
  signal pb_rdl        : std_logic;	  -- lower byte read strobe
  signal pb_hold       : std_logic;	  -- hold peripheral bus access
  signal pb_release    : std_logic;	  -- release hold of peripheral bus
  signal pb_count      : std_logic_vector(3 downto 0); -- hold counter
  signal pb_hold_state : hold_state_type;
  signal pb_wreg       : std_logic_vector(7 downto 0); -- lower byte write register
  signal pb_rreg       : std_logic_vector(7 downto 0); -- lower byte read register
 
  signal rst_i         : std_logic;     -- internal reset signal
  signal clk_i         : std_logic;     -- internal master clock signal
 
  -- signals that go through the SDRAM host-side interface
  signal opBegun       : std_logic;        -- SDRAM operation started indicator
  signal earlyBegun    : std_logic;        -- SDRAM operation started indicator
  signal ramDone       : std_logic;        -- SDRAM operation complete indicator
  signal rdDone        : std_logic;        -- SDRAM read operation complete indicator
  signal wrDone        : std_logic;        -- SDRAM write operation complete indicator
  signal hAddr         : std_logic_vector(HADDR_WIDTH-1 downto 0);  -- host address bus
  signal hDIn          : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data to SDRAM
  signal hDOut         : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data from SDRAM
  signal hRd           : std_logic;        -- host-side read control signal
  signal hWr           : std_logic;        -- host-side write control signal
  signal hUds          : std_logic;        -- host-side upper data strobe
  signal hLds          : std_logic;        -- host-side lower data strobe
  signal rdPending     : std_logic;        -- read operation pending in SDRAM pipeline
  type ram_type is (ram_state_0, 
                    ram_state_rd1, ram_state_rd2,
                    ram_state_wr1,
						  ram_state_3 );
  signal ram_state     : ram_type;
 
	 signal flash_ce_n   :  std_logic;
    signal rs232_cts    :   Std_Logic;
    signal rs232_rts    :  Std_Logic;
 
--  signal BaudCount   : std_logic_vector(5 downto 0);
 
  signal CountL        : std_logic_vector(23 downto 0);
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
  signal Clk25         : std_logic;
 
-----------------------------------------------------------------
--
-- CPU09 CPU core
--
-----------------------------------------------------------------
 
component cpu09
  port (    
    clk:      in  std_logic;
    rst:      in  std_logic;
    vma:      out std_logic;
    addr:     out std_logic_vector(15 downto 0);
    rw:       out std_logic;     -- Asynchronous memory interface
    data_out: out std_logic_vector(7 downto 0);
    data_in:  in  std_logic_vector(7 downto 0);
    irq:      in  std_logic;
    firq:     in  std_logic;
    nmi:      in  std_logic;
    halt:     in  std_logic;
    hold:     in  std_logic
  );
end component;
 
----------------------------------------
--
-- 4K Block RAM Monitor ROM
-- $F000 - $FFFF
--
----------------------------------------
 
component mon_rom
  Port (
    clk   : in  std_logic;
    rst   : in  std_logic;
    cs    : in  std_logic;
    rw    : in  std_logic;
    addr  : in  std_logic_vector (11 downto 0);
    data_out : out std_logic_vector (7 downto 0);
    data_in : in  std_logic_vector (7 downto 0)
  );
end component;
 
----------------------------------------
--
-- 8KBytes Block RAM for FLEX9
-- $C000 - $DFFF
--
----------------------------------------
 
component flex_ram
  Port (
    clk      : in  std_logic;
    rst      : in  std_logic;
    cs       : in  std_logic;
    rw       : in  std_logic;
    addr     : in  std_logic_vector (12 downto 0);
    data_out    : out std_logic_vector (7 downto 0);
    data_in    : in  std_logic_vector (7 downto 0)
  );
end component;
 
-----------------------------------------------------------------
--
-- 6850 Compatible ACIA / UART
--
-----------------------------------------------------------------
 
component acia6850
  port (
    clk      : in  Std_Logic;  -- System Clock
    rst      : in  Std_Logic;  -- Reset input (active high)
    cs       : in  Std_Logic;  -- miniUART Chip Select
    rw       : in  Std_Logic;  -- Read / Not Write
    addr     : in  Std_Logic;  -- Register Select
    data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
    data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
    irq      : out Std_Logic;  -- Interrupt
    RxC      : in  Std_Logic;  -- Receive Baud Clock
    TxC      : in  Std_Logic;  -- Transmit Baud Clock
    RxD      : in  Std_Logic;  -- Receive Data
    TxD      : out Std_Logic;  -- Transmit Data
    DCD_n    : in  Std_Logic;  -- Data Carrier Detect
    CTS_n    : in  Std_Logic;  -- Clear To Send
    RTS_n    : out Std_Logic   -- Request To send
  );
end component;
 
-----------------------------------------------------------------
--
-- ACIA Clock divider
--
-----------------------------------------------------------------
 
component ACIA_Clock
  generic (
    SYS_CLK_FREQ  : integer :=  SYS_CLK_FREQ;
    ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
  );   
  port (
    clk      : in  Std_Logic;  -- System Clock Input
    ACIA_clk : out Std_logic   -- ACIA Clock output
  );
end component;
 
----------------------------------------
--
-- Timer module
--
----------------------------------------
 
component timer
  port (
    clk       : in std_logic;
    rst       : in std_logic;
    cs        : in std_logic;
    rw        : in std_logic;
    addr      : in std_logic;
    data_in   : in std_logic_vector(7 downto 0);
    data_out  : out std_logic_vector(7 downto 0);
    irq       : out std_logic
  );
end component;
 
------------------------------------------------------------
--
-- Bus Trap logic
--
------------------------------------------------------------
 
component trap
  port (   
    clk        : in  std_logic;
    rst        : in  std_logic;
    cs         : in  std_logic;
    rw         : in  std_logic;
    vma        : in  std_logic;
    addr       : in  std_logic_vector(15 downto 0);
    data_in    : in  std_logic_vector(7 downto 0);
    data_out   : out std_logic_vector(7 downto 0);
    irq        : out std_logic
  );
end component;
 
----------------------------------------
--
-- Dynamic Address Translation Registers
--
----------------------------------------
 
component dat_ram
  port (
    clk      : in  std_logic;
    rst      : in  std_logic;
    cs       : in  std_logic;
    rw       : in  std_logic;
    addr_lo  : in  std_logic_vector(3 downto 0);
    addr_hi  : in  std_logic_vector(3 downto 0);
    data_in  : in  std_logic_vector(7 downto 0);
    data_out : out std_logic_vector(7 downto 0)
  );
end component;
 
 
--
-- Clock buffer
--
 
component BUFG 
   Port (
     i: in std_logic;
     o: out std_logic
  );
end component;
 
begin
 
  -----------------------------------------------------------------------------
  -- Instantiation of internal components
  -----------------------------------------------------------------------------
 
  my_cpu : cpu09
    port map (    
      clk       => cpu_clk,
      rst       => cpu_reset,
      vma       => cpu_vma,
      addr      => cpu_addr(15 downto 0),
      rw        => cpu_rw,
      data_out  => cpu_data_out,
      data_in   => cpu_data_in,
      irq       => cpu_irq,
      firq      => cpu_firq,
      nmi       => cpu_nmi,
      halt      => cpu_halt,
      hold      => cpu_hold
    );
 
  my_rom : mon_rom
    port map (
      clk   => cpu_clk,
      rst   => cpu_reset,
      cs    => rom_cs,
      rw    => '1',
      addr  => cpu_addr(11 downto 0),
      data_in => cpu_data_out,
      data_out => rom_data_out
    );
 
  my_flex : flex_ram
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      cs        => flex_cs,
      rw        => cpu_rw,
      addr      => cpu_addr(12 downto 0),
      data_out     => flex_data_out,
      data_in     => cpu_data_out
    );
 
  my_acia  : acia6850
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      cs        => acia_cs,
      rw        => cpu_rw,
      addr      => cpu_addr(0),
      data_in   => cpu_data_out,
      data_out  => acia_data_out,
      irq       => acia_irq,
      RxC       => acia_clk,
      TxC       => acia_clk,
      RxD       => rxd,
      TxD       => txd,
      DCD_n     => dcd_n,
      CTS_n     => cts_n,
      RTS_n     => rts_n
    );
 
  my_ACIA_Clock : ACIA_Clock
    generic map(
      SYS_CLK_FREQ  =>  SYS_CLK_FREQ,
      ACIA_CLK_FREQ => ACIA_CLK_FREQ
    ) 
    port map(
      clk        => Clk_i,
      acia_clk   => acia_clk
    ); 
 
  ----------------------------------------
  --
  -- Timer Module
  --
  ----------------------------------------
  my_timer  : timer
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      cs        => timer_cs,
      rw        => cpu_rw,
      addr      => cpu_addr(0),
      data_in   => cpu_data_out,
      data_out  => timer_data_out,
      irq       => timer_irq
    );
 
  ----------------------------------------
  --
  -- Bus Trap Interrupt logic
  --
  ----------------------------------------
  my_trap : trap
    port map (  
      clk        => cpu_clk,
      rst        => cpu_reset,
      cs         => trap_cs,
      rw         => cpu_rw,
      vma        => cpu_vma,
      addr       => cpu_addr,
      data_in    => cpu_data_out,
      data_out   => trap_data_out,
      irq        => trap_irq
    );
 
  my_dat : dat_ram
    port map (
      clk       => cpu_clk,
      rst       => cpu_reset,
      cs        => dat_cs,
      rw        => cpu_rw,
      addr_hi   => cpu_addr(15 downto 12),
      addr_lo   => cpu_addr(3 downto 0),
      data_in   => cpu_data_out,
      data_out  => dat_addr(7 downto 0)
    );
 
  cpu_clk_buffer : BUFG
    port map(
      i => Clk25,
      o => cpu_clk
    );    
 
  ----------------------------------------------------------------------
  --
  -- Process to decode memory map
  --
  ----------------------------------------------------------------------
 
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
                     dat_addr,
                     rom_data_out,
                     flex_data_out,
                     acia_data_out,
                     pb_data_out,
                     timer_data_out,
                     trap_data_out,
                     ram_data_out
                     )
  begin
    cpu_data_in <= (others=>'0');
    dat_cs      <= '0';
    rom_cs      <= '0';
    flex_cs     <= '0';
    acia_cs     <= '0';
    timer_cs    <= '0';
    trap_cs     <= '0';
    pb_cs       <= '0';
    ram_cs      <= '0';
 
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
      cpu_data_in <= rom_data_out;
      dat_cs      <= cpu_vma;              -- write DAT
      rom_cs      <= cpu_vma;              -- read  ROM
 
    --
    -- Sys09Bug Monitor ROM $F000 - $FFFF
    --
    elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
      cpu_data_in <= rom_data_out;
      rom_cs      <= cpu_vma;
 
    --
    -- IO Devices $E000 - $E7FF
    --
    elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
      case cpu_addr(11 downto 8) is
        --
        -- SWTPC peripherals from $E000 to $E0FF
        --
        when "0000" =>
          case cpu_addr(7 downto 4) is
          --
          -- Console Port ACIA $E000 - $E00F
          --
            when "0000" => -- $E000
              cpu_data_in <= acia_data_out;
              acia_cs     <= cpu_vma;
 
            --
            -- Reserved
            -- Floppy Disk Controller port $E010 - $E01F
            --
 
            --
            -- Reserved SWTPc MP-T Timer $E040 - $E04F
            --
            when "0100" => -- $E040
              cpu_data_in <= (others=> '0');
 
            --
            -- Timer $E050 - $E05F
            --
            when "0101" => -- $E050
              cpu_data_in <= timer_data_out;
              timer_cs    <= cpu_vma;
 
            --
            -- Bus Trap Logic $E060 - $E06F
            --
            when "0110" => -- $E060
              cpu_data_in <= trap_data_out;
              trap_cs     <= cpu_vma;
 
            --
            -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
            --
 
            --
            -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
            --
 
            --
            -- Remaining 6 slots reserved for non SWTPc Peripherals
            --
            when others => -- $E0A0 to $E0FF
              null;
          end case;
 
        --
        -- $E200 to $EFFF reserved for future use
        --
        when others =>
           null;
      end case;
 
    --
    -- Flex RAM $0C000 - $0DFFF
    --
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
      cpu_data_in <= flex_data_out;
      flex_cs     <= cpu_vma;
 
    --
    -- Everything else is RAM
    --
    else
      cpu_data_in <= ram_data_out;
      ram_cs      <= cpu_vma;
    end if;
 
  end process;
 
  --
  -- Interrupts and other bus control signals
  --
  interrupts : process( SW3_N,
                      pb_cs, pb_hold, pb_release, ram_hold,
                      acia_irq, 
                      trap_irq, 
                      timer_irq
                      )
  begin
    pb_hold    <= pb_cs and (not pb_release);
    cpu_irq    <= acia_irq;
    cpu_nmi    <= trap_irq or not( SW3_N );
    cpu_firq   <= timer_irq;
    cpu_halt   <= '0';
    cpu_hold   <= pb_hold or ram_hold;
    FLASH_CE_N <= '1';
  end process;
 
  --
  -- Flash 7 segment LEDS
  --
  my_led_flasher: process( clk_i, rst_i, CountL )
  begin
    if rst_i = '1' then
         CountL <= "000000000000000000000000";
    elsif rising_edge(clk_i) then
         CountL <= CountL + 1;
    end if;
    --S(7 downto 0) <= CountL(23 downto 16);
  end process;
 
  --
  -- Generate CPU & Pixel Clock from Memory Clock
  --
  my_prescaler : process( clk_i, clk_count )
  begin
    if rising_edge( clk_i ) then
      if clk_count = 0 then
        clk_count <= CPU_CLK_DIV-1;
      else
        clk_count <= clk_count - 1;
      end if;
      if clk_count = 0 then
         clk25 <= '0';
      elsif clk_count = (CPU_CLK_DIV/2) then
         clk25 <= '1';
      end if;
    end if;
  end process;
 
  --
  -- Reset button and reset timer
  --
  my_switch_assignments : process( rst_i, SW2_N)
  begin
    rst_i <= not SW2_N;
    cpu_reset <= rst_i;
  end process;
 
  --
  -- RS232 signals:
  --
  my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n )
  begin
    rxd       <= RS232_RXD;
    cts_n     <= RS232_CTS;
    dcd_n     <= '0';
    RS232_TXD <= txd;
    RS232_RTS <= rts_n;
  end process;
 
  --
  -- CPU read data request on rising CPU clock edge
  --
  ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release )
  begin
    if hRd = '1' then
      ram_rd_req   <= '0';
    elsif rising_edge(cpu_clk) then
      if (ram_cs = '1') and (cpu_rw = '1') and (ram_release = '1') then
        ram_rd_req   <= '1';
      end if;
    end if;
  end process;
 
  --
  -- CPU write data to RAM valid on rising CPU clock edge
  --
  ram_write_request: process( hWr, cpu_clk, ram_cs, cpu_rw, ram_release )
  begin
    if hWr = '1' then
       ram_wr_req   <= '0';
    elsif rising_edge(cpu_clk) then
      if (ram_cs = '1') and (cpu_rw = '0') and (ram_release = '1') then
        ram_wr_req   <= '1';
      end if;
    end if;
  end process;
 
  status_leds : process( rst_i, cpu_reset)
  begin
    S(7) <= rst_i;
    S(6) <= cpu_reset;
    S(2) <= countL(23);
    S(3) <= countL(22);
	 S(4) <= countL(21);
	 S(5) <= countL(20);
	 S(1) <= '1'; -- countL(19);
	 S(0) <= '0'; -- countL(18);
    --S(7 downto 4) <= "0000";
  end process;
 
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
--                      cpu_halt, cpu_hold,
--                      cpu_firq, cpu_irq, cpu_nmi,
--                      cpu_addr, cpu_data_out, cpu_data_in )
--  begin
--    cpu_reset_o    <= cpu_reset;
--    cpu_clk_o      <= cpu_clk;
--    cpu_rw_o       <= cpu_rw;
--    cpu_vma_o      <= cpu_vma;
--    cpu_halt_o     <= cpu_halt;
--    cpu_hold_o     <= cpu_hold;
--    cpu_firq_o     <= cpu_firq;
--    cpu_irq_o      <= cpu_irq;
--    cpu_nmi_o      <= cpu_nmi;
--    cpu_addr_o     <= cpu_addr;
--    cpu_data_out_o <= cpu_data_out;
--    cpu_data_in_o  <= cpu_data_in;
--  end process;
 
end rtl; --===================== End of architecture =======================--