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https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
[/] [System09/] [trunk/] [rtl/] [System09_Xess_XuLA/] [iseconfig/] [System09_Xess_XuLA.projectmgr] - Rev 222
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<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="2" owner="projectmgr" name="System09_Xess_XuLA" >
<!--This is an ISE project configuration file.-->
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/My_System09 - rtl C:|VHDL|System09_sandbox_JK|rtl|System09_Xess_XuLA|System09_Xess_XuLA.vhd/XSASDRAM</ClosedNode>
<ClosedNode>/My_System09 - rtl C:|VHDL|System09_sandbox_JK|rtl|System09_Xess_XuLA|System09_Xess_XuLA.vhd/XSASDRAM/common</ClosedNode>
<ClosedNode>/My_System09 - rtl C:|VHDL|System09_sandbox_JK|rtl|System09_Xess_XuLA|System09_Xess_XuLA.vhd/my_keyboard - keyboard - rtl</ClosedNode>
<ClosedNode>/My_System09 - rtl C:|VHDL|System09_sandbox_JK|rtl|System09_Xess_XuLA|System09_Xess_XuLA.vhd/my_vdu - vdu8 - RTL</ClosedNode>
<ClosedNode>/My_System09 - rtl C:|VHDL|System09_sandbox_JK|rtl|System09_Xess_XuLA|System09_Xess_XuLA.vhd/u1 - XSASDRAMCntl - arch</ClosedNode>
<ClosedNode>/XSASDRAMCntl - arch C:|VHDL|System09_sandbox_JK|rtl|System09_Xess_XuLA|xsasdramcntl.vhd</ClosedNode>
<ClosedNode>/cpu09 - rtl C:|VHDL|System09_sandbox_JK|rtl|VHDL|cpu09.vhd</ClosedNode>
<ClosedNode>/ps2_keyboard - rtl C:|VHDL|System09_sandbox_JK|rtl|VHDL|ps2_keyboard.vhd</ClosedNode>
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<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>System09_Xess_XuLA</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
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<ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode>
</ClosedNodes>
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<SelectedItem>Compile HDL Simulation Libraries</SelectedItem>
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<CurrentItem>Compile HDL Simulation Libraries</CurrentItem>
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<ItemView guiview="File" >
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>acia6850.vhd</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
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</ClosedNodes>
<SelectedItems>
<SelectedItem>sdramcntl.vhd</SelectedItem>
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<CurrentItem>sdramcntl.vhd</CurrentItem>
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<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design/Map</ClosedNode>
<ClosedNode>Implement Design/Map/Generate Post-Map Static Timing</ClosedNode>
<ClosedNode>Implement Design/Place & Route</ClosedNode>
<ClosedNode>Implement Design/Translate</ClosedNode>
<ClosedNode>Synthesize - XST</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
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<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_PACKAGE_DECL" guiview="Process" >
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<CurrentItem/>
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<SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
<CopyAdditionalFiles/>
</Project>
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