URL https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [System09_Xilinx_ML506/] [my_system09.ucf] - Rev 90

Go to most recent revision | Compare with Previous | Blame | View Log
#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
# sys_clk = USER_CLK
NET  sys_clk             LOC="AH15";  # Bank 4, Vcco=3.3V, No DCI                           # sys_clk 100MHz clock
#
# PUSH BUTTONS
#
# rst_sw = FPGA_CPU_RESET_B
NET  rst_sw     LOC="E9";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors    # rst_sw
# nmi_sw = GPIO_SW_C
NET  nmi_sw            LOC="AJ6";   # Bank 18, Vcco=3.3V, No DCI                          # nmi_sw
#
# LEDs
#
# leds = GPIO_LED_...
NET  leds<0>              LOC="H18";   # Bank 3, Vcco=2.5V, No DCI                           # leds<0>
NET  leds<1>              LOC="L18";   # Bank 3, Vcco=2.5V, No DCI                           # leds<1>
NET  leds<2>              LOC="G15";   # Bank 3, Vcco=2.5V, No DCI                           # leds<2>
NET  leds<3>              LOC="AD26";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors    # leds<3>
NET  leds<4>              LOC="G16";   # Bank 3, Vcco=2.5V, No DCI                           # leds<4>
NET  leds<5>              LOC="AD25";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors    # leds<5>
NET  leds<6>              LOC="AD24";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors    # leds<6>
NET  leds<7>              LOC="AE24";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors    # leds<7>
#
# Switches
#
# switches = GPIO_DIP_SW...
NET  switches<0>          LOC="U25";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors    # switches<0>
NET  switches<1>          LOC="AG27";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors    # switches<1>
NET  switches<2>          LOC="AF25";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors    # switches<2>
NET  switches<3>          LOC="AF26";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors    # switches<3>
NET  switches<4>          LOC="AE27";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors    # switches<4>
NET  switches<5>          LOC="AE26";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors    # switches<5>
NET  switches<6>          LOC="AC25";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors    # switches<6>
NET  switches<7>          LOC="AC24";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors    # switches<7>
#
# PS/2 KEYBOARD
#
NET  ps2c                 LOC="T26";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors    # ps2c
NET  ps2d                 LOC="T25";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors    # ps2d
#
# UART
#
NET  rxd                  LOC="AG15";  # Bank 4, Vcco=3.3V, No DCI                           # rxd
NET  txd                  LOC="AG20";  # Bank 4, Vcco=3.3V, No DCI                           # txd
#
# VDU
#
NET  red                  LOC="AG23";  # Bank 2, Vcco=3.3V                                   # red=GPIO_LED_E
NET  green                LOC="AF13";  # Bank 2, Vcco=3.3V                                   # green=GPIO_LED_N
NET  blue                 LOC="E8";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors    # blue=GPIO_LED_C
NET  hs                   LOC="AG12";  # Bank 2, Vcco=3.3V                                   # hs=GPIO_LED_S
NET  vs                   LOC="AF23";  # Bank 2, Vcco=3.3V                                   # vs=GPIO_LED_W

#
# 7 SEGMENT DISPLAY
#

#
# RAM Address bus
#
#NET  SRAM_FLASH_A0        LOC="K12";   # Bank 1, Vcco=3.3V                                  # ram_addr<0>
#NET  SRAM_FLASH_A1        LOC="K13";   # Bank 1, Vcco=3.3V                                  # ram_addr<1>
#NET  SRAM_FLASH_A2        LOC="H23";   # Bank 1, Vcco=3.3V                                  # ram_addr<2>
#NET  SRAM_FLASH_A3        LOC="G23";   # Bank 1, Vcco=3.3V                                  # ram_addr<3>
#NET  SRAM_FLASH_A4        LOC="H12";   # Bank 1, Vcco=3.3V                                  # ram_addr<4>
#NET  SRAM_FLASH_A5        LOC="J12";   # Bank 1, Vcco=3.3V                                  # ram_addr<5>
#NET  SRAM_FLASH_A6        LOC="K22";   # Bank 1, Vcco=3.3V                                  # ram_addr<6>
#NET  SRAM_FLASH_A7        LOC="K23";   # Bank 1, Vcco=3.3V                                  # ram_addr<7>
#NET  SRAM_FLASH_A8        LOC="K14";   # Bank 1, Vcco=3.3V                                  # ram_addr<8>
#NET  SRAM_FLASH_A9        LOC="L14";   # Bank 1, Vcco=3.3V                                  # ram_addr<9>
#NET  SRAM_FLASH_A10       LOC="H22";   # Bank 1, Vcco=3.3V                                  # ram_addr<10>
#NET  SRAM_FLASH_A11       LOC="G22";   # Bank 1, Vcco=3.3V                                  # ram_addr<11>
#NET  SRAM_FLASH_A12       LOC="J15";   # Bank 1, Vcco=3.3V                                  # ram_addr<12>
#NET  SRAM_FLASH_A13       LOC="K16";   # Bank 1, Vcco=3.3V                                  # ram_addr<13>
#NET  SRAM_FLASH_A14       LOC="K21";   # Bank 1, Vcco=3.3V                                  # ram_addr<14>
#NET  SRAM_FLASH_A15       LOC="J22";   # Bank 1, Vcco=3.3V                                  # ram_addr<15>
#NET  SRAM_FLASH_A16       LOC="L16";   # Bank 1, Vcco=3.3V                                  # ram_addr<16>
#NET  SRAM_FLASH_A17       LOC="L15";   # Bank 1, Vcco=3.3V                                  # ram_addr<17>
#NET  SRAM_FLASH_A18       LOC="L20";   # Bank 1, Vcco=3.3V                                  # ram_addr<18> <= GND
#NET  SRAM_FLASH_A19       LOC="L21";   # Bank 1, Vcco=3.3V                                  # ram_addr<19> <= GND
#NET  SRAM_FLASH_A20       LOC="AE23";  # Bank 2, Vcco=3.3V                                  # ram_addr<20> <= GND
#NET  SRAM_FLASH_A21       LOC="AE22";  # Bank 2, Vcco=3.3V                                  # ram_addr<21> <= GND
#NET  SRAM_FLASH_WE_B      LOC="AF20";  # Bank 2, Vcco=3.3V                                  # ram_wen
#NET  SRAM_OE_B            LOC="B12";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors   # ram_oen
#
# RAM1
#

#NET  SRAM_FLASH_D0        LOC="AD19";  # Bank 2, Vcco=3.3V                                  # ram1_data<0>
#NET  SRAM_FLASH_D1        LOC="AE19";  # Bank 2, Vcco=3.3V                                  # ram1_data<1>
#NET  SRAM_FLASH_D2        LOC="AE17";  # Bank 2, Vcco=3.3V                                  # ram1_data<2>
#NET  SRAM_FLASH_D3        LOC="AF16";  # Bank 2, Vcco=3.3V                                  #
#NET  SRAM_FLASH_D4        LOC="AD20";  # Bank 2, Vcco=3.3V                                  #
#NET  SRAM_FLASH_D5        LOC="AE21";  # Bank 2, Vcco=3.3V                                  #
#NET  SRAM_FLASH_D6        LOC="AE16";  # Bank 2, Vcco=3.3V                                  #
#NET  SRAM_FLASH_D7        LOC="AF15";  # Bank 2, Vcco=3.3V                                  #
#NET  SRAM_FLASH_D8        LOC="AH13";  # Bank 4, Vcco=3.3V, No DCI                          #
#NET  SRAM_FLASH_D9        LOC="AH14";  # Bank 4, Vcco=3.3V, No DCI                          #
#NET  SRAM_FLASH_D10       LOC="AH19";  # Bank 4, Vcco=3.3V, No DCI                          #
#NET  SRAM_FLASH_D11       LOC="AH20";  # Bank 4, Vcco=3.3V, No DCI                          #
#NET  SRAM_FLASH_D12       LOC="AG13";  # Bank 4, Vcco=3.3V, No DCI                          #
#NET  SRAM_FLASH_D13       LOC="AH12";  # Bank 4, Vcco=3.3V, No DCI                          #
#NET  SRAM_FLASH_D14       LOC="AH22";  # Bank 4, Vcco=3.3V, No DCI                          #
#NET  SRAM_FLASH_D15       LOC="AG22";  # Bank 4, Vcco=3.3V, No DCI                          #



#
# Timing Constraints
#
NET "sys_clk" TNM_NET="sys_clk"; 
TIMESPEC "TS_clk"=PERIOD "sys_clk" 10 ns HIGH 50 %; 

#NET  SRAM_ADV_LD_B        LOC="H8";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  SRAM_BW0             LOC="D10";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  SRAM_BW1             LOC="D11";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  SRAM_BW2             LOC="J11";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  SRAM_BW3             LOC="K11";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  SRAM_CLK             LOC="AG21";  # Bank 4, Vcco=3.3V, No DCI      
#NET  SRAM_CLK             LOC="G8";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  SRAM_CS_B            LOC="J10";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  SRAM_D16             LOC="N10";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  SRAM_D17             LOC="E13";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  SRAM_D18             LOC="E12";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  SRAM_D19             LOC="L9";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  SRAM_D20             LOC="M10";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  SRAM_D21             LOC="E11";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  SRAM_D22             LOC="F11";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  SRAM_D23             LOC="L8";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  SRAM_D24             LOC="M8";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  SRAM_D25             LOC="G12";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  SRAM_D26             LOC="G11";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  SRAM_D27             LOC="C13";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  SRAM_D28             LOC="B13";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  SRAM_D29             LOC="K9";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  SRAM_D30             LOC="K8";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  SRAM_D31             LOC="J9";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  SRAM_DQP0            LOC="D12";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  SRAM_DQP1            LOC="C12";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  SRAM_DQP2            LOC="H10";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  SRAM_DQP3            LOC="H9";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  SRAM_FLASH_A0        LOC="K12";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A1        LOC="K13";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A2        LOC="H23";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A3        LOC="G23";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A4        LOC="H12";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A5        LOC="J12";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A6        LOC="K22";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A7        LOC="K23";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A8        LOC="K14";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A9        LOC="L14";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A10       LOC="H22";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A11       LOC="G22";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A12       LOC="J15";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A13       LOC="K16";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A14       LOC="K21";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A15       LOC="J22";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A16       LOC="L16";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A17       LOC="L15";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A18       LOC="L20";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A19       LOC="L21";   # Bank 1, Vcco=3.3V
#NET  SRAM_FLASH_A20       LOC="AE23";  # Bank 2, Vcco=3.3V
#NET  SRAM_FLASH_A21       LOC="AE22";  # Bank 2, Vcco=3.3V
#NET  SRAM_FLASH_D0        LOC="AD19";  # Bank 2, Vcco=3.3V
#NET  SRAM_FLASH_D1        LOC="AE19";  # Bank 2, Vcco=3.3V
#NET  SRAM_FLASH_D2        LOC="AE17";  # Bank 2, Vcco=3.3V
#NET  SRAM_FLASH_D3        LOC="AF16";  # Bank 2, Vcco=3.3V
#NET  SRAM_FLASH_D4        LOC="AD20";  # Bank 2, Vcco=3.3V
#NET  SRAM_FLASH_D5        LOC="AE21";  # Bank 2, Vcco=3.3V
#NET  SRAM_FLASH_D6        LOC="AE16";  # Bank 2, Vcco=3.3V
#NET  SRAM_FLASH_D7        LOC="AF15";  # Bank 2, Vcco=3.3V
#NET  SRAM_FLASH_D8        LOC="AH13";  # Bank 4, Vcco=3.3V, No DCI
#NET  SRAM_FLASH_D9        LOC="AH14";  # Bank 4, Vcco=3.3V, No DCI
#NET  SRAM_FLASH_D10       LOC="AH19";  # Bank 4, Vcco=3.3V, No DCI
#NET  SRAM_FLASH_D11       LOC="AH20";  # Bank 4, Vcco=3.3V, No DCI
#NET  SRAM_FLASH_D12       LOC="AG13";  # Bank 4, Vcco=3.3V, No DCI
#NET  SRAM_FLASH_D13       LOC="AH12";  # Bank 4, Vcco=3.3V, No DCI
#NET  SRAM_FLASH_D14       LOC="AH22";  # Bank 4, Vcco=3.3V, No DCI
#NET  SRAM_FLASH_D15       LOC="AG22";  # Bank 4, Vcco=3.3V, No DCI
#NET  SRAM_FLASH_WE_B      LOC="AF20";  # Bank 2, Vcco=3.3V
#NET  SRAM_MODE            LOC="A13";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  SRAM_OE_B            LOC="B12";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
Go to most recent revision | Compare with Previous | Blame | View Log
Browse

Tools

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [System09_Xilinx_ML506/] [my_system09.ucf] - Rev 90
