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https://opencores.org/ocsvn/System09/System09/trunk
Subversion Repositories System09
[/] [System09/] [trunk/] [rtl/] [System09_Xilinx_ML506/] [system09.xise] - Rev 222
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../../src/sys09bug/sys09s3s.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="../VHDL/ACIA_Clock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="../VHDL/acia6850.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="../VHDL/bit_funcs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="../VHDL/cpu09.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="../VHDL/datram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="../VHDL/timer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="../VHDL/trap.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="System09_Xilinx_ML506.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="ml506.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false"/>
<property xil_pn:name="Device" xil_pn:value="xc5vsx50t"/>
<property xil_pn:name="Device Family" xil_pn:value="Virtex5"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|system09|rtl"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/system09"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="system09"/>
<property xil_pn:name="Package" xil_pn:value="ff1136"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
<property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
</properties>
<bindings/>
<libraries/>
<partitions>
<partition xil_pn:name="/system09"/>
</partitions>
</project>
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