OpenCores
URL https://opencores.org/ocsvn/System68/System68/trunk

Subversion Repositories System68

[/] [System68/] [tags/] [arelease/] [vhdl/] [system68.ucf] - Rev 5

Go to most recent revision | Compare with Previous | Blame | View Log

#### UCF file created by Project Navigator
# Connector J9
NET "ram_addr<0>" LOC = "p108";
NET "ram_addr<1>" LOC = "p109";
NET "ram_addr<2>" LOC = "p110";
NET "ram_addr<3>" LOC = "p111";
NET "ram_addr<4>" LOC = "p112";
NET "ram_addr<5>" LOC = "p113";
NET "ram_addr<6>" LOC = "p114";
NET "ram_addr<7>" LOC = "p115";
NET "ram_csn" LOC = "p119";
NET "ram_addr<8>" LOC = "p120";
NET "ram_addr<9>" LOC = "p121";
NET "ram_addr<10>" LOC = "p122";
NET "ram_addr<11>" LOC = "p123";
NET "ram_addr<12>" LOC = "p125";
NET "ram_addr<13>" LOC = "p126";
NET "ram_addr<14>" LOC = "p127";
NET "ram_addr<15>" LOC = "p129";
NET "ram_addr<16>" LOC = "p132";
# Connector J6
NET "ram_data<0>" LOC = "p133";
NET "ram_data<1>" LOC = "p134";
NET "ram_data<2>" LOC = "p135";
NET "ram_data<3>" LOC = "p136";
NET "ram_data<4>" LOC = "p138";
NET "ram_data<5>" LOC = "p139";
NET "ram_data<6>" LOC = "p140";
NET "ram_data<7>" LOC = "p141";
NET "ram_data<8>" LOC = "p142";
NET "ram_data<9>" LOC = "p146";
NET "ram_data<10>" LOC = "p147";
NET "ram_data<11>" LOC = "p148";
NET "ram_data<12>" LOC = "p149";
NET "ram_data<13>" LOC = "p150";
NET "ram_data<14>" LOC = "p151";
NET "ram_data<15>" LOC = "p152";
NET "ram_wrun" LOC = "p153";
NET "ram_wrln" LOC = "p154";
# Connector J4
NET "porta<0>" LOC = "p160";
NET "porta<1>" LOC = "p161";
NET "porta<2>" LOC = "p162";
NET "porta<3>" LOC = "p163";
NET "porta<4>" LOC = "p164";
NET "porta<5>" LOC = "p165";
NET "porta<6>" LOC = "p166";
NET "porta<7>" LOC = "p167";
NET "portb<0>" LOC = "p168";
NET "portb<1>" LOC = "p172";
NET "portb<2>" LOC = "p173";
NET "portb<3>" LOC = "p174";
NET "portb<4>" LOC = "p175";
NET "portb<5>" LOC = "p176";
NET "portb<6>" LOC = "p178";
NET "portb<7>" LOC = "p179";
#NET "timer0_out" LOC = "p180";
#NET "timer0_in" LOC = "p182";
NET "timer_out" LOC = "p180";
# Connector J3
NET "portc<0>" LOC = "p181";
NET "portc<1>" LOC = "p187";
NET "portc<2>" LOC = "p188";
NET "portc<3>" LOC = "p189";
NET "portc<4>" LOC = "p191";
NET "portc<5>" LOC = "p192";
NET "portc<6>" LOC = "p193";
NET "portc<7>" LOC = "p194";
NET "portd<0>" LOC = "p195";
NET "portd<1>" LOC = "p199";
NET "portd<2>" LOC = "p200";
NET "portd<3>" LOC = "p201";
NET "portd<4>" LOC = "p202";
NET "portd<5>" LOC = "p203";
NET "portd<6>" LOC = "p204";
NET "portd<7>" LOC = "p205";
#NET "timer1_out" LOC = "p206";
#NET "timer1_in" LOC = "p185";
# Connector J10
NET "sysclk" LOC = "p77"; #pin 2
NET "led" LOC = "p49"; #pin 3
NET "uart_csn" LOC = "p57"; #pin 4
NET "test_rw" LOC = "p58"; #pin 5
NET "test_d0" LOC = "p59"; #pin 6
NET "test_d1" LOC = "p60"; #pin 7
NET "reset_n" LOC = "p61"; #pin 8
NET "test_cc<0>" LOC = "p67"; #pin 11
NET "test_cc<1>" LOC = "p68"; #pin 12
NET "test_cc<2>" LOC = "p69"; #pin 13
NET "test_cc<3>" LOC = "p70"; #pin 14
NET "test_cc<4>" LOC = "p71"; #pin 15
NET "test_cc<5>" LOC = "p73"; #pin 16
NET "test_cc<6>" LOC = "p74"; #pin 17
NET "test_cc<7>" LOC = "p75"; #pin 18
# Connector J11
NET "test_alu<0>" LOC = "p82"; #pin 3
NET "test_alu<1>" LOC = "p83"; #pin 4
NET "test_alu<2>" LOC = "p84"; #pin 5
NET "test_alu<3>" LOC = "p86"; #pin 6
NET "test_alu<4>" LOC = "p87"; #pin 7
NET "test_alu<5>" LOC = "p88"; #pin 8
NET "test_alu<6>" LOC = "p89"; #pin 9
NET "test_alu<7>" LOC = "p90"; #pin 10
NET "test_alu<8>" LOC = "p94"; #pin 11
NET "test_alu<9>" LOC = "p95"; #pin 12
NET "test_alu<10>" LOC = "p96"; #pin 13
NET "test_alu<11>" LOC = "p97"; #pin 14
NET "test_alu<12>" LOC = "p98"; #pin 15
NET "test_alu<13>" LOC = "p99"; #pin 16
NET "test_alu<14>" LOC = "p100"; #pin 17
NET "test_alu<15>" LOC = "p101"; #pin 18
# Connector J8
#NET "aux_clock" LOC = "p24"; #pin 2
NET "buzzer" LOC = "p27"; #pin 3
#NET "mouse_clock" LOC = "p29"; #pin 4
#NET "mouse_data" LOC = "p30"; #pin 5
NET "cts_n" LOC = "p31"; #pin 6
NET "rts_n" LOC = "p33"; #pin 7
NET "txbit" LOC = "p34"; #pin 8
NET "rxbit" LOC = "p35"; #pin 9
#NET "kb_clock" LOC = "p36"; #pin 10
#NET "kb_data" LOC = "p37"; #pin 11
NET "v_drive" LOC = "p41"; #pin 12
NET "h_drive" LOC = "p42"; #pin 13
NET "blue_lo" LOC = "p43";
NET "blue_hi" LOC = "p44";
NET "green_lo" LOC = "p45";
NET "green_hi" LOC = "p46";
NET "red_lo" LOC = "p47";
NET "red_hi" LOC = "p48";
INST "ram_addr<0>" TNM = "ram_addr";
INST "ram_addr<1>" TNM = "ram_addr";
INST "ram_addr<2>" TNM = "ram_addr";
INST "ram_addr<3>" TNM = "ram_addr";
INST "ram_addr<4>" TNM = "ram_addr";
INST "ram_addr<5>" TNM = "ram_addr";
INST "ram_addr<6>" TNM = "ram_addr";
INST "ram_addr<7>" TNM = "ram_addr";
INST "ram_addr<8>" TNM = "ram_addr";
INST "ram_addr<9>" TNM = "ram_addr";
INST "ram_addr<10>" TNM = "ram_addr";
INST "ram_addr<11>" TNM = "ram_addr";
INST "ram_addr<12>" TNM = "ram_addr";
INST "ram_addr<13>" TNM = "ram_addr";
INST "ram_addr<14>" TNM = "ram_addr";
INST "ram_addr<15>" TNM = "ram_addr";
INST "ram_addr<16>" TNM = "ram_addr";
INST "ram_data<0>" TNM = "ram_data";
INST "ram_data<1>" TNM = "ram_data";
INST "ram_data<2>" TNM = "ram_data";
INST "ram_data<3>" TNM = "ram_data";
INST "ram_data<4>" TNM = "ram_data";
INST "ram_data<5>" TNM = "ram_data";
INST "ram_data<6>" TNM = "ram_data";
INST "ram_data<7>" TNM = "ram_data";
INST "ram_data<8>" TNM = "ram_data";
INST "ram_data<9>" TNM = "ram_data";
INST "ram_data<10>" TNM = "ram_data";
INST "ram_data<11>" TNM = "ram_data";
INST "ram_data<12>" TNM = "ram_data";
INST "ram_data<13>" TNM = "ram_data";
INST "ram_data<14>" TNM = "ram_data";
INST "ram_data<15>" TNM = "ram_data";
INST "ram_wrln" TNM = "ram_wr";
INST "ram_wrun" TNM = "ram_wr";
INST "ram_csn" TNM = "ram_cs";
INST "test_alu<0>" TNM = "test_alu";
INST "test_alu<1>" TNM = "test_alu";
INST "test_alu<2>" TNM = "test_alu";
INST "test_alu<3>" TNM = "test_alu";
INST "test_alu<4>" TNM = "test_alu";
INST "test_alu<5>" TNM = "test_alu";
INST "test_alu<6>" TNM = "test_alu";
INST "test_alu<7>" TNM = "test_alu";
INST "test_alu<8>" TNM = "test_alu";
INST "test_alu<9>" TNM = "test_alu";
INST "test_alu<10>" TNM = "test_alu";
INST "test_alu<11>" TNM = "test_alu";
INST "test_alu<12>" TNM = "test_alu";
INST "test_alu<13>" TNM = "test_alu";
INST "test_alu<14>" TNM = "test_alu";
INST "test_alu<15>" TNM = "test_alu";
INST "test_cc<0>" TNM = "test_cc";
INST "test_cc<1>" TNM = "test_cc";
INST "test_cc<2>" TNM = "test_cc";
INST "test_cc<3>" TNM = "test_cc";
INST "test_cc<4>" TNM = "test_cc";
INST "test_cc<5>" TNM = "test_cc";
INST "test_cc<6>" TNM = "test_cc";
INST "test_cc<7>" TNM = "test_cc";
TIMEGRP "ram_cs" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_wr" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_addr" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_data" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_data" OFFSET = IN 15 ns BEFORE "sysclk";
TIMEGRP "test_alu" OFFSET = OUT 90 ns AFTER "sysclk";
TIMEGRP "test_cc" OFFSET = OUT 90 ns AFTER "sysclk";
NET "sysclk" TNM_NET = "sysclk";
TIMESPEC "TS_sysclk" = PERIOD "sysclk" 100 ns HIGH 50 %;
NET "ram_addr<0>" FAST;
NET "ram_addr<1>" FAST;
NET "ram_addr<2>" FAST;
NET "ram_addr<3>" FAST;
NET "ram_addr<4>" FAST;
NET "ram_addr<5>" FAST;
NET "ram_addr<6>" FAST;
NET "ram_addr<7>" FAST;
NET "ram_addr<8>" FAST;
NET "ram_addr<9>" FAST;
NET "ram_addr<10>" FAST;
NET "ram_addr<11>" FAST;
NET "ram_addr<12>" FAST;
NET "ram_addr<13>" FAST;
NET "ram_addr<14>" FAST;
NET "ram_addr<15>" FAST;
NET "ram_addr<16>" FAST;
NET "ram_csn" FAST;
NET "ram_data<0>" FAST;
NET "ram_data<1>" FAST;
NET "ram_data<2>" FAST;
NET "ram_data<3>" FAST;
NET "ram_data<4>" FAST;
NET "ram_data<5>" FAST;
NET "ram_data<6>" FAST;
NET "ram_data<7>" FAST;
NET "ram_data<8>" FAST;
NET "ram_data<9>" FAST;
NET "ram_data<10>" FAST;
NET "ram_data<11>" FAST;
NET "ram_data<12>" FAST;
NET "ram_data<13>" FAST;
NET "ram_data<14>" FAST;
NET "ram_data<15>" FAST;
NET "ram_wrln" FAST;
NET "ram_wrun" FAST;

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.