OpenCores
URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

[/] [a-z80/] [trunk/] [cpu/] [control/] [ir.bsf] - Rev 15

Go to most recent revision | Compare with Previous | Blame | View Log

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
        (rect 16 16 216 144)
        (text "ir" (rect 5 0 12 14)(font "Arial" (font_size 8)))
        (text "inst" (rect 8 112 25 124)(font "Arial" ))
        (port
                (pt 0 32)
                (input)
                (text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
                (text "db[7..0]" (rect 21 27 63 41)(font "Arial" (font_size 8)))
                (line (pt 0 32)(pt 16 32)(line_width 3))
        )
        (port
                (pt 0 48)
                (input)
                (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
                (text "clk" (rect 21 43 36 57)(font "Arial" (font_size 8)))
                (line (pt 0 48)(pt 16 48))
        )
        (port
                (pt 0 64)
                (input)
                (text "ctl_ir_we" (rect 0 0 53 14)(font "Arial" (font_size 8)))
                (text "ctl_ir_we" (rect 21 59 74 73)(font "Arial" (font_size 8)))
                (line (pt 0 64)(pt 16 64))
        )
        (port
                (pt 0 80)
                (input)
                (text "hold_clk_wait" (rect 0 0 77 14)(font "Arial" (font_size 8)))
                (text "hold_clk_wait" (rect 21 75 98 89)(font "Arial" (font_size 8)))
                (line (pt 0 80)(pt 16 80))
        )
        (port
                (pt 0 96)
                (input)
                (text "nreset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
                (text "nreset" (rect 21 91 57 105)(font "Arial" (font_size 8)))
                (line (pt 0 96)(pt 16 96))
        )
        (port
                (pt 200 32)
                (output)
                (text "opcode[7..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
                (text "opcode[7..0]" (rect 109 27 179 41)(font "Arial" (font_size 8)))
                (line (pt 200 32)(pt 184 32)(line_width 3))
        )
        (drawing
                (rectangle (rect 16 16 184 112))
        )
)

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.