Subversion Repositories a-z80

#ChipScope Core Inserter Project File Version 3.0
#Sat Mar 05 11:38:40 CST 2016
Project.device.designInputFile=R\:\\Z80\\host\\basic_nexys3\\work\\host_cs.ngc
Project.device.designOutputFile=R\:\\Z80\\host\\basic_nexys3\\work\\host_cs.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=R\:\\Z80\\host\\basic_nexys3\\work\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=
Project.filter<10>=*d*
Project.filter<11>=*sw*
Project.filter<12>=*4u*
Project.filter<13>=*db2*
Project.filter<14>=*db1*
Project.filter<15>=*db0*
Project.filter<16>=*rfsh*
Project.filter<17>=*M1*
Project.filter<18>=m1
Project.filter<1>=bus_*
Project.filter<2>=GPIO_1*
Project.filter<3>=GPIO_0*
Project.filter<4>=*T*
Project.filter<5>=T*
Project.filter<6>=*ctl_reg*
Project.filter<7>=ctl_reg*
Project.filter<8>=GPIO_2*
Project.filter<9>=*D*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=clk_cpu
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=GPIO_0_0_OBUF
Project.unit<0>.dataChannel<10>=GPIO_2_0_OBUFT
Project.unit<0>.dataChannel<11>=GPIO_2_1_OBUFT
Project.unit<0>.dataChannel<12>=GPIO_2_2_OBUFT
Project.unit<0>.dataChannel<13>=GPIO_2_3_OBUFT
Project.unit<0>.dataChannel<14>=GPIO_2_4_OBUFT
Project.unit<0>.dataChannel<15>=GPIO_2_5_OBUFT
Project.unit<0>.dataChannel<16>=GPIO_2_6_OBUFT
Project.unit<0>.dataChannel<17>=GPIO_2_7_OBUFT
Project.unit<0>.dataChannel<18>=z80_/ir_ opcode<0>
Project.unit<0>.dataChannel<19>=z80_/ir_ opcode<1>
Project.unit<0>.dataChannel<1>=GPIO_0_1_OBUF
Project.unit<0>.dataChannel<20>=z80_/ir_ opcode<2>
Project.unit<0>.dataChannel<21>=z80_/ir_ opcode<3>
Project.unit<0>.dataChannel<22>=z80_/ir_ opcode<4>
Project.unit<0>.dataChannel<23>=z80_/ir_ opcode<5>
Project.unit<0>.dataChannel<24>=z80_/ir_ opcode<6>
Project.unit<0>.dataChannel<25>=z80_/ir_ opcode<7>
Project.unit<0>.dataChannel<26>=nRD
Project.unit<0>.dataChannel<27>=nWR
Project.unit<0>.dataChannel<28>=z80_/nM1_out
Project.unit<0>.dataChannel<29>=z80_/nRFSH_out
Project.unit<0>.dataChannel<2>=GPIO_0_2_OBUF
Project.unit<0>.dataChannel<30>=z80_/db0<0>
Project.unit<0>.dataChannel<31>=z80_/db0<1>
Project.unit<0>.dataChannel<32>=z80_/db1<0>
Project.unit<0>.dataChannel<33>=z80_/db1<1>
Project.unit<0>.dataChannel<34>=z80_/db2<0>
Project.unit<0>.dataChannel<35>=z80_/db2<1>
Project.unit<0>.dataChannel<36>=z80_/ctl_reg_out_hi
Project.unit<0>.dataChannel<37>=z80_/ctl_reg_out_lo
Project.unit<0>.dataChannel<38>=z80_/ctl_sw_4u
Project.unit<0>.dataChannel<39>=z80_/ctl_sw_4d
Project.unit<0>.dataChannel<3>=GPIO_0_3_OBUF
Project.unit<0>.dataChannel<40>=z80_/ctl_reg_in_lo
Project.unit<0>.dataChannel<41>=z80_/ctl_reg_in_hi
Project.unit<0>.dataChannel<42>=z80_/sequencer_ DFFE_T1_ff
Project.unit<0>.dataChannel<43>=z80_/sequencer_ DFFE_T2_ff
Project.unit<0>.dataChannel<44>=z80_/sequencer_ DFFE_T3_ff
Project.unit<0>.dataChannel<45>=z80_/sequencer_ DFFE_T4_ff
Project.unit<0>.dataChannel<46>=z80_/sequencer_ DFFE_T5_ff
Project.unit<0>.dataChannel<47>=z80_/pin_control_ bus_db_pin_re
Project.unit<0>.dataChannel<48>=z80_/pin_control_ bus_ab_pin_we
Project.unit<0>.dataChannel<49>=z80_/pin_control_ bus_db_pin_oe
Project.unit<0>.dataChannel<4>=GPIO_0_4_OBUF
Project.unit<0>.dataChannel<5>=GPIO_0_5_OBUF
Project.unit<0>.dataChannel<6>=GPIO_0_6_OBUF
Project.unit<0>.dataChannel<7>=GPIO_0_7_OBUF
Project.unit<0>.dataChannel<8>=GPIO_1_0_OBUF
Project.unit<0>.dataChannel<9>=GPIO_1_1_OBUF
Project.unit<0>.dataDepth=1024
Project.unit<0>.dataEqualsTrigger=false
Project.unit<0>.dataPortWidth=50
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=z80_/nreset
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchType<0><0>=5
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=1
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro