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[/] [a-z80/] [trunk/] [host/] [basic_nexys3/] [ipcore_dir/] [clock/] [simulation/] [functional/] [simulate_mti.bat] - Rev 8
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REM file: simulate_mti.bat
REM
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
REM
REM This file contains confidential and proprietary information
REM of Xilinx, Inc. and is protected under U.S. and
REM international copyright and other intellectual property
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REM
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REM
REM set up the working directory
vlib work
REM compile all of the files
vlog -work work %XILINX%\verilog\src\glbl.v
vlog -work work ..\..\..\clock.v
vlog -work work ..\..\example_design\clock_exdes.v
vlog -work work ..\clock_tb.v
REM run the simulation
vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.clock_tb work.glbl