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[/] [a-z80/] [trunk/] [host/] [basic_nexys3/] [ipcore_dir/] [clock/] [simulation/] [functional/] [simulate_mti.do] - Rev 8
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# file: simulate_mti.do
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
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# set up the working directory
set work work
vlib work
# compile all of the files
vlog -work work $env(XILINX)/verilog/src/glbl.v
vlog -work work ../../../clock.v
vlog -work work ../../example_design/clock_exdes.v
vlog -work work ../clock_tb.v
# run the simulation
vsim -t ps -voptargs="+acc" -L unisims_ver work.clock_tb work.glbl
do wave.do
log clock_tb/dut/counter
log -r /*
run 50000ns