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[/] [a-z80/] [trunk/] [host/] [basic_nexys3/] [ipcore_dir/] [clock.xise] - Rev 17
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<!-- ISE source project file created by Project Navigator. -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
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<file xil_pn:name="clock.ucf" xil_pn:type="FILE_UCF">
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<file xil_pn:name="clock.v" xil_pn:type="FILE_VERILOG">
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<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|clock" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="clock.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clock" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_DesignName" xil_pn:value="clock" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-03-05T09:25:25" xil_pn:valueState="non-default"/>
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