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[/] [a-z80/] [trunk/] [host/] [basic_nexys3/] [ipcore_dir/] [ila.cdc] - Rev 15

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#ChipScope Core Generator Project File Version 3.0
#Tue Feb 23 19:15:38 Central Standard Time 2016
SignalExport.clockChannel=CLK
SignalExport.dataChannel<0000>=DATA[0]
SignalExport.dataChannel<0001>=DATA[1]
SignalExport.dataChannel<0002>=DATA[2]
SignalExport.dataChannel<0003>=DATA[3]
SignalExport.dataChannel<0004>=DATA[4]
SignalExport.dataChannel<0005>=DATA[5]
SignalExport.dataChannel<0006>=DATA[6]
SignalExport.dataChannel<0007>=DATA[7]
SignalExport.dataEqualsTrigger=false
SignalExport.dataPortWidth=8
SignalExport.triggerChannel<0000><0000>=TRIG0[0]
SignalExport.triggerChannel<0000><0001>=TRIG0[1]
SignalExport.triggerChannel<0000><0002>=TRIG0[2]
SignalExport.triggerChannel<0000><0003>=TRIG0[3]
SignalExport.triggerChannel<0000><0004>=TRIG0[4]
SignalExport.triggerChannel<0000><0005>=TRIG0[5]
SignalExport.triggerChannel<0000><0006>=TRIG0[6]
SignalExport.triggerChannel<0000><0007>=TRIG0[7]
SignalExport.triggerPort<0000>.name=TRIG0
SignalExport.triggerPortCount=1
SignalExport.triggerPortIsData<0000>=false
SignalExport.triggerPortWidth<0000>=8
SignalExport.type=ila

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