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[/] [ac97/] [trunk/] [syn/] [bin/] [comp.dc] - Rev 4
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###############################################################################
#
# Actual Synthesis Script
#
# This script does the actual synthesis
#
# Author: Rudolf Usselmann
# rudi@asics.ws
#
# Revision:
# 3/7/01 RU Initial Sript
#
#
###############################################################################
# ==============================================
# Setup Design Parameters
source ../bin/design_spec.dc
# ==============================================
# Setup Libraries
source ../bin/lib_spec.dc
# ==============================================
# Setup File IO
set junk_file /dev/null
append log_file ../log/$active_design "_cmp.log"
append pre_comp_db_file ../out/$design_name "_pre.db"
append post_comp_db_file ../out/$design_name ".db"
append post_syn_verilog_file ../out/$design_name "_ps.v"
sh rm -f $log_file
# ==============================================
# Setup Misc Variables
set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
# ==============================================
# Read Design
echo "+++++++++ Reading Design ..." >> $log_file
read_file $pre_comp_db_file >> $log_file
# ==============================================
# Operating conditions
echo "+++++++++ Setting up Operation Conditions ..." >> $log_file
current_design $design_name
set_operating_conditions WORST >> $log_file
# ==============================================
# Setup Clocks and Resets
echo "+++++++++ Setting up Clocks ..." >> $log_file
set_drive 0 [find port {*clk}]
# !!! WISHBONE Clock !!!
set clock_period 5
create_clock -period $clock_period clk
set_clock_skew -uncertainty 0.1 clk
set_clock_transition 0.5 clk
set_dont_touch_network clk
# !!! BIT Clock !!!
set clock_period 500
create_clock -period $clock_period bit_clk
set_clock_skew -uncertainty 0.1 bit_clk
set_clock_transition 0.5 bit_clk
set_dont_touch_network bit_clk
# !!! Reset !!!
set_drive 0 [find port {rst*}]
set_dont_touch_network [find port {rst*}]
# ==============================================
# Setup IOs
echo "+++++++++ Setting up IOs ..." >> $log_file
# Need to spell out external IOs
set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file
set_load 0.2 [all_outputs]
set_input_delay -max 1 -clock clk [all_inputs]
set_output_delay -max 1 -clock clk [all_outputs]
set_input_delay -max 1 -clock bit_clk sdata_in
set_output_delay -max 1 -clock bit_clk sdata_out
# ==============================================
# Setup Area Constrains
set_max_area 0.0
# ==============================================
# Force Ultra
set_ultra_optimization -f
# ==============================================
# Compile Design
echo "+++++++++ Starting Compile ..." >> $log_file
#compile -map_effort medium -area_effort medium -ungroup_all >> $log_file
compile -map_effort low -area_effort low >> $log_file
#compile -map_effort high -area_effort high -ungroup_all >> $log_file
#compile -map_effort high -area_effort high -auto_ungroup >> $log_file
# ==============================================
# Write Out the optimized design
echo "+++++++++ Saving Optimized Design ..." >> $log_file
write_file -format verilog -output $post_syn_verilog_file
write_file -hierarchy -format db -output $post_comp_db_file
# ==============================================
# Create Some Basic Reports
echo "+++++++++ Reporting Final Results ..." >> $log_file
report_timing -nworst 10 >> $log_file
report_area >> $log_file
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