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###############################################################################
#
# Design Specification
#
# Author: Rudolf Usselmann
# rudi@asics.ws
#
# Revision:
# 3/7/01 RU Initial Sript
#
#
###############################################################################
# ==============================================
# Setup Design Parameters
set design_files {ac97_fifo_ctrl ac97_dma_req ac97_cra ac97_prc ac97_soc ac97_in_fifo ac97_rf ac97_sout ac97_dma_if ac97_int ac97_rst ac97_out_fifo ac97_sin ac97_wb_if ac97_top}
set design_name ac97_top
set active_design ac97_top
# Next Statement defines all clocks and resets in the design
set special_net {rst clk bit_clk}
set hdl_src_dir ../../rtl/verilog/