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[/] [aes-128-ecb-encoder/] [trunk/] [fpga/] [aes128_ecb_2017/] [aes128_ecb.ip_user_files/] [ip/] [axi_uartlite_module/] [axi_uartlite_module_stub.v] - Rev 2
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// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 // Date : Thu Jul 23 09:49:59 2020 // Host : gigant.modulew.local running 64-bit Red Hat Enterprise Linux Server release 6.9 (Santiago) // Command : write_verilog -force -mode synth_stub -rename_top axi_uartlite_module -prefix // axi_uartlite_module_ axi_uartlite_module_stub.v // Design : axi_uartlite_module // Purpose : Stub declaration of top-level module interface // Device : xc7k325tffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* x_core_info = "axi_uartlite,Vivado 2017.4" *) module axi_uartlite_module(s_axi_aclk, s_axi_aresetn, interrupt, s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, rx, tx) /* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,interrupt,s_axi_awaddr[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,rx,tx" */; input s_axi_aclk; input s_axi_aresetn; output interrupt; input [3:0]s_axi_awaddr; input s_axi_awvalid; output s_axi_awready; input [31:0]s_axi_wdata; input [3:0]s_axi_wstrb; input s_axi_wvalid; output s_axi_wready; output [1:0]s_axi_bresp; output s_axi_bvalid; input s_axi_bready; input [3:0]s_axi_araddr; input s_axi_arvalid; output s_axi_arready; output [31:0]s_axi_rdata; output [1:0]s_axi_rresp; output s_axi_rvalid; input s_axi_rready; input rx; output tx; endmodule