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[/] [aes_decrypt_fpga/] [trunk/] [rtl/] [verilog/] [generic/] [generic_muxfx.v] - Rev 2

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// Technology independent version of MUXF7 and MUXF8.
//
// This file should not be included while targeting Xilinx so that
// the MUXF7/MUXF8 primitives in the Xilinx simulation/synthesis
// will be used instead.
module MUXF7 (output O, input I0, input I1, input S);
	assign O = (S)? I1 : I0;
endmodule
 
module MUXF8 (output O, input I0, input I1, input S);
	assign O = (S)? I1 : I0;
endmodule

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