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[/] [aes_pipe/] [trunk/] [syn/] [Xilinx/] [log/] [aes.mrp] - Rev 10
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Release 11.1 Map L.33 (lin)Xilinx Mapping Report File for Design 'aes_top'Design Information------------------Command Line : map -w -timing -ol high -cm speed -o ../out/aes.ncd../out/aes.ngdTarget Device : xc5vlx50tTarget Package : ff1136Target Speed : -1Mapper Version : virtex5 -- $Revision: 1.51 $Mapped Date : Thu Mar 25 14:16:56 2010Design Summary--------------Number of errors: 0Number of warnings: 0Slice Logic Utilization:Number of Slice Registers: 7,873 out of 28,800 27%Number used as Flip Flops: 7,873Number of Slice LUTs: 14,724 out of 28,800 51%Number used as logic: 14,724 out of 28,800 51%Number using O6 output only: 14,724Slice Logic Distribution:Number of occupied Slices: 4,656 out of 7,200 64%Number of occupied SLICEMs: 0 out of 1,920 0%Number of LUT Flip Flop pairs used: 15,770Number with an unused Flip Flop: 7,897 out of 15,770 50%Number with an unused LUT: 1,046 out of 15,770 6%Number of fully used LUT-FF pairs: 6,827 out of 15,770 43%Number of unique control sets: 1Number of slice register sites lostto control set restrictions: 3 out of 28,800 1%A LUT Flip Flop pair for this architecture represents one LUT paired withone Flip Flop within a slice. A control set is a unique combination ofclock, reset, set, and enable signals for a registered element.The Slice Logic Distribution report is not meaningful if the design isover-mapped for a non-slice resource or if Placement fails.OVERMAPPING of BRAM resources should be ignored if the design isover-mapped for a non-BRAM resource or if placement fails.IO Utilization:Number of bonded IOBs: 386 out of 480 80%Specific Feature Utilization:Number of BUFG/BUFGCTRLs: 2 out of 32 6%Number used as BUFGs: 2Average Fanout of Non-Clock Nets: 5.14Peak Memory Usage: 535 MBTotal REAL time to MAP completion: 13 mins 31 secsTotal CPU time to MAP completion: 13 minsTable of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group and Partition SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Control Set InformationSection 14 - Utilization by HierarchySection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:Map:220 - The command line option -timing is automatically supported forthis architecture. Therefore, it is not necessary to specify this option.INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slewrate limited output drivers. The delay on speed critical single ended outputscan be dramatically reduced by designating them as fast outputs.INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:0.000 to 85.000 Celsius)INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to1.050 Volts)INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report(.mrp).INFO:Pack:1650 - Map created a placed design.Section 4 - Removed Logic Summary---------------------------------1 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKVCC XST_VCCSection 6 - IOB Properties--------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Term | Strength | Rate | | | Delay |+---------------------------------------------------------------------------------------------------------------------------------------------------------+| ciphertext_o<0><0><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><0><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><0><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><0><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><0><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><0><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><0><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><0><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><1><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><1><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><1><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><1><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><1><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><1><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><1><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><1><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><2><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><2><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><2><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><2><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><2><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><2><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><2><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><2><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><3><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><3><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><3><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><3><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><3><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><3><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><3><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<0><3><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><0><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><0><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><0><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><0><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><0><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><0><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><0><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><0><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><1><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><1><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><1><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><1><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><1><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><1><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><1><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><1><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><2><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><2><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><2><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><2><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><2><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><2><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><2><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><2><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><3><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><3><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><3><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><3><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><3><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><3><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><3><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<1><3><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><0><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><0><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><0><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><0><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><0><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><0><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><0><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><0><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><1><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><1><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><1><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><1><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><1><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><1><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><1><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><1><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><2><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><2><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><2><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><2><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><2><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><2><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><2><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><2><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><3><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><3><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><3><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><3><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><3><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><3><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><3><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<2><3><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><0><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><0><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><0><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><0><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><0><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><0><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><0><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><0><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><1><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><1><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><1><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><1><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><1><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><1><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><1><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><1><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><2><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><2><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><2><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><2><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><2><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><2><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><2><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><2><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><3><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><3><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><3><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><3><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><3><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><3><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><3><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || ciphertext_o<3><3><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | || clk_i | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><0><0> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><0><1> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><0><2> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><0><3> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><0><4> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><0><5> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><0><6> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><0><7> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><1><0> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><1><1> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><1><2> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><1><3> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><1><4> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><1><5> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><1><6> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><1><7> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><2><0> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><2><1> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><2><2> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><2><3> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><2><4> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><2><5> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><2><6> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><2><7> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><3><0> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><3><1> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><3><2> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><3><3> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><3><4> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><3><5> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><3><6> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<0><3><7> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><0><0> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><0><1> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><0><2> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><0><3> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><0><4> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><0><5> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><0><6> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><0><7> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><1><0> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><1><1> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><1><2> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><1><3> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><1><4> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><1><5> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><1><6> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><1><7> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><2><0> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><2><1> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><2><2> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><2><3> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><2><4> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><2><5> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><2><6> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><2><7> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><3><0> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><3><1> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><3><2> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><3><3> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><3><4> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><3><5> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><3><6> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<1><3><7> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><0><0> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><0><1> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><0><2> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><0><3> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><0><4> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><0><5> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><0><6> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><0><7> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><1><0> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><1><1> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><1><2> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><1><3> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><1><4> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><1><5> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><1><6> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><1><7> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><2><0> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><2><1> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><2><2> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><2><3> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><2><4> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><2><5> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><2><6> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><2><7> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><3><0> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><3><1> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><3><2> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><3><3> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><3><4> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><3><5> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><3><6> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<2><3><7> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><0><0> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><0><1> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><0><2> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><0><3> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><0><4> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><0><5> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><0><6> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><0><7> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><1><0> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><1><1> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><1><2> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><1><3> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><1><4> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><1><5> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><1><6> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><1><7> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><2><0> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><2><1> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><2><2> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><2><3> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><2><4> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><2><5> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><2><6> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><2><7> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><3><0> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><3><1> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><3><2> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><3><3> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><3><4> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><3><5> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><3><6> | IOB | INPUT | LVCMOS25 | | | | | | || keyblock_i<3><3><7> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><0><0> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><0><1> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><0><2> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><0><3> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><0><4> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><0><5> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><0><6> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><0><7> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><1><0> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><1><1> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><1><2> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><1><3> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><1><4> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><1><5> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><1><6> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><1><7> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><2><0> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><2><1> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><2><2> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><2><3> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><2><4> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><2><5> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><2><6> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><2><7> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><3><0> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><3><1> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><3><2> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><3><3> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><3><4> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><3><5> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><3><6> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<0><3><7> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><0><0> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><0><1> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><0><2> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><0><3> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><0><4> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><0><5> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><0><6> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><0><7> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><1><0> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><1><1> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><1><2> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><1><3> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><1><4> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><1><5> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><1><6> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><1><7> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><2><0> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><2><1> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><2><2> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><2><3> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><2><4> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><2><5> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><2><6> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><2><7> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><3><0> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><3><1> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><3><2> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><3><3> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><3><4> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><3><5> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><3><6> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<1><3><7> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><0><0> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><0><1> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><0><2> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><0><3> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><0><4> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><0><5> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><0><6> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><0><7> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><1><0> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><1><1> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><1><2> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><1><3> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><1><4> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><1><5> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><1><6> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><1><7> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><2><0> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><2><1> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><2><2> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><2><3> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><2><4> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><2><5> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><2><6> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><2><7> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><3><0> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><3><1> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><3><2> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><3><3> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><3><4> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><3><5> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><3><6> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<2><3><7> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><0><0> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><0><1> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><0><2> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><0><3> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><0><4> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><0><5> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><0><6> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><0><7> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><1><0> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><1><1> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><1><2> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><1><3> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><1><4> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><1><5> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><1><6> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><1><7> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><2><0> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><2><1> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><2><2> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><2><3> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><2><4> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><2><5> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><2><6> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><2><7> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><3><0> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><3><1> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><3><2> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><3><3> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><3><4> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><3><5> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><3><6> | IOB | INPUT | LVCMOS25 | | | | | | || plaintext_i<3><3><7> | IOB | INPUT | LVCMOS25 | | | | | | || rst_i | IOB | INPUT | LVCMOS25 | | | | | | |+---------------------------------------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group and Partition Summary--------------------------------------------Partition Implementation Status-------------------------------No Partitions were found in this design.-------------------------------Area Group Information----------------------No area groups were found in this design.----------------------Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------A logic-level (pre-route) timing report can be generated by using Xilinx statictiming analysis tools, Timing Analyzer (GUI) or TRCE (command line), with themapped NCD and PCF files. Please note that this timing report will be generatedusing estimated delay information. For accurate numbers, please generate atiming report with the post Place and Route NCD file.For more information about the Timing Analyzer, consult the Xilinx TimingAnalyzer Reference Manual; for more information about TRCE, consult the XilinxCommand Line Tools User Guide "TRACE" chapter.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Control Set Information------------------------------------Use the "-detail" map option to print out Control Set Information.Section 14 - Utilization by Hierarchy-------------------------------------Use the "-detail" map option to print out the Utilization by Hierarchy section.