Subversion Repositories ag_6502

NET "b1" LOC = D18;
NET "b2" LOC = K17;

NET "b1" PULLDOWN;
NET "b2" PULLDOWN;

//NET "b1" CLOCK_DEDICATED_ROUTE = FALSE;
//NET "b2" CLOCK_DEDICATED_ROUTE = FALSE;
//NET "rot_a" CLOCK_DEDICATED_ROUTE = FALSE;
//NET "rot_b" CLOCK_DEDICATED_ROUTE = FALSE;
//NET "rot_center" CLOCK_DEDICATED_ROUTE = FALSE;

NET "clk" LOC = C9 | IOSTANDARD = "LVCMOS33";
//NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "ROT_A" LOC = K18 | IOSTANDARD = "LVTTL" | PULLUP;
NET "ROT_B" LOC = G18 | IOSTANDARD = "LVTTL" | PULLUP;
NET "ROT_CENTER" LOC = V16 | IOSTANDARD = "LVTTL" | PULLDOWN;

NET "LED<7>" LOC = F9 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
NET "LED<6>" LOC = E9 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
NET "LED<5>" LOC = D11 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
NET "LED<4>" LOC = C11 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
NET "LED<3>" LOC = F11 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
NET "LED<2>" LOC = E11 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
NET "LED<1>" LOC = E12 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;
NET "LED<0>" LOC = F12 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 8;

NET "VGA_RED" LOC = H14 | IOSTANDARD = "LVTTL" | DRIVE = 8 | SLEW = FAST;
NET "VGA_GREEN" LOC = H15 | IOSTANDARD = "LVTTL" | DRIVE = 8 | SLEW = FAST;
NET "VGA_BLUE" LOC = G15 | IOSTANDARD = "LVTTL" | DRIVE = 8 | SLEW = FAST;
NET "VGA_HSYNC" LOC = F15 | IOSTANDARD = "LVTTL" | DRIVE = 8 | SLEW = FAST;
NET "VGA_VSYNC" LOC = F14 | IOSTANDARD = "LVTTL" | DRIVE = 8 | SLEW = FAST;

NET "J4<0>" LOC = D7 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 6;
NET "J4<1>" LOC = C7 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 6;
NET "J4<2>" LOC = F8 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 6;
NET "J4<3>" LOC = E8 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 6;
#Created by Constraints Editor (xc3s500e-fg320-4) - 2012/01/19
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;

#NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
NET "SPI_MOSI" LOC = T4 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
NET "SPI_MISO" LOC = N10 | IOSTANDARD = "LVCMOS33";
NET "SPI_SCK" LOC = U16 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
NET "DAC_CS" LOC = N8 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
NET "DAC_CLR" LOC = P8 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;

NET "spi_amp_cs" LOC = N7 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
NET "spi_rom_cs" LOC = U3 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
NET "platformflash_oe" LOC = T3 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 2;
NET "strataflash_oe" LOC = C18 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 2;
NET "strataflash_ce" LOC = D16 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 2;
NET "strataflash_we" LOC = D17 | IOSTANDARD = "LVTTL" | SLEW = SLOW | DRIVE = 2;
NET "spi_adc_conv" LOC = P11 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;

NET "PS2_CLK" LOC = G14  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | PULLUP;
NET "PS2_DATA" LOC = G13 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | PULLUP;
NET "PS2_CLK" CLOCK_DEDICATED_ROUTE = FALSE;

NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;