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[/] [ahb_master/] [trunk/] [src/] [base/] [def_ic.txt] - Rev 14
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<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
REQUIRE(1.5)
INCLUDE def_ic_static.txt
STARTUSER
SWAP.GLOBAL #FFD #1 ##flip-flop delay
SWAP.USER PREFIX fabric_MASTER_NUM_SLAVE_NUM ##prefix for all module and file names
SWAP.USER MASTER_NUM 3 ##number of masters
SWAP.USER SLAVE_NUM 6 ##number of slaves
SWAP.USER CMD_DEPTH 4 ##AXI master command depth for read and write
SWAP.USER SLV_DEPTH 8 ##AXI slave command depth for read and write
SWAP.USER DATA_BITS 64 ##AXI data bits
SWAP.USER ADDR_BITS 32 ##AXI address bits
SWAP.USER SIZE_BITS 2 ##AXI size bits
DEFINE.USER DEF_DECERR_SLV ##use interanl decode slave error
SWAP.USER USER_BITS 4 ##AXI user bits
SWAP.USER MSTR_ID_BITS 4 ##AXI ID bits
UNDEF.USER UNIQUE_ID ##If defined all IDs must be unique, else bits will be added to slave IDs to identify masters
GROUP.USER.TRUE(MASTER_NUM>0) M0_ID is { ##Supported AXI IDs for master 0 (binary)
000
001
}
GROUP.USER.TRUE(MASTER_NUM>1) M1_ID is { ##Supported AXI IDs for master 1 (binary)
011
}
GROUP.USER.TRUE(MASTER_NUM>2) M2_ID is { ##Supported AXI IDs for master 2 (binary)
000
100
101
}
GROUP.USER.TRUE(MASTER_NUM>3) M3_ID is { ##Supported AXI IDs for master 3 (binary)
}
GROUP.USER.TRUE(MASTER_NUM>4) M4_ID is { ##Supported AXI IDs for master 4 (binary)
}
GROUP.USER.TRUE(MASTER_NUM>5) M5_ID is { ##Supported AXI IDs for master 5 (binary)
}
GROUP.USER.TRUE(MASTER_NUM>6) M6_ID is { ##Supported AXI IDs for master 6 (binary)
}
GROUP.USER.TRUE(MASTER_NUM>7) M7_ID is { ##Supported AXI IDs for master 7 (binary)
}