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[/] [ahb_slave/] [trunk/] [src/] [base/] [def_ahb_slave_static.txt] - Rev 8
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<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
SWAP.GLOBAL MODEL_NAME AHB slave stub
VERIFY ((DATA_BITS == 64) || (DATA_BITS == 32)) else stub supports 32 or 64 bits data bus
VERIFY (ADDR_BITS<=24) else Memory size should not be too big to prevent maloc fail
GROUP STUB_AHB is {
HADDR ADDR_BITS output
HBURST 3 output
HSIZE 2 output
HTRANS 2 output
HWRITE 1 output
HWDATA DATA_BITS output
HRDATA DATA_BITS input
HREADY 1 input
HRESP 1 input
}
GROUP STUB_MEM is {
WR 1 output
RD 1 output
ADDR_WR ADDR_BITS output
ADDR_RD ADDR_BITS output
DIN DATA_BITS output
BSEL DATA_BITS/8 output
DOUT DATA_BITS input
}
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