Subversion Repositories ahbmaster

<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>CoreAHBLite</name><vendor>Actel</vendor><library>DirectCore</library><version>5.3.101</version><fileSets><fileSet fileSetId="STIMULUS_FILESET"><file fileid="0"><name>rtl\vhdl\amba_bfm\misc.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="1"><name>rtl\vhdl\amba_bfm\textio.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="2"><name>rtl\vhdl\amba_bfm\bfm_package.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="3"><name>rtl\vhdl\amba_bfm\bfm_main.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="4"><name>rtl\vhdl\amba_bfm\bfm_ahbl.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="5"><name>rtl\vhdl\amba_bfm\bfm_ahbslaveext.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="6"><name>rtl\vhdl\amba_bfm\bfm_ahbslave.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="7"><name>mti\scripts\wave_user.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file><file fileid="8"><name>mti\scripts\bfmtovec_compile.tcl</name><userFileType>tclSource</userFileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file><file fileid="9"><name>mti\scripts\bfmtovec.exe</name><userFileType>unknown</userFileType></file><file fileid="10"><name>mti\scripts\bfmtovec.lin</name><userFileType>unknown</userFileType></file><file fileid="11"><name>mti\scripts\coreahblite_usertb_include.bfm</name><userFileType>BFM</userFileType></file><file fileid="12"><name>mti\scripts\coreahblite_usertb_ahb_master0.bfm</name><userFileType>BFM</userFileType></file><file fileid="13"><name>mti\scripts\coreahblite_usertb_ahb_master0.vec</name><userFileType>unknown</userFileType></file><file fileid="14"><name>mti\scripts\coreahblite_usertb_ahb_master1.bfm</name><userFileType>BFM</userFileType></file><file fileid="15"><name>mti\scripts\coreahblite_usertb_ahb_master1.vec</name><userFileType>unknown</userFileType></file><file fileid="16"><name>mti\scripts\coreahblite_usertb_ahb_master2.bfm</name><userFileType>BFM</userFileType></file><file fileid="17"><name>mti\scripts\coreahblite_usertb_ahb_master2.vec</name><userFileType>unknown</userFileType></file><file fileid="18"><name>mti\scripts\coreahblite_usertb_ahb_master3.bfm</name><userFileType>BFM</userFileType></file><file fileid="19"><name>mti\scripts\coreahblite_usertb_ahb_master3.vec</name><userFileType>unknown</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="20"><name>rtl\vhdl\core\coreahblite_addrdec.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="21"><name>rtl\vhdl\core\coreahblite_defaultslavesm.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="22"><name>rtl\vhdl\core\coreahblite_slavearbiter.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="23"><name>rtl\vhdl\core\coreahblite_masterstage.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="24"><name>rtl\vhdl\core\coreahblite_slavestage.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="25"><name>rtl\vhdl\core\coreahblite_matrix4x16.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file><file fileid="26"><name>rtl\vhdl\core\coreahblite_pkg.vhd</name><logicalName>COREAHBLITE_LIB</logicalName><fileType>VHDLSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><vendorExtensions><libraries><library><name>COREAHBLITE_LIB</name><path>mti/user_vhdl/COREAHBLITE_LIB</path></library></libraries></vendorExtensions></Component>