Subversion Repositories ahbmaster

library IEEe;
use IEEE.std_lOGIC_1164.all;
entity COREAPB is
generic (APBSLOT0Enable: inTEGER := 1;
APBSLOT1Enable: integer := 1;
ApbSlot2EnaBLE: intEGER := 1;
ApbSlOT3ENABLe: INTEGer := 1;
APBSLOT4Enable: INteger := 1;
APBSLOT5Enable: Integer := 1;
ApbSlot6ENABLE: INTEGER := 1;
APBSLOt7Enable: Integer := 1;
ApbSlot8EnABLE: inTEGER := 1;
ApbSlot9ENABLE: intEGER := 1;
ApbSLOT10Enable: INTeger := 1;
APbSlot11EnabLE: inteGER := 1;
ApbSLOT12ENable: Integer := 1;
APBSlot13Enable: integer := 1;
ApbSlot14ENABLE: INTEGER := 1;
ApbSlot15EnABLE: inTEGER := 1); port (PADDR: in STD_Logic_vector(23 downto 0);
PWRITE: in std_logic;
PENABLE: in std_logIC;
PWDATA: in STD_LOgic_vector(31 downto 0);
PRDATA: out STD_logic_vectOR(31 downto 0);
PSELECT: in STD_logic_vectOR(15 downto 0);
PADDRS: out stD_LOGIC_vector(23 downto 0);
PWRITES: out STD_logic;
PENABLES: out STD_Logic;
PWDATAS: out std_LOGIC_VEctor(31 downto 0);
PSELS0: out std_logic;
PSELS1: out std_logic;
PSELS2: out STD_LOGic;
PSELS3: out STD_logic;
PSELS4: out STD_Logic;
PSELS5: out std_lOGIC;
PSELS6: out STD_LOgic;
PSELS7: out Std_logic;
PSELS8: out std_logic;
PSELS9: out STD_logic;
PSELS10: out std_logic;
PSELS11: out std_LOGIC;
PSELS12: out std_logiC;
PSELS13: out STD_LOGIc;
PSELS14: out std_loGIC;
PSELS15: out stD_LOGIC;
PRDATAS0: in std_lOGIC_VECtor(31 downto 0);
PRDATAS1: in std_logic_veCTOR(31 downto 0);
PRDATAS2: in sTD_LOGIC_vector(31 downto 0);
PRDATAS3: in STD_LOGic_vector(31 downto 0);
PRDATAS4: in STD_LOGIc_vector(31 downto 0);
PRDATAS5: in STD_LOGIc_vector(31 downto 0);
PRDATAS6: in STD_Logic_vectoR(31 downto 0);
PRDATAS7: in STD_LOgic_vector(31 downto 0);
PRDATAS8: in std_logIC_VECTor(31 downto 0);
PRDATAS9: in std_logic_VECTOR(31 downto 0);
PRDATAS10: in std_logIC_VECTOr(31 downto 0);
PRDATAS11: in Std_logic_vECTOR(31 downto 0);
PRDATAS12: in STD_logic_vectOR(31 downto 0);
PRDATAS13: in STD_LOGic_vector(31 downto 0);
PRDATAS14: in sTD_LOGIC_vector(31 downto 0);
PRDATAS15: in STD_logic_vectoR(31 downto 0));
end CoreAPB;
 
architecture CoreAPB_O of CoreAPB is
 
component CoreAPB_L
port (PSELS0: in STD_logic;
PSELS1: in STD_LOGIc;
PSELS2: in std_logic;
PSELS3: in STD_logic;
PSELS4: in STD_logic;
PSELS5: in stD_LOGIC;
PSELS6: in std_logIC;
PSELS7: in std_logic;
PSELS8: in std_logic;
PSELS9: in Std_logic;
PSELS10: in STD_logic;
PSELS11: in std_logic;
PSELS12: in std_logIC;
PSELS13: in std_logiC;
PSELS14: in STD_logic;
PSELS15: in STD_LOGic;
PRDATAS0: in std_LOGIC_vector(31 downto 0);
PRDATAS1: in std_logic_vECTOR(31 downto 0);
PRDATAS2: in STD_LOGic_vector(31 downto 0);
PRDATAS3: in std_logic_VECTOR(31 downto 0);
PRDATAS4: in std_loGIC_VECTor(31 downto 0);
PRDATAS5: in STD_logic_vectOR(31 downto 0);
PRDATAS6: in STD_logic_vectOR(31 downto 0);
PRDATAS7: in stD_LOGIC_vector(31 downto 0);
PRDATAS8: in STD_logic_vectOR(31 downto 0);
PRDATAS9: in stD_LOGIC_vector(31 downto 0);
PRDATAS10: in std_logic_VECTOR(31 downto 0);
PRDATAS11: in STD_logic_vectOR(31 downto 0);
PRDATAS12: in Std_logic_veCTOR(31 downto 0);
PRDATAS13: in STd_logic_veCTOR(31 downto 0);
PRDATAS14: in std_logic_VECTOR(31 downto 0);
PRDATAS15: in STD_LOGic_vector(31 downto 0);
PRDATA: out STD_logic_vectOR(31 downto 0));
end component;
 
signal COREAPB_i: sTD_LOGic_vector(31 downto 0);
 
signal COREAPB_ol: stD_LOGIC_vector(31 downto 0);
 
signal COREAPB_ll: sTD_LOGIC_vector(31 downto 0);
 
signal CoreAPB_il: STD_LOgic_vector(31 downto 0);
 
signal COREAPB_oi: std_LOGIC_VEctor(31 downto 0);
 
signal CoreAPB_LI: std_logic_vECTOR(31 downto 0);
 
signal COREAPB_ii: sTD_LOGIC_vector(31 downto 0);
 
signal COREAPB_o0: std_lOGIC_VEctor(31 downto 0);
 
signal COREAPB_l0: sTD_LOGIC_vector(31 downto 0);
 
signal CoreAPB_i0: STD_Logic_vector(31 downto 0);
 
signal CoREAPB_O1: stD_LOGIC_vector(31 downto 0);
 
signal CoreAPB_l1: STD_logic_vectOR(31 downto 0);
 
signal COREAPB_i1: std_logIC_VECTOr(31 downto 0);
 
signal CoREAPB_OOl: std_logIC_VECTOr(31 downto 0);
 
signal CoreAPB_lol: STD_logic_vecTOR(31 downto 0);
 
signal CoreAPB_ioL: STD_logic_vectOR(31 downto 0);
 
signal CoREAPB_Oll: std_LOGIC_VEctor(31 downto 0);
 
begin
CoreAPB_olL <= ( others => '0');
PADDRS <= PADDR;
PWRITES <= PWRITE;
PENABLES <= PENABLE;
PWDATAS <= PWDATA;
PSELS0 <= PSELECT(0);
PSELS1 <= PSELECT(1);
PSELS2 <= PSELECT(2);
PSELS3 <= PSELECT(3);
PSELS4 <= PSELECT(4);
PSELS5 <= PSELECT(5);
PSELS6 <= PSELECT(6);
PSELS7 <= PSELECT(7);
PSELS8 <= PSELECT(8);
PSELS9 <= PSELECT(9);
PSELS10 <= PSELECT(10);
PSELS11 <= PSELECT(11);
PSELS12 <= PSELECT(12);
PSELS13 <= PSELECT(13);
PSELS14 <= PSELECT(14);
PSELS15 <= PSELECT(15);
CoreAPB_LLL:
if (APBSlot0Enable = 1)
generate
begin
CoreAPB_I <= PRDATAS0;
end generate CoreAPB_llL;
CoreAPB_ilL:
if (APbSlot0EnablE = 0)
generate
begin
COREAPB_i <= COREAPB_oll;
end generate COREAPB_ill;
COReAPB_oil:
if (ApbSlot1EnaBLE = 1)
generate
begin
CoreAPB_ol <= PRDATAS1;
end generate CoreAPB_OIL;
CoreAPB_LIL:
if (APbSlot1EnablE = 0)
generate
begin
COREAPB_ol <= COREAPB_oll;
end generate COReAPB_lil;
COREAPB_iil:
if (ApbSlot2EnabLE = 1)
generate
begin
CoreAPB_ll <= PRDATAS2;
end generate COREAPB_iil;
COREAPB_o0l:
if (APBSLOT2Enable = 0)
generate
begin
COREAPB_ll <= CoreAPB_OLL;
end generate COREAPB_o0l;
COREAPB_l0l:
if (APBSlot3Enable = 1)
generate
begin
COReAPB_il <= PRDATAS3;
end generate COREAPB_l0l;
COREAPB_i0l:
if (ApBSLOT3Enable = 0)
generate
begin
CoreAPB_IL <= CoREAPB_Oll;
end generate COREAPB_i0l;
CoreAPB_O1L:
if (ApbSlot4EnaBLE = 1)
generate
begin
CoreAPB_oi <= PRDATAS4;
end generate CoreAPB_O1L;
CoreAPB_l1L:
if (ApbSlot4EnABLE = 0)
generate
begin
COReAPB_oi <= COreAPB_oll;
end generate CoreAPB_l1L;
COREAPB_i1l:
if (ApbSlot5EnaBLE = 1)
generate
begin
CoreAPB_li <= PRDATAS5;
end generate CoreAPB_i1L;
CoreAPB_ooi:
if (APBSLOT5Enable = 0)
generate
begin
CoreAPB_LI <= CoreAPB_OLL;
end generate CoreAPB_OOI;
CoreAPB_loi:
if (ApbSlot6ENABLE = 1)
generate
begin
CoreAPB_II <= PRDATAS6;
end generate CoreAPB_lOI;
CoreAPB_IOI:
if (APBSlot6Enable = 0)
generate
begin
CoreAPB_II <= CoreAPB_oLL;
end generate CoreAPB_IOI;
COREAPB_oli:
if (APbSlot7EnablE = 1)
generate
begin
COREAPB_O0 <= PRDATAS7;
end generate CoreAPB_OLI;
CoreAPB_LLI:
if (APBSLOT7Enable = 0)
generate
begin
COREAPB_o0 <= COReAPB_oll;
end generate CoreAPB_lli;
CoreAPB_ili:
if (ApbSlot8EnABLE = 1)
generate
begin
COREAPB_l0 <= PRDATAS8;
end generate COREAPB_ili;
COREAPB_oii:
if (ApbSloT8ENABLe = 0)
generate
begin
CoreAPB_l0 <= CoreAPB_oll;
end generate CoreAPB_OII;
COREAPB_lii:
if (ApbSlot9EnaBLE = 1)
generate
begin
COreAPB_i0 <= PRDATAS9;
end generate CoreAPB_liI;
CoreAPB_III:
if (APBSlot9Enable = 0)
generate
begin
CoreAPB_I0 <= CoreAPB_olL;
end generate CoreAPB_III;
CoreAPB_o0i:
if (APBSLOT10Enable = 1)
generate
begin
CorEAPB_O1 <= PRDATAS10;
end generate COReAPB_o0i;
CoreAPB_l0i:
if (APBSLOT10Enable = 0)
generate
begin
COREAPB_o1 <= COREAPB_oll;
end generate COREAPB_l0i;
CoreAPB_i0I:
if (ApbSlot11EnABLE = 1)
generate
begin
CoreAPB_l1 <= PRDATAS11;
end generate COREAPB_i0i;
COReAPB_o1i:
if (ApbSlot11ENABLE = 0)
generate
begin
COREAPB_l1 <= COREAPB_oll;
end generate COReAPB_o1i;
COREAPB_l1i:
if (ApbSlot12ENABLE = 1)
generate
begin
CoREAPB_I1 <= PRDATAS12;
end generate CoreAPB_l1I;
COREAPB_i1i:
if (APBSLOT12Enable = 0)
generate
begin
CoreAPB_I1 <= CoreAPB_olL;
end generate CoreAPB_i1I;
COReAPB_oo0:
if (APBSLOT13Enable = 1)
generate
begin
COREAPB_ool <= PRDATAS13;
end generate CoreAPB_oo0;
CoreAPB_LO0:
if (ApbSlot13ENABLE = 0)
generate
begin
CoreAPB_ool <= COREAPB_oll;
end generate CoreAPB_lo0;
COREAPB_io0:
if (APBSLOT14Enable = 1)
generate
begin
CoreAPB_LOL <= PRDATAS14;
end generate CorEAPB_IO0;
CoREAPB_Ol0:
if (ApbSlot14ENABLE = 0)
generate
begin
CoreAPB_lol <= COreAPB_oll;
end generate COreAPB_ol0;
COReAPB_ll0:
if (ApbSloT15ENABle = 1)
generate
begin
COREAPB_iol <= PRDATAS15;
end generate CoreAPB_ll0;
CoreAPB_il0:
if (ApbSlot15ENABLE = 0)
generate
begin
COREAPB_iol <= CoreAPB_OLL;
end generate CoreAPB_IL0;
COREAPB_oi0: COREAPB_l
port map (PSELS0 => PSELECT(0),
PSELS1 => PSELECT(1),
PSELS2 => PSELECT(2),
PSELS3 => PSELECT(3),
PSELS4 => PSELECT(4),
PSELS5 => PSELECT(5),
PSELS6 => PSELECT(6),
PSELS7 => PSELECT(7),
PSELS8 => PSELECT(8),
PSELS9 => PSELECT(9),
PSELS10 => PSELECT(10),
PSELS11 => PSELECT(11),
PSELS12 => PSELECT(12),
PSELS13 => PSELECT(13),
PSELS14 => PSELECT(14),
PSELS15 => PSELECT(15),
PRDATAS0 => COREAPB_i,
PRDATAS1 => COREAPB_ol,
PRDATAS2 => CoreAPB_ll,
PRDATAS3 => CoreAPB_iL,
PRDATAS4 => COREAPB_oi,
PRDATAS5 => CoreAPB_LI,
PRDATAS6 => COReAPB_ii,
PRDATAS7 => CoreAPB_O0,
PRDATAS8 => CoreAPB_l0,
PRDATAS9 => COREAPB_i0,
PRDATAS10 => COREAPB_O1,
PRDATAS11 => CoreAPB_L1,
PRDATAS12 => COREAPB_i1,
PRDATAS13 => CorEAPB_OOl,
PRDATAS14 => COReAPB_lol,
PRDATAS15 => CoreAPB_ioL,
PRDATA => PRDATA);
end COreAPB_o;