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Subversion Repositories ahbmaster
[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [component/] [work/] [top/] [top.vhd] - Rev 3
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---------------------------------------------------------------------- -- Created by SmartDesign Sat Jun 02 22:52:57 2018 -- Version: v11.8 SP3 11.8.3.6 ---------------------------------------------------------------------- ---------------------------------------------------------------------- -- Libraries ---------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; library COREAHBLITE_LIB; use COREAHBLITE_LIB.all; use COREAHBLITE_LIB.top_CoreAHBLite_0_components.all; library COREUARTAPB_LIB; use COREUARTAPB_LIB.all; use COREUARTAPB_LIB.top_CoreUARTapb_0_components.all; ---------------------------------------------------------------------- -- top entity declaration ---------------------------------------------------------------------- entity top is -- Port list port( -- Inputs ADDR : in std_logic_vector(31 downto 0); DATAIN : in std_logic_vector(31 downto 0); HCLK : in std_logic; HRESETn : in std_logic; LREAD : in std_logic; LWRITE : in std_logic; -- Outputs DATAOUT : out std_logic_vector(31 downto 0); RESP_err : out std_logic_vector(1 downto 0); TX : out std_logic; ahb_busy : out std_logic ); end top; ---------------------------------------------------------------------- -- top architecture body ---------------------------------------------------------------------- architecture RTL of top is ---------------------------------------------------------------------- -- Component declarations ---------------------------------------------------------------------- -- AHBMASTER_FIC -- using entity instantiation for component AHBMASTER_FIC -- CoreAHB2APB - Actel:DirectCore:CoreAHB2APB:1.1.101 component CoreAHB2APB -- Port list port( -- Inputs HADDR : in std_logic_vector(27 downto 0); HCLK : in std_logic; HREADY : in std_logic; HRESETn : in std_logic; HSEL : in std_logic; HTRANS : in std_logic_vector(1 downto 0); HWDATA : in std_logic_vector(31 downto 0); HWRITE : in std_logic; PRDATA : in std_logic_vector(31 downto 0); -- Outputs HRDATA : out std_logic_vector(31 downto 0); HREADYOUT : out std_logic; HRESP : out std_logic_vector(1 downto 0); PADDR : out std_logic_vector(23 downto 0); PENABLE : out std_logic; PSELECT : out std_logic_vector(15 downto 0); PWDATA : out std_logic_vector(31 downto 0); PWRITE : out std_logic ); end component; -- top_CoreAHBLite_0_CoreAHBLite - Actel:DirectCore:CoreAHBLite:5.3.101 component top_CoreAHBLite_0_CoreAHBLite generic( FAMILY : integer := 15 ; HADDR_SHG_CFG : integer := 1 ; M0_AHBSLOT0ENABLE : integer := 1 ; M0_AHBSLOT1ENABLE : integer := 0 ; M0_AHBSLOT2ENABLE : integer := 0 ; M0_AHBSLOT3ENABLE : integer := 0 ; M0_AHBSLOT4ENABLE : integer := 0 ; M0_AHBSLOT5ENABLE : integer := 0 ; M0_AHBSLOT6ENABLE : integer := 0 ; M0_AHBSLOT7ENABLE : integer := 0 ; M0_AHBSLOT8ENABLE : integer := 0 ; M0_AHBSLOT9ENABLE : integer := 0 ; M0_AHBSLOT10ENABLE : integer := 0 ; M0_AHBSLOT11ENABLE : integer := 0 ; M0_AHBSLOT12ENABLE : integer := 0 ; M0_AHBSLOT13ENABLE : integer := 0 ; M0_AHBSLOT14ENABLE : integer := 0 ; M0_AHBSLOT15ENABLE : integer := 0 ; M0_AHBSLOT16ENABLE : integer := 0 ; M1_AHBSLOT0ENABLE : integer := 0 ; M1_AHBSLOT1ENABLE : integer := 0 ; M1_AHBSLOT2ENABLE : integer := 0 ; M1_AHBSLOT3ENABLE : integer := 0 ; M1_AHBSLOT4ENABLE : integer := 0 ; M1_AHBSLOT5ENABLE : integer := 0 ; M1_AHBSLOT6ENABLE : integer := 0 ; M1_AHBSLOT7ENABLE : integer := 0 ; M1_AHBSLOT8ENABLE : integer := 0 ; M1_AHBSLOT9ENABLE : integer := 0 ; M1_AHBSLOT10ENABLE : integer := 0 ; M1_AHBSLOT11ENABLE : integer := 0 ; M1_AHBSLOT12ENABLE : integer := 0 ; M1_AHBSLOT13ENABLE : integer := 0 ; M1_AHBSLOT14ENABLE : integer := 0 ; M1_AHBSLOT15ENABLE : integer := 0 ; M1_AHBSLOT16ENABLE : integer := 0 ; M2_AHBSLOT0ENABLE : integer := 0 ; M2_AHBSLOT1ENABLE : integer := 0 ; M2_AHBSLOT2ENABLE : integer := 0 ; M2_AHBSLOT3ENABLE : integer := 0 ; M2_AHBSLOT4ENABLE : integer := 0 ; M2_AHBSLOT5ENABLE : integer := 0 ; M2_AHBSLOT6ENABLE : integer := 0 ; M2_AHBSLOT7ENABLE : integer := 0 ; M2_AHBSLOT8ENABLE : integer := 0 ; M2_AHBSLOT9ENABLE : integer := 0 ; M2_AHBSLOT10ENABLE : integer := 0 ; M2_AHBSLOT11ENABLE : integer := 0 ; M2_AHBSLOT12ENABLE : integer := 0 ; M2_AHBSLOT13ENABLE : integer := 0 ; M2_AHBSLOT14ENABLE : integer := 0 ; M2_AHBSLOT15ENABLE : integer := 0 ; M2_AHBSLOT16ENABLE : integer := 0 ; M3_AHBSLOT0ENABLE : integer := 0 ; M3_AHBSLOT1ENABLE : integer := 0 ; M3_AHBSLOT2ENABLE : integer := 0 ; M3_AHBSLOT3ENABLE : integer := 0 ; M3_AHBSLOT4ENABLE : integer := 0 ; M3_AHBSLOT5ENABLE : integer := 0 ; M3_AHBSLOT6ENABLE : integer := 0 ; M3_AHBSLOT7ENABLE : integer := 0 ; M3_AHBSLOT8ENABLE : integer := 0 ; M3_AHBSLOT9ENABLE : integer := 0 ; M3_AHBSLOT10ENABLE : integer := 0 ; M3_AHBSLOT11ENABLE : integer := 0 ; M3_AHBSLOT12ENABLE : integer := 0 ; M3_AHBSLOT13ENABLE : integer := 0 ; M3_AHBSLOT14ENABLE : integer := 0 ; M3_AHBSLOT15ENABLE : integer := 0 ; M3_AHBSLOT16ENABLE : integer := 0 ; MEMSPACE : integer := 1 ; SC_0 : integer := 0 ; SC_1 : integer := 0 ; SC_2 : integer := 0 ; SC_3 : integer := 0 ; SC_4 : integer := 0 ; SC_5 : integer := 0 ; SC_6 : integer := 0 ; SC_7 : integer := 0 ; SC_8 : integer := 0 ; SC_9 : integer := 0 ; SC_10 : integer := 0 ; SC_11 : integer := 0 ; SC_12 : integer := 0 ; SC_13 : integer := 0 ; SC_14 : integer := 0 ; SC_15 : integer := 0 ); -- Port list port( -- Inputs HADDR_M0 : in std_logic_vector(31 downto 0); HADDR_M1 : in std_logic_vector(31 downto 0); HADDR_M2 : in std_logic_vector(31 downto 0); HADDR_M3 : in std_logic_vector(31 downto 0); HBURST_M0 : in std_logic_vector(2 downto 0); HBURST_M1 : in std_logic_vector(2 downto 0); HBURST_M2 : in std_logic_vector(2 downto 0); HBURST_M3 : in std_logic_vector(2 downto 0); HCLK : in std_logic; HMASTLOCK_M0 : in std_logic; HMASTLOCK_M1 : in std_logic; HMASTLOCK_M2 : in std_logic; HMASTLOCK_M3 : in std_logic; HPROT_M0 : in std_logic_vector(3 downto 0); HPROT_M1 : in std_logic_vector(3 downto 0); HPROT_M2 : in std_logic_vector(3 downto 0); HPROT_M3 : in std_logic_vector(3 downto 0); HRDATA_S0 : in std_logic_vector(31 downto 0); HRDATA_S1 : in std_logic_vector(31 downto 0); HRDATA_S10 : in std_logic_vector(31 downto 0); HRDATA_S11 : in std_logic_vector(31 downto 0); HRDATA_S12 : in std_logic_vector(31 downto 0); HRDATA_S13 : in std_logic_vector(31 downto 0); HRDATA_S14 : in std_logic_vector(31 downto 0); HRDATA_S15 : in std_logic_vector(31 downto 0); HRDATA_S16 : in std_logic_vector(31 downto 0); HRDATA_S2 : in std_logic_vector(31 downto 0); HRDATA_S3 : in std_logic_vector(31 downto 0); HRDATA_S4 : in std_logic_vector(31 downto 0); HRDATA_S5 : in std_logic_vector(31 downto 0); HRDATA_S6 : in std_logic_vector(31 downto 0); HRDATA_S7 : in std_logic_vector(31 downto 0); HRDATA_S8 : in std_logic_vector(31 downto 0); HRDATA_S9 : in std_logic_vector(31 downto 0); HREADYOUT_S0 : in std_logic; HREADYOUT_S1 : in std_logic; HREADYOUT_S10 : in std_logic; HREADYOUT_S11 : in std_logic; HREADYOUT_S12 : in std_logic; HREADYOUT_S13 : in std_logic; HREADYOUT_S14 : in std_logic; HREADYOUT_S15 : in std_logic; HREADYOUT_S16 : in std_logic; HREADYOUT_S2 : in std_logic; HREADYOUT_S3 : in std_logic; HREADYOUT_S4 : in std_logic; HREADYOUT_S5 : in std_logic; HREADYOUT_S6 : in std_logic; HREADYOUT_S7 : in std_logic; HREADYOUT_S8 : in std_logic; HREADYOUT_S9 : in std_logic; HRESETN : in std_logic; HRESP_S0 : in std_logic_vector(1 downto 0); HRESP_S1 : in std_logic_vector(1 downto 0); HRESP_S10 : in std_logic_vector(1 downto 0); HRESP_S11 : in std_logic_vector(1 downto 0); HRESP_S12 : in std_logic_vector(1 downto 0); HRESP_S13 : in std_logic_vector(1 downto 0); HRESP_S14 : in std_logic_vector(1 downto 0); HRESP_S15 : in std_logic_vector(1 downto 0); HRESP_S16 : in std_logic_vector(1 downto 0); HRESP_S2 : in std_logic_vector(1 downto 0); HRESP_S3 : in std_logic_vector(1 downto 0); HRESP_S4 : in std_logic_vector(1 downto 0); HRESP_S5 : in std_logic_vector(1 downto 0); HRESP_S6 : in std_logic_vector(1 downto 0); HRESP_S7 : in std_logic_vector(1 downto 0); HRESP_S8 : in std_logic_vector(1 downto 0); HRESP_S9 : in std_logic_vector(1 downto 0); HSIZE_M0 : in std_logic_vector(2 downto 0); HSIZE_M1 : in std_logic_vector(2 downto 0); HSIZE_M2 : in std_logic_vector(2 downto 0); HSIZE_M3 : in std_logic_vector(2 downto 0); HTRANS_M0 : in std_logic_vector(1 downto 0); HTRANS_M1 : in std_logic_vector(1 downto 0); HTRANS_M2 : in std_logic_vector(1 downto 0); HTRANS_M3 : in std_logic_vector(1 downto 0); HWDATA_M0 : in std_logic_vector(31 downto 0); HWDATA_M1 : in std_logic_vector(31 downto 0); HWDATA_M2 : in std_logic_vector(31 downto 0); HWDATA_M3 : in std_logic_vector(31 downto 0); HWRITE_M0 : in std_logic; HWRITE_M1 : in std_logic; HWRITE_M2 : in std_logic; HWRITE_M3 : in std_logic; REMAP_M0 : in std_logic; -- Outputs HADDR_S0 : out std_logic_vector(31 downto 0); HADDR_S1 : out std_logic_vector(31 downto 0); HADDR_S10 : out std_logic_vector(31 downto 0); HADDR_S11 : out std_logic_vector(31 downto 0); HADDR_S12 : out std_logic_vector(31 downto 0); HADDR_S13 : out std_logic_vector(31 downto 0); HADDR_S14 : out std_logic_vector(31 downto 0); HADDR_S15 : out std_logic_vector(31 downto 0); HADDR_S16 : out std_logic_vector(31 downto 0); HADDR_S2 : out std_logic_vector(31 downto 0); HADDR_S3 : out std_logic_vector(31 downto 0); HADDR_S4 : out std_logic_vector(31 downto 0); HADDR_S5 : out std_logic_vector(31 downto 0); HADDR_S6 : out std_logic_vector(31 downto 0); HADDR_S7 : out std_logic_vector(31 downto 0); HADDR_S8 : out std_logic_vector(31 downto 0); HADDR_S9 : out std_logic_vector(31 downto 0); HBURST_S0 : out std_logic_vector(2 downto 0); HBURST_S1 : out std_logic_vector(2 downto 0); HBURST_S10 : out std_logic_vector(2 downto 0); HBURST_S11 : out std_logic_vector(2 downto 0); HBURST_S12 : out std_logic_vector(2 downto 0); HBURST_S13 : out std_logic_vector(2 downto 0); HBURST_S14 : out std_logic_vector(2 downto 0); HBURST_S15 : out std_logic_vector(2 downto 0); HBURST_S16 : out std_logic_vector(2 downto 0); HBURST_S2 : out std_logic_vector(2 downto 0); HBURST_S3 : out std_logic_vector(2 downto 0); HBURST_S4 : out std_logic_vector(2 downto 0); HBURST_S5 : out std_logic_vector(2 downto 0); HBURST_S6 : out std_logic_vector(2 downto 0); HBURST_S7 : out std_logic_vector(2 downto 0); HBURST_S8 : out std_logic_vector(2 downto 0); HBURST_S9 : out std_logic_vector(2 downto 0); HMASTLOCK_S0 : out std_logic; HMASTLOCK_S1 : out std_logic; HMASTLOCK_S10 : out std_logic; HMASTLOCK_S11 : out std_logic; HMASTLOCK_S12 : out std_logic; HMASTLOCK_S13 : out std_logic; HMASTLOCK_S14 : out std_logic; HMASTLOCK_S15 : out std_logic; HMASTLOCK_S16 : out std_logic; HMASTLOCK_S2 : out std_logic; HMASTLOCK_S3 : out std_logic; HMASTLOCK_S4 : out std_logic; HMASTLOCK_S5 : out std_logic; HMASTLOCK_S6 : out std_logic; HMASTLOCK_S7 : out std_logic; HMASTLOCK_S8 : out std_logic; HMASTLOCK_S9 : out std_logic; HPROT_S0 : out std_logic_vector(3 downto 0); HPROT_S1 : out std_logic_vector(3 downto 0); HPROT_S10 : out std_logic_vector(3 downto 0); HPROT_S11 : out std_logic_vector(3 downto 0); HPROT_S12 : out std_logic_vector(3 downto 0); HPROT_S13 : out std_logic_vector(3 downto 0); HPROT_S14 : out std_logic_vector(3 downto 0); HPROT_S15 : out std_logic_vector(3 downto 0); HPROT_S16 : out std_logic_vector(3 downto 0); HPROT_S2 : out std_logic_vector(3 downto 0); HPROT_S3 : out std_logic_vector(3 downto 0); HPROT_S4 : out std_logic_vector(3 downto 0); HPROT_S5 : out std_logic_vector(3 downto 0); HPROT_S6 : out std_logic_vector(3 downto 0); HPROT_S7 : out std_logic_vector(3 downto 0); HPROT_S8 : out std_logic_vector(3 downto 0); HPROT_S9 : out std_logic_vector(3 downto 0); HRDATA_M0 : out std_logic_vector(31 downto 0); HRDATA_M1 : out std_logic_vector(31 downto 0); HRDATA_M2 : out std_logic_vector(31 downto 0); HRDATA_M3 : out std_logic_vector(31 downto 0); HREADY_M0 : out std_logic; HREADY_M1 : out std_logic; HREADY_M2 : out std_logic; HREADY_M3 : out std_logic; HREADY_S0 : out std_logic; HREADY_S1 : out std_logic; HREADY_S10 : out std_logic; HREADY_S11 : out std_logic; HREADY_S12 : out std_logic; HREADY_S13 : out std_logic; HREADY_S14 : out std_logic; HREADY_S15 : out std_logic; HREADY_S16 : out std_logic; HREADY_S2 : out std_logic; HREADY_S3 : out std_logic; HREADY_S4 : out std_logic; HREADY_S5 : out std_logic; HREADY_S6 : out std_logic; HREADY_S7 : out std_logic; HREADY_S8 : out std_logic; HREADY_S9 : out std_logic; HRESP_M0 : out std_logic_vector(1 downto 0); HRESP_M1 : out std_logic_vector(1 downto 0); HRESP_M2 : out std_logic_vector(1 downto 0); HRESP_M3 : out std_logic_vector(1 downto 0); HSEL_S0 : out std_logic; HSEL_S1 : out std_logic; HSEL_S10 : out std_logic; HSEL_S11 : out std_logic; HSEL_S12 : out std_logic; HSEL_S13 : out std_logic; HSEL_S14 : out std_logic; HSEL_S15 : out std_logic; HSEL_S16 : out std_logic; HSEL_S2 : out std_logic; HSEL_S3 : out std_logic; HSEL_S4 : out std_logic; HSEL_S5 : out std_logic; HSEL_S6 : out std_logic; HSEL_S7 : out std_logic; HSEL_S8 : out std_logic; HSEL_S9 : out std_logic; HSIZE_S0 : out std_logic_vector(2 downto 0); HSIZE_S1 : out std_logic_vector(2 downto 0); HSIZE_S10 : out std_logic_vector(2 downto 0); HSIZE_S11 : out std_logic_vector(2 downto 0); HSIZE_S12 : out std_logic_vector(2 downto 0); HSIZE_S13 : out std_logic_vector(2 downto 0); HSIZE_S14 : out std_logic_vector(2 downto 0); HSIZE_S15 : out std_logic_vector(2 downto 0); HSIZE_S16 : out std_logic_vector(2 downto 0); HSIZE_S2 : out std_logic_vector(2 downto 0); HSIZE_S3 : out std_logic_vector(2 downto 0); HSIZE_S4 : out std_logic_vector(2 downto 0); HSIZE_S5 : out std_logic_vector(2 downto 0); HSIZE_S6 : out std_logic_vector(2 downto 0); HSIZE_S7 : out std_logic_vector(2 downto 0); HSIZE_S8 : out std_logic_vector(2 downto 0); HSIZE_S9 : out std_logic_vector(2 downto 0); HTRANS_S0 : out std_logic_vector(1 downto 0); HTRANS_S1 : out std_logic_vector(1 downto 0); HTRANS_S10 : out std_logic_vector(1 downto 0); HTRANS_S11 : out std_logic_vector(1 downto 0); HTRANS_S12 : out std_logic_vector(1 downto 0); HTRANS_S13 : out std_logic_vector(1 downto 0); HTRANS_S14 : out std_logic_vector(1 downto 0); HTRANS_S15 : out std_logic_vector(1 downto 0); HTRANS_S16 : out std_logic_vector(1 downto 0); HTRANS_S2 : out std_logic_vector(1 downto 0); HTRANS_S3 : out std_logic_vector(1 downto 0); HTRANS_S4 : out std_logic_vector(1 downto 0); HTRANS_S5 : out std_logic_vector(1 downto 0); HTRANS_S6 : out std_logic_vector(1 downto 0); HTRANS_S7 : out std_logic_vector(1 downto 0); HTRANS_S8 : out std_logic_vector(1 downto 0); HTRANS_S9 : out std_logic_vector(1 downto 0); HWDATA_S0 : out std_logic_vector(31 downto 0); HWDATA_S1 : out std_logic_vector(31 downto 0); HWDATA_S10 : out std_logic_vector(31 downto 0); HWDATA_S11 : out std_logic_vector(31 downto 0); HWDATA_S12 : out std_logic_vector(31 downto 0); HWDATA_S13 : out std_logic_vector(31 downto 0); HWDATA_S14 : out std_logic_vector(31 downto 0); HWDATA_S15 : out std_logic_vector(31 downto 0); HWDATA_S16 : out std_logic_vector(31 downto 0); HWDATA_S2 : out std_logic_vector(31 downto 0); HWDATA_S3 : out std_logic_vector(31 downto 0); HWDATA_S4 : out std_logic_vector(31 downto 0); HWDATA_S5 : out std_logic_vector(31 downto 0); HWDATA_S6 : out std_logic_vector(31 downto 0); HWDATA_S7 : out std_logic_vector(31 downto 0); HWDATA_S8 : out std_logic_vector(31 downto 0); HWDATA_S9 : out std_logic_vector(31 downto 0); HWRITE_S0 : out std_logic; HWRITE_S1 : out std_logic; HWRITE_S10 : out std_logic; HWRITE_S11 : out std_logic; HWRITE_S12 : out std_logic; HWRITE_S13 : out std_logic; HWRITE_S14 : out std_logic; HWRITE_S15 : out std_logic; HWRITE_S16 : out std_logic; HWRITE_S2 : out std_logic; HWRITE_S3 : out std_logic; HWRITE_S4 : out std_logic; HWRITE_S5 : out std_logic; HWRITE_S6 : out std_logic; HWRITE_S7 : out std_logic; HWRITE_S8 : out std_logic; HWRITE_S9 : out std_logic ); end component; -- CoreAPB - Actel:DirectCore:CoreAPB:1.1.101 component CoreAPB generic( ApbSlot0Enable : integer := 1 ; ApbSlot1Enable : integer := 0 ; ApbSlot2Enable : integer := 0 ; ApbSlot3Enable : integer := 0 ; ApbSlot4Enable : integer := 0 ; ApbSlot5Enable : integer := 0 ; ApbSlot6Enable : integer := 0 ; ApbSlot7Enable : integer := 0 ; ApbSlot8Enable : integer := 0 ; ApbSlot9Enable : integer := 0 ; ApbSlot10Enable : integer := 0 ; ApbSlot11Enable : integer := 0 ; ApbSlot12Enable : integer := 0 ; ApbSlot13Enable : integer := 0 ; ApbSlot14Enable : integer := 0 ; ApbSlot15Enable : integer := 0 ); -- Port list port( -- Inputs PADDR : in std_logic_vector(23 downto 0); PENABLE : in std_logic; PRDATAS0 : in std_logic_vector(31 downto 0); PRDATAS1 : in std_logic_vector(31 downto 0); PRDATAS10 : in std_logic_vector(31 downto 0); PRDATAS11 : in std_logic_vector(31 downto 0); PRDATAS12 : in std_logic_vector(31 downto 0); PRDATAS13 : in std_logic_vector(31 downto 0); PRDATAS14 : in std_logic_vector(31 downto 0); PRDATAS15 : in std_logic_vector(31 downto 0); PRDATAS2 : in std_logic_vector(31 downto 0); PRDATAS3 : in std_logic_vector(31 downto 0); PRDATAS4 : in std_logic_vector(31 downto 0); PRDATAS5 : in std_logic_vector(31 downto 0); PRDATAS6 : in std_logic_vector(31 downto 0); PRDATAS7 : in std_logic_vector(31 downto 0); PRDATAS8 : in std_logic_vector(31 downto 0); PRDATAS9 : in std_logic_vector(31 downto 0); PSELECT : in std_logic_vector(15 downto 0); PWDATA : in std_logic_vector(31 downto 0); PWRITE : in std_logic; -- Outputs PADDRS : out std_logic_vector(23 downto 0); PENABLES : out std_logic; PRDATA : out std_logic_vector(31 downto 0); PSELS0 : out std_logic; PSELS1 : out std_logic; PSELS10 : out std_logic; PSELS11 : out std_logic; PSELS12 : out std_logic; PSELS13 : out std_logic; PSELS14 : out std_logic; PSELS15 : out std_logic; PSELS2 : out std_logic; PSELS3 : out std_logic; PSELS4 : out std_logic; PSELS5 : out std_logic; PSELS6 : out std_logic; PSELS7 : out std_logic; PSELS8 : out std_logic; PSELS9 : out std_logic; PWDATAS : out std_logic_vector(31 downto 0); PWRITES : out std_logic ); end component; -- top_CoreUARTapb_0_CoreUARTapb - Actel:DirectCore:CoreUARTapb:5.6.102 component top_CoreUARTapb_0_CoreUARTapb generic( BAUD_VAL_FRCTN : integer := 0 ; BAUD_VAL_FRCTN_EN : integer := 0 ; BAUD_VALUE : integer := 1 ; FAMILY : integer := 15 ; FIXEDMODE : integer := 1 ; PRG_BIT8 : integer := 1 ; PRG_PARITY : integer := 0 ; RX_FIFO : integer := 0 ; RX_LEGACY_MODE : integer := 0 ; TX_FIFO : integer := 0 ); -- Port list port( -- Inputs PADDR : in std_logic_vector(4 downto 0); PCLK : in std_logic; PENABLE : in std_logic; PRESETN : in std_logic; PSEL : in std_logic; PWDATA : in std_logic_vector(7 downto 0); PWRITE : in std_logic; RX : in std_logic; -- Outputs FRAMING_ERR : out std_logic; OVERFLOW : out std_logic; PARITY_ERR : out std_logic; PRDATA : out std_logic_vector(7 downto 0); PREADY : out std_logic; PSLVERR : out std_logic; RXRDY : out std_logic; TX : out std_logic; TXRDY : out std_logic ); end component; ---------------------------------------------------------------------- -- Signal declarations ---------------------------------------------------------------------- signal ahb_busy_net_0 : std_logic; signal AHBMASTER_FIC_0_AHBmaster_HADDR : std_logic_vector(31 downto 0); signal AHBMASTER_FIC_0_AHBmaster_HBURST : std_logic_vector(2 downto 0); signal AHBMASTER_FIC_0_AHBmaster_HPROT : std_logic_vector(3 downto 0); signal AHBMASTER_FIC_0_AHBmaster_HRDATA : std_logic_vector(31 downto 0); signal AHBMASTER_FIC_0_AHBmaster_HREADY : std_logic; signal AHBMASTER_FIC_0_AHBmaster_HRESP : std_logic_vector(1 downto 0); signal AHBMASTER_FIC_0_AHBmaster_HSIZE : std_logic_vector(2 downto 0); signal AHBMASTER_FIC_0_AHBmaster_HTRANS : std_logic_vector(1 downto 0); signal AHBMASTER_FIC_0_AHBmaster_HWDATA : std_logic_vector(31 downto 0); signal AHBMASTER_FIC_0_AHBmaster_HWRITE : std_logic; signal CoreAHB2APB_0_APBmaster_PADDR : std_logic_vector(23 downto 0); signal CoreAHB2APB_0_APBmaster_PENABLE : std_logic; signal CoreAHB2APB_0_APBmaster_PRDATA : std_logic_vector(31 downto 0); signal CoreAHB2APB_0_APBmaster_PSELx : std_logic_vector(15 downto 0); signal CoreAHB2APB_0_APBmaster_PWDATA : std_logic_vector(31 downto 0); signal CoreAHB2APB_0_APBmaster_PWRITE : std_logic; signal CoreAHBLite_0_AHBmslave0_HBURST : std_logic_vector(2 downto 0); signal CoreAHBLite_0_AHBmslave0_HMASTLOCK : std_logic; signal CoreAHBLite_0_AHBmslave0_HPROT : std_logic_vector(3 downto 0); signal CoreAHBLite_0_AHBmslave0_HRDATA : std_logic_vector(31 downto 0); signal CoreAHBLite_0_AHBmslave0_HREADY : std_logic; signal CoreAHBLite_0_AHBmslave0_HREADYOUT : std_logic; signal CoreAHBLite_0_AHBmslave0_HRESP : std_logic_vector(1 downto 0); signal CoreAHBLite_0_AHBmslave0_HSELx : std_logic; signal CoreAHBLite_0_AHBmslave0_HSIZE : std_logic_vector(2 downto 0); signal CoreAHBLite_0_AHBmslave0_HTRANS : std_logic_vector(1 downto 0); signal CoreAHBLite_0_AHBmslave0_HWDATA : std_logic_vector(31 downto 0); signal CoreAHBLite_0_AHBmslave0_HWRITE : std_logic; signal CoreAPB_0_APBmslave0_PENABLE : std_logic; signal CoreAPB_0_APBmslave0_PREADY : std_logic; signal CoreAPB_0_APBmslave0_PSELx : std_logic; signal CoreAPB_0_APBmslave0_PSLVERR : std_logic; signal CoreAPB_0_APBmslave0_PWRITE : std_logic; signal DATAOUT_net_0 : std_logic_vector(31 downto 0); signal RESP_err_net_0 : std_logic_vector(1 downto 0); signal TX_net_0 : std_logic; signal ahb_busy_net_1 : std_logic; signal DATAOUT_net_1 : std_logic_vector(31 downto 0); signal RESP_err_net_1 : std_logic_vector(1 downto 0); signal TX_net_1 : std_logic; ---------------------------------------------------------------------- -- TiedOff Signals ---------------------------------------------------------------------- signal GND_net : std_logic; signal VCC_net : std_logic; signal HADDR_M1_const_net_0 : std_logic_vector(31 downto 0); signal HTRANS_M1_const_net_0 : std_logic_vector(1 downto 0); signal HSIZE_M1_const_net_0 : std_logic_vector(2 downto 0); signal HBURST_M1_const_net_0 : std_logic_vector(2 downto 0); signal HPROT_M1_const_net_0 : std_logic_vector(3 downto 0); signal HWDATA_M1_const_net_0 : std_logic_vector(31 downto 0); signal HADDR_M2_const_net_0 : std_logic_vector(31 downto 0); signal HTRANS_M2_const_net_0 : std_logic_vector(1 downto 0); signal HSIZE_M2_const_net_0 : std_logic_vector(2 downto 0); signal HBURST_M2_const_net_0 : std_logic_vector(2 downto 0); signal HPROT_M2_const_net_0 : std_logic_vector(3 downto 0); signal HWDATA_M2_const_net_0 : std_logic_vector(31 downto 0); signal HADDR_M3_const_net_0 : std_logic_vector(31 downto 0); signal HTRANS_M3_const_net_0 : std_logic_vector(1 downto 0); signal HSIZE_M3_const_net_0 : std_logic_vector(2 downto 0); signal HBURST_M3_const_net_0 : std_logic_vector(2 downto 0); signal HPROT_M3_const_net_0 : std_logic_vector(3 downto 0); signal HWDATA_M3_const_net_0 : std_logic_vector(31 downto 0); signal HRDATA_S1_const_net_0 : std_logic_vector(31 downto 0); signal HRESP_S1_const_net_0 : std_logic_vector(1 downto 0); signal HRDATA_S2_const_net_0 : std_logic_vector(31 downto 0); signal HRESP_S2_const_net_0 : std_logic_vector(1 downto 0); signal HRDATA_S3_const_net_0 : std_logic_vector(31 downto 0); signal HRESP_S3_const_net_0 : std_logic_vector(1 downto 0); signal HRDATA_S4_const_net_0 : std_logic_vector(31 downto 0); signal HRESP_S4_const_net_0 : std_logic_vector(1 downto 0); signal HRDATA_S5_const_net_0 : std_logic_vector(31 downto 0); signal HRESP_S5_const_net_0 : std_logic_vector(1 downto 0); signal HRDATA_S6_const_net_0 : std_logic_vector(31 downto 0); signal HRESP_S6_const_net_0 : std_logic_vector(1 downto 0); signal HRDATA_S7_const_net_0 : std_logic_vector(31 downto 0); signal HRESP_S7_const_net_0 : std_logic_vector(1 downto 0); signal HRDATA_S8_const_net_0 : std_logic_vector(31 downto 0); signal HRESP_S8_const_net_0 : std_logic_vector(1 downto 0); signal HRDATA_S9_const_net_0 : std_logic_vector(31 downto 0); signal HRESP_S9_const_net_0 : std_logic_vector(1 downto 0); signal HRDATA_S10_const_net_0 : std_logic_vector(31 downto 0); signal HRESP_S10_const_net_0 : std_logic_vector(1 downto 0); signal HRDATA_S11_const_net_0 : std_logic_vector(31 downto 0); signal HRESP_S11_const_net_0 : std_logic_vector(1 downto 0); signal HRDATA_S12_const_net_0 : std_logic_vector(31 downto 0); signal HRESP_S12_const_net_0 : std_logic_vector(1 downto 0); signal HRDATA_S13_const_net_0 : std_logic_vector(31 downto 0); signal HRESP_S13_const_net_0 : std_logic_vector(1 downto 0); signal HRDATA_S14_const_net_0 : std_logic_vector(31 downto 0); signal HRESP_S14_const_net_0 : std_logic_vector(1 downto 0); signal HRDATA_S15_const_net_0 : std_logic_vector(31 downto 0); signal HRESP_S15_const_net_0 : std_logic_vector(1 downto 0); signal HRDATA_S16_const_net_0 : std_logic_vector(31 downto 0); signal HRESP_S16_const_net_0 : std_logic_vector(1 downto 0); signal PRDATAS1_const_net_0 : std_logic_vector(31 downto 0); signal PRDATAS2_const_net_0 : std_logic_vector(31 downto 0); signal PRDATAS3_const_net_0 : std_logic_vector(31 downto 0); signal PRDATAS4_const_net_0 : std_logic_vector(31 downto 0); signal PRDATAS5_const_net_0 : std_logic_vector(31 downto 0); signal PRDATAS6_const_net_0 : std_logic_vector(31 downto 0); signal PRDATAS7_const_net_0 : std_logic_vector(31 downto 0); signal PRDATAS8_const_net_0 : std_logic_vector(31 downto 0); signal PRDATAS9_const_net_0 : std_logic_vector(31 downto 0); signal PRDATAS10_const_net_0 : std_logic_vector(31 downto 0); signal PRDATAS11_const_net_0 : std_logic_vector(31 downto 0); signal PRDATAS12_const_net_0 : std_logic_vector(31 downto 0); signal PRDATAS13_const_net_0 : std_logic_vector(31 downto 0); signal PRDATAS14_const_net_0 : std_logic_vector(31 downto 0); signal PRDATAS15_const_net_0 : std_logic_vector(31 downto 0); ---------------------------------------------------------------------- -- Bus Interface Nets Declarations - Unequal Pin Widths ---------------------------------------------------------------------- signal CoreAHBLite_0_AHBmslave0_HADDR_0_27to0: std_logic_vector(27 downto 0); signal CoreAHBLite_0_AHBmslave0_HADDR_0 : std_logic_vector(27 downto 0); signal CoreAHBLite_0_AHBmslave0_HADDR : std_logic_vector(31 downto 0); signal CoreAPB_0_APBmslave0_PADDR : std_logic_vector(23 downto 0); signal CoreAPB_0_APBmslave0_PADDR_0_4to0 : std_logic_vector(4 downto 0); signal CoreAPB_0_APBmslave0_PADDR_0 : std_logic_vector(4 downto 0); signal CoreAPB_0_APBmslave0_PRDATA_0_31to8: std_logic_vector(31 downto 8); signal CoreAPB_0_APBmslave0_PRDATA_0_7to0 : std_logic_vector(7 downto 0); signal CoreAPB_0_APBmslave0_PRDATA_0 : std_logic_vector(31 downto 0); signal CoreAPB_0_APBmslave0_PRDATA : std_logic_vector(7 downto 0); signal CoreAPB_0_APBmslave0_PWDATA : std_logic_vector(31 downto 0); signal CoreAPB_0_APBmslave0_PWDATA_0_7to0 : std_logic_vector(7 downto 0); signal CoreAPB_0_APBmslave0_PWDATA_0 : std_logic_vector(7 downto 0); begin ---------------------------------------------------------------------- -- Constant assignments ---------------------------------------------------------------------- GND_net <= '0'; VCC_net <= '1'; HADDR_M1_const_net_0 <= B"00000000000000000000000000000000"; HTRANS_M1_const_net_0 <= B"00"; HSIZE_M1_const_net_0 <= B"000"; HBURST_M1_const_net_0 <= B"000"; HPROT_M1_const_net_0 <= B"0000"; HWDATA_M1_const_net_0 <= B"00000000000000000000000000000000"; HADDR_M2_const_net_0 <= B"00000000000000000000000000000000"; HTRANS_M2_const_net_0 <= B"00"; HSIZE_M2_const_net_0 <= B"000"; HBURST_M2_const_net_0 <= B"000"; HPROT_M2_const_net_0 <= B"0000"; HWDATA_M2_const_net_0 <= B"00000000000000000000000000000000"; HADDR_M3_const_net_0 <= B"00000000000000000000000000000000"; HTRANS_M3_const_net_0 <= B"00"; HSIZE_M3_const_net_0 <= B"000"; HBURST_M3_const_net_0 <= B"000"; HPROT_M3_const_net_0 <= B"0000"; HWDATA_M3_const_net_0 <= B"00000000000000000000000000000000"; HRDATA_S1_const_net_0 <= B"00000000000000000000000000000000"; HRESP_S1_const_net_0 <= B"00"; HRDATA_S2_const_net_0 <= B"00000000000000000000000000000000"; HRESP_S2_const_net_0 <= B"00"; HRDATA_S3_const_net_0 <= B"00000000000000000000000000000000"; HRESP_S3_const_net_0 <= B"00"; HRDATA_S4_const_net_0 <= B"00000000000000000000000000000000"; HRESP_S4_const_net_0 <= B"00"; HRDATA_S5_const_net_0 <= B"00000000000000000000000000000000"; HRESP_S5_const_net_0 <= B"00"; HRDATA_S6_const_net_0 <= B"00000000000000000000000000000000"; HRESP_S6_const_net_0 <= B"00"; HRDATA_S7_const_net_0 <= B"00000000000000000000000000000000"; HRESP_S7_const_net_0 <= B"00"; HRDATA_S8_const_net_0 <= B"00000000000000000000000000000000"; HRESP_S8_const_net_0 <= B"00"; HRDATA_S9_const_net_0 <= B"00000000000000000000000000000000"; HRESP_S9_const_net_0 <= B"00"; HRDATA_S10_const_net_0 <= B"00000000000000000000000000000000"; HRESP_S10_const_net_0 <= B"00"; HRDATA_S11_const_net_0 <= B"00000000000000000000000000000000"; HRESP_S11_const_net_0 <= B"00"; HRDATA_S12_const_net_0 <= B"00000000000000000000000000000000"; HRESP_S12_const_net_0 <= B"00"; HRDATA_S13_const_net_0 <= B"00000000000000000000000000000000"; HRESP_S13_const_net_0 <= B"00"; HRDATA_S14_const_net_0 <= B"00000000000000000000000000000000"; HRESP_S14_const_net_0 <= B"00"; HRDATA_S15_const_net_0 <= B"00000000000000000000000000000000"; HRESP_S15_const_net_0 <= B"00"; HRDATA_S16_const_net_0 <= B"00000000000000000000000000000000"; HRESP_S16_const_net_0 <= B"00"; PRDATAS1_const_net_0 <= B"00000000000000000000000000000000"; PRDATAS2_const_net_0 <= B"00000000000000000000000000000000"; PRDATAS3_const_net_0 <= B"00000000000000000000000000000000"; PRDATAS4_const_net_0 <= B"00000000000000000000000000000000"; PRDATAS5_const_net_0 <= B"00000000000000000000000000000000"; PRDATAS6_const_net_0 <= B"00000000000000000000000000000000"; PRDATAS7_const_net_0 <= B"00000000000000000000000000000000"; PRDATAS8_const_net_0 <= B"00000000000000000000000000000000"; PRDATAS9_const_net_0 <= B"00000000000000000000000000000000"; PRDATAS10_const_net_0 <= B"00000000000000000000000000000000"; PRDATAS11_const_net_0 <= B"00000000000000000000000000000000"; PRDATAS12_const_net_0 <= B"00000000000000000000000000000000"; PRDATAS13_const_net_0 <= B"00000000000000000000000000000000"; PRDATAS14_const_net_0 <= B"00000000000000000000000000000000"; PRDATAS15_const_net_0 <= B"00000000000000000000000000000000"; ---------------------------------------------------------------------- -- Top level output port assignments ---------------------------------------------------------------------- ahb_busy_net_1 <= ahb_busy_net_0; ahb_busy <= ahb_busy_net_1; DATAOUT_net_1 <= DATAOUT_net_0; DATAOUT(31 downto 0) <= DATAOUT_net_1; RESP_err_net_1 <= RESP_err_net_0; RESP_err(1 downto 0) <= RESP_err_net_1; TX_net_1 <= TX_net_0; TX <= TX_net_1; ---------------------------------------------------------------------- -- Bus Interface Nets Assignments - Unequal Pin Widths ---------------------------------------------------------------------- CoreAHBLite_0_AHBmslave0_HADDR_0_27to0(27 downto 0) <= CoreAHBLite_0_AHBmslave0_HADDR(27 downto 0); CoreAHBLite_0_AHBmslave0_HADDR_0 <= ( CoreAHBLite_0_AHBmslave0_HADDR_0_27to0(27 downto 0) ); CoreAPB_0_APBmslave0_PADDR_0_4to0(4 downto 0) <= CoreAPB_0_APBmslave0_PADDR(4 downto 0); CoreAPB_0_APBmslave0_PADDR_0 <= ( CoreAPB_0_APBmslave0_PADDR_0_4to0(4 downto 0) ); CoreAPB_0_APBmslave0_PRDATA_0_31to8(31 downto 8) <= B"000000000000000000000000"; CoreAPB_0_APBmslave0_PRDATA_0_7to0(7 downto 0) <= CoreAPB_0_APBmslave0_PRDATA(7 downto 0); CoreAPB_0_APBmslave0_PRDATA_0 <= ( CoreAPB_0_APBmslave0_PRDATA_0_31to8(31 downto 8) & CoreAPB_0_APBmslave0_PRDATA_0_7to0(7 downto 0) ); CoreAPB_0_APBmslave0_PWDATA_0_7to0(7 downto 0) <= CoreAPB_0_APBmslave0_PWDATA(7 downto 0); CoreAPB_0_APBmslave0_PWDATA_0 <= ( CoreAPB_0_APBmslave0_PWDATA_0_7to0(7 downto 0) ); ---------------------------------------------------------------------- -- Component instances ---------------------------------------------------------------------- -- AHBMASTER_FIC_0 AHBMASTER_FIC_0 : entity work.AHBMASTER_FIC port map( -- Inputs HCLK => HCLK, HRESETn => HRESETn, LREAD => LREAD, LWRITE => LWRITE, HREADY => AHBMASTER_FIC_0_AHBmaster_HREADY, ADDR => ADDR, DATAIN => DATAIN, HRDATA => AHBMASTER_FIC_0_AHBmaster_HRDATA, HRESP => AHBMASTER_FIC_0_AHBmaster_HRESP, -- Outputs HWRITE => AHBMASTER_FIC_0_AHBmaster_HWRITE, ahb_busy => ahb_busy_net_0, DATAOUT => DATAOUT_net_0, HADDR => AHBMASTER_FIC_0_AHBmaster_HADDR, HTRANS => AHBMASTER_FIC_0_AHBmaster_HTRANS, HSIZE => AHBMASTER_FIC_0_AHBmaster_HSIZE, HBURST => AHBMASTER_FIC_0_AHBmaster_HBURST, HPROT => AHBMASTER_FIC_0_AHBmaster_HPROT, HWDATA => AHBMASTER_FIC_0_AHBmaster_HWDATA, RESP_err => RESP_err_net_0 ); -- CoreAHB2APB_0 - Actel:DirectCore:CoreAHB2APB:1.1.101 CoreAHB2APB_0 : CoreAHB2APB port map( -- Inputs HCLK => HCLK, HRESETn => HRESETn, HWRITE => CoreAHBLite_0_AHBmslave0_HWRITE, HSEL => CoreAHBLite_0_AHBmslave0_HSELx, HREADY => CoreAHBLite_0_AHBmslave0_HREADY, HADDR => CoreAHBLite_0_AHBmslave0_HADDR_0, HTRANS => CoreAHBLite_0_AHBmslave0_HTRANS, HWDATA => CoreAHBLite_0_AHBmslave0_HWDATA, PRDATA => CoreAHB2APB_0_APBmaster_PRDATA, -- Outputs HREADYOUT => CoreAHBLite_0_AHBmslave0_HREADYOUT, PENABLE => CoreAHB2APB_0_APBmaster_PENABLE, PWRITE => CoreAHB2APB_0_APBmaster_PWRITE, HRDATA => CoreAHBLite_0_AHBmslave0_HRDATA, HRESP => CoreAHBLite_0_AHBmslave0_HRESP, PWDATA => CoreAHB2APB_0_APBmaster_PWDATA, PADDR => CoreAHB2APB_0_APBmaster_PADDR, PSELECT => CoreAHB2APB_0_APBmaster_PSELx ); -- CoreAHBLite_0 - Actel:DirectCore:CoreAHBLite:5.3.101 CoreAHBLite_0 : top_CoreAHBLite_0_CoreAHBLite generic map( FAMILY => ( 15 ), HADDR_SHG_CFG => ( 1 ), M0_AHBSLOT0ENABLE => ( 1 ), M0_AHBSLOT1ENABLE => ( 0 ), M0_AHBSLOT2ENABLE => ( 0 ), M0_AHBSLOT3ENABLE => ( 0 ), M0_AHBSLOT4ENABLE => ( 0 ), M0_AHBSLOT5ENABLE => ( 0 ), M0_AHBSLOT6ENABLE => ( 0 ), M0_AHBSLOT7ENABLE => ( 0 ), M0_AHBSLOT8ENABLE => ( 0 ), M0_AHBSLOT9ENABLE => ( 0 ), M0_AHBSLOT10ENABLE => ( 0 ), M0_AHBSLOT11ENABLE => ( 0 ), M0_AHBSLOT12ENABLE => ( 0 ), M0_AHBSLOT13ENABLE => ( 0 ), M0_AHBSLOT14ENABLE => ( 0 ), M0_AHBSLOT15ENABLE => ( 0 ), M0_AHBSLOT16ENABLE => ( 0 ), M1_AHBSLOT0ENABLE => ( 0 ), M1_AHBSLOT1ENABLE => ( 0 ), M1_AHBSLOT2ENABLE => ( 0 ), M1_AHBSLOT3ENABLE => ( 0 ), M1_AHBSLOT4ENABLE => ( 0 ), M1_AHBSLOT5ENABLE => ( 0 ), M1_AHBSLOT6ENABLE => ( 0 ), M1_AHBSLOT7ENABLE => ( 0 ), M1_AHBSLOT8ENABLE => ( 0 ), M1_AHBSLOT9ENABLE => ( 0 ), M1_AHBSLOT10ENABLE => ( 0 ), M1_AHBSLOT11ENABLE => ( 0 ), M1_AHBSLOT12ENABLE => ( 0 ), M1_AHBSLOT13ENABLE => ( 0 ), M1_AHBSLOT14ENABLE => ( 0 ), M1_AHBSLOT15ENABLE => ( 0 ), M1_AHBSLOT16ENABLE => ( 0 ), M2_AHBSLOT0ENABLE => ( 0 ), M2_AHBSLOT1ENABLE => ( 0 ), M2_AHBSLOT2ENABLE => ( 0 ), M2_AHBSLOT3ENABLE => ( 0 ), M2_AHBSLOT4ENABLE => ( 0 ), M2_AHBSLOT5ENABLE => ( 0 ), M2_AHBSLOT6ENABLE => ( 0 ), M2_AHBSLOT7ENABLE => ( 0 ), M2_AHBSLOT8ENABLE => ( 0 ), M2_AHBSLOT9ENABLE => ( 0 ), M2_AHBSLOT10ENABLE => ( 0 ), M2_AHBSLOT11ENABLE => ( 0 ), M2_AHBSLOT12ENABLE => ( 0 ), M2_AHBSLOT13ENABLE => ( 0 ), M2_AHBSLOT14ENABLE => ( 0 ), M2_AHBSLOT15ENABLE => ( 0 ), M2_AHBSLOT16ENABLE => ( 0 ), M3_AHBSLOT0ENABLE => ( 0 ), M3_AHBSLOT1ENABLE => ( 0 ), M3_AHBSLOT2ENABLE => ( 0 ), M3_AHBSLOT3ENABLE => ( 0 ), M3_AHBSLOT4ENABLE => ( 0 ), M3_AHBSLOT5ENABLE => ( 0 ), M3_AHBSLOT6ENABLE => ( 0 ), M3_AHBSLOT7ENABLE => ( 0 ), M3_AHBSLOT8ENABLE => ( 0 ), M3_AHBSLOT9ENABLE => ( 0 ), M3_AHBSLOT10ENABLE => ( 0 ), M3_AHBSLOT11ENABLE => ( 0 ), M3_AHBSLOT12ENABLE => ( 0 ), M3_AHBSLOT13ENABLE => ( 0 ), M3_AHBSLOT14ENABLE => ( 0 ), M3_AHBSLOT15ENABLE => ( 0 ), M3_AHBSLOT16ENABLE => ( 0 ), MEMSPACE => ( 1 ), SC_0 => ( 0 ), SC_1 => ( 0 ), SC_2 => ( 0 ), SC_3 => ( 0 ), SC_4 => ( 0 ), SC_5 => ( 0 ), SC_6 => ( 0 ), SC_7 => ( 0 ), SC_8 => ( 0 ), SC_9 => ( 0 ), SC_10 => ( 0 ), SC_11 => ( 0 ), SC_12 => ( 0 ), SC_13 => ( 0 ), SC_14 => ( 0 ), SC_15 => ( 0 ) ) port map( -- Inputs HCLK => HCLK, HRESETN => HRESETn, REMAP_M0 => GND_net, HMASTLOCK_M0 => GND_net, -- tied to '0' from definition HWRITE_M0 => AHBMASTER_FIC_0_AHBmaster_HWRITE, HMASTLOCK_M1 => GND_net, -- tied to '0' from definition HWRITE_M1 => GND_net, -- tied to '0' from definition HMASTLOCK_M2 => GND_net, -- tied to '0' from definition HWRITE_M2 => GND_net, -- tied to '0' from definition HMASTLOCK_M3 => GND_net, -- tied to '0' from definition HWRITE_M3 => GND_net, -- tied to '0' from definition HREADYOUT_S0 => CoreAHBLite_0_AHBmslave0_HREADYOUT, HREADYOUT_S1 => VCC_net, -- tied to '1' from definition HREADYOUT_S2 => VCC_net, -- tied to '1' from definition HREADYOUT_S3 => VCC_net, -- tied to '1' from definition HREADYOUT_S4 => VCC_net, -- tied to '1' from definition HREADYOUT_S5 => VCC_net, -- tied to '1' from definition HREADYOUT_S6 => VCC_net, -- tied to '1' from definition HREADYOUT_S7 => VCC_net, -- tied to '1' from definition HREADYOUT_S8 => VCC_net, -- tied to '1' from definition HREADYOUT_S9 => VCC_net, -- tied to '1' from definition HREADYOUT_S10 => VCC_net, -- tied to '1' from definition HREADYOUT_S11 => VCC_net, -- tied to '1' from definition HREADYOUT_S12 => VCC_net, -- tied to '1' from definition HREADYOUT_S13 => VCC_net, -- tied to '1' from definition HREADYOUT_S14 => VCC_net, -- tied to '1' from definition HREADYOUT_S15 => VCC_net, -- tied to '1' from definition HREADYOUT_S16 => VCC_net, -- tied to '1' from definition HADDR_M0 => AHBMASTER_FIC_0_AHBmaster_HADDR, HSIZE_M0 => AHBMASTER_FIC_0_AHBmaster_HSIZE, HTRANS_M0 => AHBMASTER_FIC_0_AHBmaster_HTRANS, HWDATA_M0 => AHBMASTER_FIC_0_AHBmaster_HWDATA, HBURST_M0 => AHBMASTER_FIC_0_AHBmaster_HBURST, HPROT_M0 => AHBMASTER_FIC_0_AHBmaster_HPROT, HADDR_M1 => HADDR_M1_const_net_0, -- tied to X"0" from definition HSIZE_M1 => HSIZE_M1_const_net_0, -- tied to X"0" from definition HTRANS_M1 => HTRANS_M1_const_net_0, -- tied to X"0" from definition HWDATA_M1 => HWDATA_M1_const_net_0, -- tied to X"0" from definition HBURST_M1 => HBURST_M1_const_net_0, -- tied to X"0" from definition HPROT_M1 => HPROT_M1_const_net_0, -- tied to X"0" from definition HADDR_M2 => HADDR_M2_const_net_0, -- tied to X"0" from definition HSIZE_M2 => HSIZE_M2_const_net_0, -- tied to X"0" from definition HTRANS_M2 => HTRANS_M2_const_net_0, -- tied to X"0" from definition HWDATA_M2 => HWDATA_M2_const_net_0, -- tied to X"0" from definition HBURST_M2 => HBURST_M2_const_net_0, -- tied to X"0" from definition HPROT_M2 => HPROT_M2_const_net_0, -- tied to X"0" from definition HADDR_M3 => HADDR_M3_const_net_0, -- tied to X"0" from definition HSIZE_M3 => HSIZE_M3_const_net_0, -- tied to X"0" from definition HTRANS_M3 => HTRANS_M3_const_net_0, -- tied to X"0" from definition HWDATA_M3 => HWDATA_M3_const_net_0, -- tied to X"0" from definition HBURST_M3 => HBURST_M3_const_net_0, -- tied to X"0" from definition HPROT_M3 => HPROT_M3_const_net_0, -- tied to X"0" from definition HRDATA_S0 => CoreAHBLite_0_AHBmslave0_HRDATA, HRESP_S0 => CoreAHBLite_0_AHBmslave0_HRESP, HRDATA_S1 => HRDATA_S1_const_net_0, -- tied to X"0" from definition HRESP_S1 => HRESP_S1_const_net_0, -- tied to X"0" from definition HRDATA_S2 => HRDATA_S2_const_net_0, -- tied to X"0" from definition HRESP_S2 => HRESP_S2_const_net_0, -- tied to X"0" from definition HRDATA_S3 => HRDATA_S3_const_net_0, -- tied to X"0" from definition HRESP_S3 => HRESP_S3_const_net_0, -- tied to X"0" from definition HRDATA_S4 => HRDATA_S4_const_net_0, -- tied to X"0" from definition HRESP_S4 => HRESP_S4_const_net_0, -- tied to X"0" from definition HRDATA_S5 => HRDATA_S5_const_net_0, -- tied to X"0" from definition HRESP_S5 => HRESP_S5_const_net_0, -- tied to X"0" from definition HRDATA_S6 => HRDATA_S6_const_net_0, -- tied to X"0" from definition HRESP_S6 => HRESP_S6_const_net_0, -- tied to X"0" from definition HRDATA_S7 => HRDATA_S7_const_net_0, -- tied to X"0" from definition HRESP_S7 => HRESP_S7_const_net_0, -- tied to X"0" from definition HRDATA_S8 => HRDATA_S8_const_net_0, -- tied to X"0" from definition HRESP_S8 => HRESP_S8_const_net_0, -- tied to X"0" from definition HRDATA_S9 => HRDATA_S9_const_net_0, -- tied to X"0" from definition HRESP_S9 => HRESP_S9_const_net_0, -- tied to X"0" from definition HRDATA_S10 => HRDATA_S10_const_net_0, -- tied to X"0" from definition HRESP_S10 => HRESP_S10_const_net_0, -- tied to X"0" from definition HRDATA_S11 => HRDATA_S11_const_net_0, -- tied to X"0" from definition HRESP_S11 => HRESP_S11_const_net_0, -- tied to X"0" from definition HRDATA_S12 => HRDATA_S12_const_net_0, -- tied to X"0" from definition HRESP_S12 => HRESP_S12_const_net_0, -- tied to X"0" from definition HRDATA_S13 => HRDATA_S13_const_net_0, -- tied to X"0" from definition HRESP_S13 => HRESP_S13_const_net_0, -- tied to X"0" from definition HRDATA_S14 => HRDATA_S14_const_net_0, -- tied to X"0" from definition HRESP_S14 => HRESP_S14_const_net_0, -- tied to X"0" from definition HRDATA_S15 => HRDATA_S15_const_net_0, -- tied to X"0" from definition HRESP_S15 => HRESP_S15_const_net_0, -- tied to X"0" from definition HRDATA_S16 => HRDATA_S16_const_net_0, -- tied to X"0" from definition HRESP_S16 => HRESP_S16_const_net_0, -- tied to X"0" from definition -- Outputs HREADY_M0 => AHBMASTER_FIC_0_AHBmaster_HREADY, HREADY_M1 => OPEN, HREADY_M2 => OPEN, HREADY_M3 => OPEN, HSEL_S0 => CoreAHBLite_0_AHBmslave0_HSELx, HWRITE_S0 => CoreAHBLite_0_AHBmslave0_HWRITE, HREADY_S0 => CoreAHBLite_0_AHBmslave0_HREADY, HMASTLOCK_S0 => CoreAHBLite_0_AHBmslave0_HMASTLOCK, HSEL_S1 => OPEN, HWRITE_S1 => OPEN, HREADY_S1 => OPEN, HMASTLOCK_S1 => OPEN, HSEL_S2 => OPEN, HWRITE_S2 => OPEN, HREADY_S2 => OPEN, HMASTLOCK_S2 => OPEN, HSEL_S3 => OPEN, HWRITE_S3 => OPEN, HREADY_S3 => OPEN, HMASTLOCK_S3 => OPEN, HSEL_S4 => OPEN, HWRITE_S4 => OPEN, HREADY_S4 => OPEN, HMASTLOCK_S4 => OPEN, HSEL_S5 => OPEN, HWRITE_S5 => OPEN, HREADY_S5 => OPEN, HMASTLOCK_S5 => OPEN, HSEL_S6 => OPEN, HWRITE_S6 => OPEN, HREADY_S6 => OPEN, HMASTLOCK_S6 => OPEN, HSEL_S7 => OPEN, HWRITE_S7 => OPEN, HREADY_S7 => OPEN, HMASTLOCK_S7 => OPEN, HSEL_S8 => OPEN, HWRITE_S8 => OPEN, HREADY_S8 => OPEN, HMASTLOCK_S8 => OPEN, HSEL_S9 => OPEN, HWRITE_S9 => OPEN, HREADY_S9 => OPEN, HMASTLOCK_S9 => OPEN, HSEL_S10 => OPEN, HWRITE_S10 => OPEN, HREADY_S10 => OPEN, HMASTLOCK_S10 => OPEN, HSEL_S11 => OPEN, HWRITE_S11 => OPEN, HREADY_S11 => OPEN, HMASTLOCK_S11 => OPEN, HSEL_S12 => OPEN, HWRITE_S12 => OPEN, HREADY_S12 => OPEN, HMASTLOCK_S12 => OPEN, HSEL_S13 => OPEN, HWRITE_S13 => OPEN, HREADY_S13 => OPEN, HMASTLOCK_S13 => OPEN, HSEL_S14 => OPEN, HWRITE_S14 => OPEN, HREADY_S14 => OPEN, HMASTLOCK_S14 => OPEN, HSEL_S15 => OPEN, HWRITE_S15 => OPEN, HREADY_S15 => OPEN, HMASTLOCK_S15 => OPEN, HSEL_S16 => OPEN, HWRITE_S16 => OPEN, HREADY_S16 => OPEN, HMASTLOCK_S16 => OPEN, HRESP_M0 => AHBMASTER_FIC_0_AHBmaster_HRESP, HRDATA_M0 => AHBMASTER_FIC_0_AHBmaster_HRDATA, HRESP_M1 => OPEN, HRDATA_M1 => OPEN, HRESP_M2 => OPEN, HRDATA_M2 => OPEN, HRESP_M3 => OPEN, HRDATA_M3 => OPEN, HADDR_S0 => CoreAHBLite_0_AHBmslave0_HADDR, HSIZE_S0 => CoreAHBLite_0_AHBmslave0_HSIZE, HTRANS_S0 => CoreAHBLite_0_AHBmslave0_HTRANS, HWDATA_S0 => CoreAHBLite_0_AHBmslave0_HWDATA, HBURST_S0 => CoreAHBLite_0_AHBmslave0_HBURST, HPROT_S0 => CoreAHBLite_0_AHBmslave0_HPROT, HADDR_S1 => OPEN, HSIZE_S1 => OPEN, HTRANS_S1 => OPEN, HWDATA_S1 => OPEN, HBURST_S1 => OPEN, HPROT_S1 => OPEN, HADDR_S2 => OPEN, HSIZE_S2 => OPEN, HTRANS_S2 => OPEN, HWDATA_S2 => OPEN, HBURST_S2 => OPEN, HPROT_S2 => OPEN, HADDR_S3 => OPEN, HSIZE_S3 => OPEN, HTRANS_S3 => OPEN, HWDATA_S3 => OPEN, HBURST_S3 => OPEN, HPROT_S3 => OPEN, HADDR_S4 => OPEN, HSIZE_S4 => OPEN, HTRANS_S4 => OPEN, HWDATA_S4 => OPEN, HBURST_S4 => OPEN, HPROT_S4 => OPEN, HADDR_S5 => OPEN, HSIZE_S5 => OPEN, HTRANS_S5 => OPEN, HWDATA_S5 => OPEN, HBURST_S5 => OPEN, HPROT_S5 => OPEN, HADDR_S6 => OPEN, HSIZE_S6 => OPEN, HTRANS_S6 => OPEN, HWDATA_S6 => OPEN, HBURST_S6 => OPEN, HPROT_S6 => OPEN, HADDR_S7 => OPEN, HSIZE_S7 => OPEN, HTRANS_S7 => OPEN, HWDATA_S7 => OPEN, HBURST_S7 => OPEN, HPROT_S7 => OPEN, HADDR_S8 => OPEN, HSIZE_S8 => OPEN, HTRANS_S8 => OPEN, HWDATA_S8 => OPEN, HBURST_S8 => OPEN, HPROT_S8 => OPEN, HADDR_S9 => OPEN, HSIZE_S9 => OPEN, HTRANS_S9 => OPEN, HWDATA_S9 => OPEN, HBURST_S9 => OPEN, HPROT_S9 => OPEN, HADDR_S10 => OPEN, HSIZE_S10 => OPEN, HTRANS_S10 => OPEN, HWDATA_S10 => OPEN, HBURST_S10 => OPEN, HPROT_S10 => OPEN, HADDR_S11 => OPEN, HSIZE_S11 => OPEN, HTRANS_S11 => OPEN, HWDATA_S11 => OPEN, HBURST_S11 => OPEN, HPROT_S11 => OPEN, HADDR_S12 => OPEN, HSIZE_S12 => OPEN, HTRANS_S12 => OPEN, HWDATA_S12 => OPEN, HBURST_S12 => OPEN, HPROT_S12 => OPEN, HADDR_S13 => OPEN, HSIZE_S13 => OPEN, HTRANS_S13 => OPEN, HWDATA_S13 => OPEN, HBURST_S13 => OPEN, HPROT_S13 => OPEN, HADDR_S14 => OPEN, HSIZE_S14 => OPEN, HTRANS_S14 => OPEN, HWDATA_S14 => OPEN, HBURST_S14 => OPEN, HPROT_S14 => OPEN, HADDR_S15 => OPEN, HSIZE_S15 => OPEN, HTRANS_S15 => OPEN, HWDATA_S15 => OPEN, HBURST_S15 => OPEN, HPROT_S15 => OPEN, HADDR_S16 => OPEN, HSIZE_S16 => OPEN, HTRANS_S16 => OPEN, HWDATA_S16 => OPEN, HBURST_S16 => OPEN, HPROT_S16 => OPEN ); -- CoreAPB_0 - Actel:DirectCore:CoreAPB:1.1.101 CoreAPB_0 : CoreAPB generic map( ApbSlot0Enable => ( 1 ), ApbSlot1Enable => ( 0 ), ApbSlot2Enable => ( 0 ), ApbSlot3Enable => ( 0 ), ApbSlot4Enable => ( 0 ), ApbSlot5Enable => ( 0 ), ApbSlot6Enable => ( 0 ), ApbSlot7Enable => ( 0 ), ApbSlot8Enable => ( 0 ), ApbSlot9Enable => ( 0 ), ApbSlot10Enable => ( 0 ), ApbSlot11Enable => ( 0 ), ApbSlot12Enable => ( 0 ), ApbSlot13Enable => ( 0 ), ApbSlot14Enable => ( 0 ), ApbSlot15Enable => ( 0 ) ) port map( -- Inputs PWRITE => CoreAHB2APB_0_APBmaster_PWRITE, PENABLE => CoreAHB2APB_0_APBmaster_PENABLE, PADDR => CoreAHB2APB_0_APBmaster_PADDR, PWDATA => CoreAHB2APB_0_APBmaster_PWDATA, PSELECT => CoreAHB2APB_0_APBmaster_PSELx, PRDATAS0 => CoreAPB_0_APBmslave0_PRDATA_0, PRDATAS1 => PRDATAS1_const_net_0, -- tied to X"0" from definition PRDATAS2 => PRDATAS2_const_net_0, -- tied to X"0" from definition PRDATAS3 => PRDATAS3_const_net_0, -- tied to X"0" from definition PRDATAS4 => PRDATAS4_const_net_0, -- tied to X"0" from definition PRDATAS5 => PRDATAS5_const_net_0, -- tied to X"0" from definition PRDATAS6 => PRDATAS6_const_net_0, -- tied to X"0" from definition PRDATAS7 => PRDATAS7_const_net_0, -- tied to X"0" from definition PRDATAS8 => PRDATAS8_const_net_0, -- tied to X"0" from definition PRDATAS9 => PRDATAS9_const_net_0, -- tied to X"0" from definition PRDATAS10 => PRDATAS10_const_net_0, -- tied to X"0" from definition PRDATAS11 => PRDATAS11_const_net_0, -- tied to X"0" from definition PRDATAS12 => PRDATAS12_const_net_0, -- tied to X"0" from definition PRDATAS13 => PRDATAS13_const_net_0, -- tied to X"0" from definition PRDATAS14 => PRDATAS14_const_net_0, -- tied to X"0" from definition PRDATAS15 => PRDATAS15_const_net_0, -- tied to X"0" from definition -- Outputs PWRITES => CoreAPB_0_APBmslave0_PWRITE, PENABLES => CoreAPB_0_APBmslave0_PENABLE, PSELS0 => CoreAPB_0_APBmslave0_PSELx, PSELS1 => OPEN, PSELS2 => OPEN, PSELS3 => OPEN, PSELS4 => OPEN, PSELS5 => OPEN, PSELS6 => OPEN, PSELS7 => OPEN, PSELS8 => OPEN, PSELS9 => OPEN, PSELS10 => OPEN, PSELS11 => OPEN, PSELS12 => OPEN, PSELS13 => OPEN, PSELS14 => OPEN, PSELS15 => OPEN, PRDATA => CoreAHB2APB_0_APBmaster_PRDATA, PADDRS => CoreAPB_0_APBmslave0_PADDR, PWDATAS => CoreAPB_0_APBmslave0_PWDATA ); -- CoreUARTapb_0 - Actel:DirectCore:CoreUARTapb:5.6.102 CoreUARTapb_0 : top_CoreUARTapb_0_CoreUARTapb generic map( BAUD_VAL_FRCTN => ( 0 ), BAUD_VAL_FRCTN_EN => ( 0 ), BAUD_VALUE => ( 1 ), FAMILY => ( 15 ), FIXEDMODE => ( 1 ), PRG_BIT8 => ( 1 ), PRG_PARITY => ( 0 ), RX_FIFO => ( 0 ), RX_LEGACY_MODE => ( 0 ), TX_FIFO => ( 0 ) ) port map( -- Inputs PCLK => HCLK, PRESETN => HRESETn, PSEL => CoreAPB_0_APBmslave0_PSELx, PENABLE => CoreAPB_0_APBmslave0_PENABLE, PWRITE => CoreAPB_0_APBmslave0_PWRITE, RX => VCC_net, PADDR => CoreAPB_0_APBmslave0_PADDR_0, PWDATA => CoreAPB_0_APBmslave0_PWDATA_0, -- Outputs TXRDY => OPEN, RXRDY => OPEN, PARITY_ERR => OPEN, OVERFLOW => OPEN, TX => TX_net_0, PREADY => CoreAPB_0_APBmslave0_PREADY, PSLVERR => CoreAPB_0_APBmslave0_PSLVERR, FRAMING_ERR => OPEN, PRDATA => CoreAPB_0_APBmslave0_PRDATA ); end RTL;