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-- Converted from AHBMASTER_FIC.v
-- by Verilog2VHDL ver1.00(2004/05/06)  Copyright(c) S.Morioka (http://www02.so-net.ne.jp/~morioka/v2v.htm)
 
 
-- AHBMASTER_FIC.v
--`timescale 1 ns / 100 ps
-------------------------------------------------------------------------------
-- Title      : Custom AHB slave
-------------------------------------------------------------------------------
-- File       : AHBMASTER_FIC.v
-- Author     : Mir Ali
-- Company    : Microsemi Corporation
-- Device     : SmartFusion 
-- Standard   : Verilog
-- Special Notes: This is code is for refernce only. You shouldn't use it in real 
-- design as it is
-------------------------------------------------------------------------------
-- Description: This code creates an AHB-Lite master wrapper to FIC on SamrtFusion 
-- The AHB interface to Logic will initaite AMBA transaction by sending write/read signals.
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Microsemi Corporation 
--                      All rights reserved.
-------------------------------------------------------------------------------
-- Revisions  : V1.0 
-------------------------------------------------------------------------------*/
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity AHBMASTER_FIC is
	port (
		HCLK	: in  std_logic;
		HRESETn	: in  std_logic;
 
	--AHB interface to Logic
		LREAD	: in  std_logic;
		LWRITE	: in  std_logic;
		ADDR	: in  std_logic_vector(31 downto 0);
		DATAIN	: in  std_logic_vector(31 downto 0);
		DATAOUT	: out std_logic_vector(31 downto 0);
 
	-- AHB Side Interfacing with FIC 
		HADDR	: out std_logic_vector(31 downto 0);
		HTRANS	: out std_logic_vector(1 downto 0);
		HWRITE	: out std_logic;
		HSIZE	: out std_logic_vector(2 downto 0);
		HBURST	: out std_logic_vector(2 downto 0);
		HPROT	: out std_logic_vector(3 downto 0);
		HWDATA	: out std_logic_vector(31 downto 0);
 
		HRDATA	: in  std_logic_vector(31 downto 0);
		HREADY	: in  std_logic;
		HRESP	: in  std_logic_vector(1 downto 0);
 
		RESP_err	: out std_logic_vector(1 downto 0);
		ahb_busy	: out std_logic 
	);
end AHBMASTER_FIC;
 
architecture RTL of AHBMASTER_FIC is
	-- AHB FSM States
	signal ahb_fsm_current_state	: std_logic_vector(2 downto 0);
	constant Idle	: std_logic_vector(2 downto 0) := "000";
	constant Write_FIC_0	: std_logic_vector(2 downto 0) := "001";
	constant Write_FIC_1	: std_logic_vector(2 downto 0) := "010";
	constant Write_FIC_2	: std_logic_vector(2 downto 0) := "011";
	constant Read_FIC_0	: std_logic_vector(2 downto 0) := "100";
	constant Read_FIC_1	: std_logic_vector(2 downto 0) := "101";
	constant Read_FIC_2	: std_logic_vector(2 downto 0) := "110";
 
	signal HADDR_int	: std_logic_vector(31 downto 0);	--temporary hold the address
	signal HWDATA_int	: std_logic_vector(31 downto 0);	--temporary hold the data
	signal HSIZE_int	: std_logic_vector(2 downto 0);
 
	-- since the current coreahblite is 32 bit, we are using Hsize=10 (32-bit), but can be changed
 
-- WARNING(5) in line 54: Please write a signal width part in the following sentence, manually.
	constant Data_size	: std_logic_vector(7 downto 0) := x"20"; -- 32
 
begin
	RESP_err    <= HRESP;
	HBURST	    <= "000";
	HPROT	    <= "0011";
 
	HSIZE_int	<= "010";
 
--generate
--    if (Data_size == 32) begin
--        assign HSIZE_int  = 2'b10;
--    end
--    else if (Data_size == 16) begin
--        assign HSIZE_int  = 2'b01;
--    end
--    else if (Data_size ==  8) begin
--        assign HSIZE_int  = 2'b00;
--    end
--endgenerate
 
	-- FSM That Acts as Master on AHB Bus
	-- Assuming only Non-Sequential & Idle
	v2v_pr_0:process (HCLK, HRESETn)
 
	begin
		if (HRESETn = '0') then
			HADDR	<= x"00000000";
			HTRANS	<= "00";			--Idle
			HWRITE	<= '0';
			HSIZE	<= "010";			-- 32 Bit Mode
			HWDATA	<= x"00000000";
			DATAOUT	<= x"00000000";
			ahb_fsm_current_state	<= Idle;
			ahb_busy	<= '0';
		elsif (HCLK'event and HCLK = '1') then
 
 
			case (ahb_fsm_current_state) is
			when Idle =>
			--0x00
				if (LWRITE = '1') then
					ahb_fsm_current_state	<= Write_FIC_0;
					HADDR	<= ADDR;
					HADDR_int	<= ADDR;
					HWDATA_int	<= DATAIN;
					ahb_busy	<= '1';
				elsif (LREAD = '1') then
					ahb_fsm_current_state	<= Read_FIC_0;
					HADDR	<= ADDR;
					HADDR_int	<= ADDR;
					ahb_busy	<= '1';
				else
					ahb_fsm_current_state	<= Idle;
				end if;
 
 
			when Write_FIC_0 =>
			--0x01  store the address+control signals and apply to coreahblite
				HTRANS	<= "10";
				HSIZE	<= HSIZE_int;
				HWRITE	<= '1';
				ahb_fsm_current_state	<= Write_FIC_1;
				ahb_busy	<= '1';
			when Write_FIC_1 =>
			--0x02 
				if (HREADY = '0') then				        --keep the address+control signals when slave is not ready yet
					HTRANS	<= "10";
					HSIZE	<= HSIZE_int;
					HWRITE	<= '1';
					HADDR	<= HADDR_int;
					ahb_fsm_current_state	<= Write_FIC_1;
					ahb_busy	<= '1';
				else
					HWDATA	<= HWDATA_int;					--send the data+go to next state, doesn't need to keep the address+other controls active
					HADDR	<= x"00000000";
					HTRANS	<= "00";
					HWRITE	<= '0';
					ahb_fsm_current_state	<= Write_FIC_2;
					ahb_busy	<= '1';
				end if;
			when Write_FIC_2 =>
			--0x03
				if (HREADY = '0') then				        --keep the data when slave is not ready yet
					ahb_fsm_current_state	<= Write_FIC_2;
					ahb_busy	<= '1';
				else
					ahb_fsm_current_state	<= Idle;		--finish the write transfer  
					ahb_busy	<= '0';
				end if;
			when Read_FIC_0 =>
			--0x04 store the address+control signals and apply to coreahblite
				HTRANS	<= "10";
				HSIZE	<= HSIZE_int;
				HWRITE	<= '0';
				ahb_fsm_current_state	<= Read_FIC_1;
				ahb_busy	<= '1';
			when Read_FIC_1 =>
			--0x05
				if (HREADY = '1') then				        -- go to next state
					ahb_fsm_current_state	<= Read_FIC_2;
				else
					HTRANS	<= "10";					    --keep the address+control signals when slave is not ready yet
					HSIZE	<= HSIZE_int;
					HWRITE	<= '0';
					HADDR	<= HADDR_int;
					ahb_fsm_current_state	<= Read_FIC_1;
					ahb_busy	<= '1';
				end if;
			when Read_FIC_2 =>
			--0x06                         
				if (HREADY = '1') then				        --read the data+finish the read transfer 
					DATAOUT	<= HRDATA;
					ahb_fsm_current_state	<= Idle;
					ahb_busy	<= '0';
				else
					ahb_fsm_current_state	<= Read_FIC_2;	--waiting slave to be ready
					ahb_busy	<= '1';
				end if;
				HADDR	<= x"00000000";				        --doesn't need to keep the address+other controls any more
				HTRANS	<= "00";    
 
			end case;
		end if;
	end process;
 
end RTL;