URL
https://opencores.org/ocsvn/ahbmaster/ahbmaster/trunk
Subversion Repositories ahbmaster
[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [simulation/] [run.do] - Rev 3
Compare with Previous | Blame | View Log
quietly set ACTELLIBNAME ProASIC3
quietly set PROJECT_DIR "C:/Actelprj/test79_AHBmaster"
if {[file exists postsynth/_info]} {
echo "INFO: Simulation library postsynth already exists"
} else {
file delete -force postsynth
vlib postsynth
}
vmap postsynth postsynth
vmap proasic3 "C:/Microsemi/Libero_SoC_v11.8/Designer/lib/modelsim/precompiled/vhdl/proasic3"
vmap COREAHBLITE_LIB "../component/Actel/DirectCore/CoreAHBLite/5.3.101/mti/user_vhdl/COREAHBLITE_LIB"
vcom -work COREAHBLITE_LIB -force_refresh
vlog -work COREAHBLITE_LIB -force_refresh
if {[file exists COREUARTAPB_LIB/_info]} {
echo "INFO: Simulation library COREUARTAPB_LIB already exists"
} else {
file delete -force COREUARTAPB_LIB
vlib COREUARTAPB_LIB
}
vmap COREUARTAPB_LIB "COREUARTAPB_LIB"
vcom -2008 -explicit -work COREAHBLITE_LIB "${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/5.3.101/rtl/vhdl/core/coreahblite_addrdec.vhd"
vcom -2008 -explicit -work COREAHBLITE_LIB "${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/5.3.101/rtl/vhdl/core/coreahblite_pkg.vhd"
vcom -2008 -explicit -work COREAHBLITE_LIB "${PROJECT_DIR}/component/work/top/CoreAHBLite_0/rtl/vhdl/core/components.vhd"
vcom -2008 -explicit -work COREUARTAPB_LIB "${PROJECT_DIR}/component/work/top/CoreUARTapb_0/rtl/vhdl/core/components.vhd"
vcom -2008 -explicit -work COREUARTAPB_LIB "${PROJECT_DIR}/component/work/top/CoreUARTapb_0/rtl/vhdl/core/coreuart_pkg.vhd"
vcom -2008 -explicit -work postsynth "${PROJECT_DIR}/synthesis/top.vhd"
vcom -2008 -explicit -work postsynth "${PROJECT_DIR}/stimulus/tb_clk.vhd"
vcom -2008 -explicit -work postsynth "${PROJECT_DIR}/component/work/tb_top/tb_top.vhd"
vsim -L proasic3 -L postsynth -L COREAHBLITE_LIB -L COREUARTAPB_LIB -t 1ps postsynth.tb_top
add wave /tb_top/*
run 1000ns