Subversion Repositories ahbmaster

Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016
@N|Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

Synopsys VHDL Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016
@N|Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@N: CD720 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vhd2008\std.vhd":146:18:146:21|Setting time resolution to ps
@N:"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":32:7:32:19|Top entity is set to AHBMASTER_FIC.
VHDL syntax check successful!
@N: CD231 :"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vhd2008\std1164.vhd":890:16:890:17|Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000".
@N: CD630 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":32:7:32:19|Synthesizing work.ahbmaster_fic.rtl.
@W: CD274 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":118:3:118:6|Incomplete case statement - add more cases or a when others
Post processing for work.ahbmaster_fic.rtl
@A: CL282 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Feedback mux created for signal HADDR_int[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A: CL282 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Feedback mux created for signal HWDATA_int[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@W: CL190 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Optimizing register bit HTRANS(0) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Pruning register bit 0 of HTRANS(1 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N: CL201 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":106:2:106:3|Trying to extract state machine for register ahb_fsm_current_state.
Extracted state machine for register ahb_fsm_current_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sat Jun 02 22:49:57 2018

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Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016
@N|Running in 64-bit mode
@N: NF107 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":32:7:32:19|Selected library: work cell: AHBMASTER_FIC view rtl as top level
@N: NF107 :"C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd":32:7:32:19|Selected library: work cell: AHBMASTER_FIC view rtl as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sat Jun 02 22:49:57 2018

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@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Sat Jun 02 22:49:57 2018

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