Subversion Repositories ahbmaster

# Sat Jun 02 22:49:59 2018

Synopsys Microsemi Technology Pre-mapping, Version mapact, Build 1920R, Built Nov 17 2016 09:40:34
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09M-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)

@A: MF827 |No constraint file specified.
@L: C:\Actelprj\test79_AHBmaster\synthesis\AHBMASTER_FIC_scck.rpt 
Printing clock  summary report in "C:\Actelprj\test79_AHBmaster\synthesis\AHBMASTER_FIC_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)



Clock Summary
*****************

Start                  Requested     Requested     Clock        Clock                   Clock
Clock                  Frequency     Period        Type         Group                   Load 
---------------------------------------------------------------------------------------------
AHBMASTER_FIC|HCLK     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     173  
=============================================================================================

@W: MT530 :"c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd":106:2:106:3|Found inferred clock AHBMASTER_FIC|HCLK which controls 173 sequential elements including HADDR[31:0]. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file C:\Actelprj\test79_AHBmaster\synthesis\AHBMASTER_FIC.sap.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)

Encoding state machine ahb_fsm_current_state[0:6] (in view: work.AHBMASTER_FIC(rtl))
original code -> new code
   000 -> 0000001
   001 -> 0000010
   010 -> 0000100
   011 -> 0001000
   100 -> 0010000
   101 -> 0100000
   110 -> 1000000
None
None

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 109MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Jun 02 22:49:59 2018

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