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@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: FP130 |Promoting Net HRESETn_c on CLKBUF  HRESETn_pad 
@N: FP130 |Promoting Net HCLK_c on CLKBUF  HCLK_pad 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.