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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [synthesis/] [synlog/] [report/] [top_fpga_mapper_combined_clk.rpt] - Rev 3
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@S |Clock Optimization Summary#### START OF CLOCK OPTIMIZATION REPORT #####[Clock optimization not enabled1 non-gated/non-generated clock tree(s) driving 258 clock pin(s) of sequential element(s)0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)0 instances converted, 0 sequential instances remain driven by gated/generated clocks================================ Non-Gated/Non-Generated Clocks ================================Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance------------------------------------------------------------------------------------------------@K:CKID0001 HCLK port 258 CoreUARTapb_0.iPRDATA[7]================================================================================================##### END OF CLOCK OPTIMIZATION REPORT ######]