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<html><body><samp><pre> <!@TC:1527947396> #Build: Synplify Pro L-2016.09M-2, Build 065R, Nov 16 2016 #install: C:\Microsemi\Libero_SoC_v11.8\SynplifyPro #OS: Windows 8 6.2 #Hostname: H81I # Sat Jun 02 22:49:56 2018 #Implementation: synthesis <a name=compilerReport1></a>Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016</a> @N: : <!@TM:1527947397> | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. <a name=compilerReport2></a>Synopsys VHDL Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016</a> @N: : <!@TM:1527947397> | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vhd2008\std.vhd:146:18:146:22:@N:CD720:@XP_MSG">std.vhd(146)</a><!@TM:1527947397> | Setting time resolution to ps @N: : <a href="C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd:32:7:32:20:@N::@XP_MSG">AHBMASTER_FIC.vhd(32)</a><!@TM:1527947397> | Top entity is set to AHBMASTER_FIC. VHDL syntax check successful! @N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vhd2008\std1164.vhd:890:16:890:18:@N:CD231:@XP_MSG">std1164.vhd(890)</a><!@TM:1527947397> | Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000". @N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd:32:7:32:20:@N:CD630:@XP_MSG">AHBMASTER_FIC.vhd(32)</a><!@TM:1527947397> | Synthesizing work.ahbmaster_fic.rtl. <font color=#A52A2A>@W:<a href="@W:CD274:@XP_HELP">CD274</a> : <a href="C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd:118:3:118:7:@W:CD274:@XP_MSG">AHBMASTER_FIC.vhd(118)</a><!@TM:1527947397> | Incomplete case statement - add more cases or a when others</font> Post processing for work.ahbmaster_fic.rtl @A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd:106:2:106:4:@A:CL282:@XP_MSG">AHBMASTER_FIC.vhd(106)</a><!@TM:1527947397> | Feedback mux created for signal HADDR_int[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. @A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd:106:2:106:4:@A:CL282:@XP_MSG">AHBMASTER_FIC.vhd(106)</a><!@TM:1527947397> | Feedback mux created for signal HWDATA_int[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value. <font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd:106:2:106:4:@W:CL190:@XP_MSG">AHBMASTER_FIC.vhd(106)</a><!@TM:1527947397> | Optimizing register bit HTRANS(0) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font> <font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd:106:2:106:4:@W:CL260:@XP_MSG">AHBMASTER_FIC.vhd(106)</a><!@TM:1527947397> | Pruning register bit 0 of HTRANS(1 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font> @N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd:106:2:106:4:@N:CL201:@XP_MSG">AHBMASTER_FIC.vhd(106)</a><!@TM:1527947397> | Trying to extract state machine for register ahb_fsm_current_state. Extracted state machine for register ahb_fsm_current_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Sat Jun 02 22:49:57 2018 ###########################################################] <a name=compilerReport3></a>Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016</a> @N: : <!@TM:1527947397> | Running in 64-bit mode @N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd:32:7:32:20:@N:NF107:@XP_MSG">AHBMASTER_FIC.vhd(32)</a><!@TM:1527947397> | Selected library: work cell: AHBMASTER_FIC view rtl as top level @N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd:32:7:32:20:@N:NF107:@XP_MSG">AHBMASTER_FIC.vhd(32)</a><!@TM:1527947397> | Selected library: work cell: AHBMASTER_FIC view rtl as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Sat Jun 02 22:49:57 2018 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Sat Jun 02 22:49:57 2018 ###########################################################] <a name=compilerReport4></a>Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016</a> @N: : <!@TM:1527947399> | Running in 64-bit mode @N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd:32:7:32:20:@N:NF107:@XP_MSG">AHBMASTER_FIC.vhd(32)</a><!@TM:1527947399> | Selected library: work cell: AHBMASTER_FIC view rtl as top level @N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Actelprj\test79_AHBmaster\hdl\AHBMASTER_FIC.vhd:32:7:32:20:@N:NF107:@XP_MSG">AHBMASTER_FIC.vhd(32)</a><!@TM:1527947399> | Selected library: work cell: AHBMASTER_FIC view rtl as top level At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Sat Jun 02 22:49:59 2018 ###########################################################] Pre-mapping Report # Sat Jun 02 22:49:59 2018 <a name=mapperReport5></a>Synopsys Microsemi Technology Pre-mapping, Version mapact, Build 1920R, Built Nov 17 2016 09:40:34</a> Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) @A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1527947399> | No constraint file specified. Linked File: <a href="C:\Actelprj\test79_AHBmaster\synthesis\AHBMASTER_FIC_scck.rpt:@XP_FILE">AHBMASTER_FIC_scck.rpt</a> Printing clock summary report in "C:\Actelprj\test79_AHBmaster\synthesis\AHBMASTER_FIC_scck.rpt" file @N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1527947399> | Running in 64-bit mode. @N:<a href="@N:MF667:@XP_HELP">MF667</a> : <!@TM:1527947399> | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB) <a name=mapperReport6></a>Clock Summary</a> ***************** Start Requested Requested Clock Clock Clock Clock Frequency Period Type Group Load --------------------------------------------------------------------------------------------- AHBMASTER_FIC|HCLK 100.0 MHz 10.000 inferred Inferred_clkgroup_0 173 ============================================================================================= <font color=#A52A2A>@W:<a href="@W:MT530:@XP_HELP">MT530</a> : <a href="c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd:106:2:106:4:@W:MT530:@XP_MSG">ahbmaster_fic.vhd(106)</a><!@TM:1527947399> | Found inferred clock AHBMASTER_FIC|HCLK which controls 173 sequential elements including HADDR[31:0]. This clock has no specified timing constraint which may adversely impact design performance. </font> Finished Pre Mapping Phase. @N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1527947399> | Writing default property annotation file C:\Actelprj\test79_AHBmaster\synthesis\AHBMASTER_FIC.sap. Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB) Encoding state machine ahb_fsm_current_state[0:6] (in view: work.AHBMASTER_FIC(rtl)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 None None Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 109MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sat Jun 02 22:49:59 2018 ###########################################################] Map & Optimize Report # Sat Jun 02 22:50:00 2018 <a name=mapperReport7></a>Synopsys Microsemi Technology Mapper, Version mapact, Build 1920R, Built Nov 17 2016 09:40:34</a> Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) @N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1527947401> | Running in 64-bit mode. @N:<a href="@N:MF667:@XP_HELP">MF667</a> : <!@TM:1527947401> | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB) Encoding state machine ahb_fsm_current_state[0:6] (in view: work.AHBMASTER_FIC(rtl)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 <font color=#A52A2A>@W:<a href="@W:MO160:@XP_HELP">MO160</a> : <a href="c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd:106:2:106:4:@W:MO160:@XP_MSG">ahbmaster_fic.vhd(106)</a><!@TM:1527947401> | Register bit HSIZE[2] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.</font> <font color=#A52A2A>@W:<a href="@W:MO161:@XP_HELP">MO161</a> : <a href="c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd:106:2:106:4:@W:MO161:@XP_MSG">ahbmaster_fic.vhd(106)</a><!@TM:1527947401> | Register bit HSIZE[1] (in view view:work.AHBMASTER_FIC(rtl)) is always 1. To keep the instance, apply syn_preserve=1 on the instance.</font> <font color=#A52A2A>@W:<a href="@W:MO160:@XP_HELP">MO160</a> : <a href="c:\actelprj\test79_ahbmaster\hdl\ahbmaster_fic.vhd:106:2:106:4:@W:MO160:@XP_MSG">ahbmaster_fic.vhd(106)</a><!@TM:1527947401> | Register bit HSIZE[0] (in view view:work.AHBMASTER_FIC(rtl)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.</font> Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ----------------------------------------------------------------------- un1_HWDATA_0_sqmuxa_0 / Y 32 HADDR_int_0_sqmuxa / Y 32 HWDATA_int_0_sqmuxa_1 / Y 32 DATAOUT_0_sqmuxa_i / Y 32 un1_ahb_fsm_current_state_12_i / Y 32 HWDATA_1_sqmuxa_0_a4 / Y 33 v2v_pr_0.HADDR_7_sn_i0_i_i / Y 33 HRESETn_pad / Y 108 : 106 asynchronous set/reset ======================================================================= @N:<a href="@N:FP130:@XP_HELP">FP130</a> : <!@TM:1527947401> | Promoting Net HRESETn_c on CLKBUF HRESETn_pad @N:<a href="@N:FP130:@XP_HELP">FP130</a> : <!@TM:1527947401> | Promoting Net HCLK_c on CLKBUF HCLK_pad Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Replicating Combinational Instance v2v_pr_0.HADDR_7_sn_i0_i_i, fanout 33 segments 2 Replicating Combinational Instance HWDATA_1_sqmuxa_0_a4, fanout 34 segments 2 Replicating Combinational Instance un1_ahb_fsm_current_state_12_i, fanout 32 segments 2 Replicating Combinational Instance DATAOUT_0_sqmuxa_i, fanout 32 segments 2 Replicating Combinational Instance HWDATA_int_0_sqmuxa_1, fanout 32 segments 2 Replicating Combinational Instance HADDR_int_0_sqmuxa, fanout 32 segments 2 Replicating Combinational Instance un1_HWDATA_0_sqmuxa_0, fanout 32 segments 2 Added 0 Buffers Added 7 Cells via replication Added 0 Sequential Cells via replication Added 7 Combinational Cells via replication Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) @S |Clock Optimization Summary <a name=clockReport8></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a> Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 170 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- <a href="@|S:HCLK@|E:HADDR[0]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 @XP_NAMES_BY_PROP">ClockId0001 </a> HCLK port 170 HADDR[0] ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 110MB) Writing Analyst data base C:\Actelprj\test79_AHBmaster\synthesis\synwork\AHBMASTER_FIC_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Writing EDIF Netlist and constraint files L-2016.09M-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Start final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) <font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1527947401> | Found inferred clock AHBMASTER_FIC|HCLK with period 10.00ns. Please declare a user-defined clock on object "p:HCLK"</font> <a name=timingReport9></a>##### START OF TIMING REPORT #####[</a> # Timing Report written on Sat Jun 02 22:50:00 2018 # Top view: AHBMASTER_FIC Library name: PA3 Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: proasic3 Paths requested: 5 Constraint File(s): @N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1527947401> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1527947401> | Clock constraints include only register-to-register paths associated with each individual clock. <a name=performanceSummary10></a>Performance Summary</a> ******************* Worst slack in design: 0.679 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------- AHBMASTER_FIC|HCLK 100.0 MHz 107.3 MHz 10.000 9.321 0.679 inferred Inferred_clkgroup_0 ========================================================================================================================= <a name=clockRelationships11></a>Clock Relationships</a> ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------ AHBMASTER_FIC|HCLK AHBMASTER_FIC|HCLK | 10.000 0.679 | No paths - | No paths - | No paths - ============================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. <a name=interfaceInfo12></a>Interface Information </a> ********************* No IO constraint found ==================================== <a name=clockReport13></a>Detailed Report for Clock: AHBMASTER_FIC|HCLK</a> ==================================== <a name=startingSlack14></a>Starting Points with Worst Slack</a> ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------- ahb_fsm_current_state[4] AHBMASTER_FIC|HCLK DFN1C0 Q ahb_fsm_current_state[4] 0.737 0.679 ahb_fsm_current_state[1] AHBMASTER_FIC|HCLK DFN1C0 Q ahb_fsm_current_state[1] 0.737 1.401 ahb_fsm_current_state[6] AHBMASTER_FIC|HCLK DFN1P0 Q ahb_fsm_current_state[6] 0.737 1.795 ahb_fsm_current_state[2] AHBMASTER_FIC|HCLK DFN1C0 Q ahb_fsm_current_state[2] 0.737 3.104 ahb_fsm_current_state[5] AHBMASTER_FIC|HCLK DFN1C0 Q ahb_fsm_current_state[5] 0.737 3.243 ahb_fsm_current_state[0] AHBMASTER_FIC|HCLK DFN1C0 Q ahb_fsm_current_state[0] 0.737 3.551 ahb_fsm_current_state[3] AHBMASTER_FIC|HCLK DFN1C0 Q ahb_fsm_current_state[3] 0.737 3.658 HADDR_int[0] AHBMASTER_FIC|HCLK DFN1E1 Q HADDR_int[0] 0.737 6.526 HADDR_int[1] AHBMASTER_FIC|HCLK DFN1E1 Q HADDR_int[1] 0.737 6.526 HADDR_int[2] AHBMASTER_FIC|HCLK DFN1E1 Q HADDR_int[2] 0.737 6.526 ===================================================================================================================== <a name=endingSlack15></a>Ending Points with Worst Slack</a> ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------ HADDR[10] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[10] 9.461 0.679 HADDR[11] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[11] 9.461 0.679 HADDR[12] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[12] 9.461 0.679 HADDR[13] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[13] 9.461 0.679 HADDR[14] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[14] 9.461 0.679 HADDR[15] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[15] 9.461 0.679 HADDR[16] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[16] 9.461 0.679 HADDR[17] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[17] 9.461 0.679 HADDR[18] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[18] 9.461 0.679 HADDR[19] AHBMASTER_FIC|HCLK DFN1E0C0 D v2v_pr_0\.HADDR_7[19] 9.461 0.679 ====================================================================================================== <a name=worstPaths16></a>Worst Path Information</a> <a href="C:\Actelprj\test79_AHBmaster\synthesis\AHBMASTER_FIC.srr:srsfC:\Actelprj\test79_AHBmaster\synthesis\AHBMASTER_FIC.srs:fp:22948:24160:@XP_NAMES_GATE">View Worst Path in Analyst</a> *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.539 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.461 - Propagation time: 8.782 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 0.679 Number of logic level(s): 3 Starting point: ahb_fsm_current_state[4] / Q Ending point: HADDR[10] / D The start point is clocked by AHBMASTER_FIC|HCLK [rising] on pin CLK The end point is clocked by AHBMASTER_FIC|HCLK [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- ahb_fsm_current_state[4] DFN1C0 Q Out 0.737 0.737 - ahb_fsm_current_state[4] Net - - 1.639 - 8 ahb_fsm_current_state_RNIFVDD[4] NOR2B A In - 2.376 - ahb_fsm_current_state_RNIFVDD[4] NOR2B Y Out 0.514 2.890 - HWDATA_1_sqmuxa_0 Net - - 2.218 - 17 v2v_pr_0\.HADDR_7_sn_i0_i_i_0 NOR2 B In - 5.108 - v2v_pr_0\.HADDR_7_sn_i0_i_i_0 NOR2 Y Out 0.646 5.754 - N_348_0 Net - - 2.218 - 17 v2v_pr_0\.HADDR_7[10] NOR2B A In - 7.972 - v2v_pr_0\.HADDR_7[10] NOR2B Y Out 0.488 8.460 - v2v_pr_0\.HADDR_7[10] Net - - 0.322 - 1 HADDR[10] DFN1E0C0 D In - 8.782 - =================================================================================================== Total path delay (propagation time + setup) of 9.321 is 2.925(31.4%) logic and 6.396(68.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) Finished timing report (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB) -------------------------------------------------------------------------------- Target Part: A3PN250_VQFP100_STD <a name=cellReport17></a>Report for cell AHBMASTER_FIC.rtl</a> Core Cell usage: cell count area count*area AO1A 6 1.0 6.0 GND 1 0.0 0.0 MX2 33 1.0 33.0 NOR2 3 1.0 3.0 NOR2A 1 1.0 1.0 NOR2B 36 1.0 36.0 NOR3 1 1.0 1.0 NOR3A 1 1.0 1.0 NOR3B 1 1.0 1.0 NOR3C 4 1.0 4.0 OA1B 1 1.0 1.0 OAI1 1 1.0 1.0 OR2 6 1.0 6.0 OR2B 2 1.0 2.0 OR3 2 1.0 2.0 VCC 1 0.0 0.0 DFN1C0 6 1.0 6.0 DFN1E0C0 67 1.0 67.0 DFN1E1 64 1.0 64.0 DFN1E1C0 32 1.0 32.0 DFN1P0 1 1.0 1.0 ----- ---------- TOTAL 270 268.0 IO Cell usage: cell count CLKBUF 2 INBUF 101 OUTBUF 112 ----- TOTAL 215 Core Cells : 268 of 6144 (4%) IO Cells : 215 RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 24MB peak: 110MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sat Jun 02 22:50:01 2018 ###########################################################] </pre></samp></body></html>