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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [synthesis/] [top.vhd] - Rev 3
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-- Version: v11.8 SP3 11.8.3.6 library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity AHBMASTER_FIC is port( AHBMASTER_FIC_0_AHBmaster_HADDR_0 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_1 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_2 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_22 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_23 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_24 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_25 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_26 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_27 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_28 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_29 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HRDATA : in std_logic_vector(7 downto 0); DATAOUT_c : out std_logic_vector(7 downto 0); DATAIN_c : in std_logic_vector(7 downto 0); AHBMASTER_FIC_0_AHBmaster_HWDATA : out std_logic_vector(7 downto 0); AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : out std_logic; ADDR_c_29 : in std_logic; ADDR_c_23 : in std_logic; ADDR_c_26 : in std_logic; ADDR_c_22 : in std_logic; ADDR_c_24 : in std_logic; ADDR_c_25 : in std_logic; ADDR_c_27 : in std_logic; ADDR_c_1 : in std_logic; ADDR_c_0 : in std_logic; ADDR_c_28 : in std_logic; ADDR_c_2 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HWRITE : out std_logic; HCLK_c : in std_logic; ahb_busy_c : out std_logic; HRESETn_c : in std_logic; PREVDATASLAVEREADY_iv_i_0_i_o4_0 : in std_logic; N_163 : in std_logic; LWRITE_c : in std_logic; LREAD_c : in std_logic; N_398 : in std_logic; PREVDATASLAVEREADY_iv_i_0_i_o4_1 : in std_logic; N_340 : in std_logic ); end AHBMASTER_FIC; architecture DEF_ARCH of AHBMASTER_FIC is component DFN1E0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; E : in std_logic := 'U'; Q : out std_logic ); end component; component DFN1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; Q : out std_logic ); end component; component DFN1E0C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; E : in std_logic := 'U'; Q : out std_logic ); end component; component DFN1E1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; E : in std_logic := 'U'; Q : out std_logic ); end component; component AO1A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component AO1 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component OR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2B port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component AOI1 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component MX2C port( A : in std_logic := 'U'; B : in std_logic := 'U'; S : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component OR3C port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1P0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; PRE : in std_logic := 'U'; Q : out std_logic ); end component; component NOR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component OR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component OR3 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3B port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; component NOR3 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; signal \ahb_fsm_current_state_ns_i_0_2[0]\, N_125, un1_ahb_fsm_current_state_12_i_0, N_87, \ahb_fsm_current_state[5]_net_1\, \ahb_fsm_current_state[2]_net_1\, \HADDR_7_i_0[31]\, \HADDR_int[31]_net_1\, \HADDR_7_i_0[25]\, \HADDR_int[25]_net_1\, \HADDR_7_i_0[28]\, \HADDR_int[28]_net_1\, \HADDR_7_i_0[24]\, \HADDR_int[24]_net_1\, \HADDR_7_i_0[26]\, \HADDR_int[26]_net_1\, \HADDR_7_i_0[27]\, \HADDR_int[27]_net_1\, \HADDR_7_i_0[29]\, \HADDR_int[29]_net_1\, \HADDR_7_i_0[3]\, \HADDR_int[3]_net_1\, \HADDR_7_i_0[2]\, \HADDR_int[2]_net_1\, \HADDR_7_i_0[30]\, \HADDR_int[30]_net_1\, \HADDR_7_i_0[4]\, \HADDR_int[4]_net_1\, \ahb_fsm_current_state[0]_net_1\, un1_ahb_fsm_current_state_12_i_3, un1_ahb_fsm_current_state_12_i_0_a1_0, un1_ahb_fsm_current_state_12_i_2, \ahb_fsm_current_state[3]_net_1\, N_197, DATAOUT_0_sqmuxa_i_0, un1_ahb_fsm_current_state_7_i_0_0, \ahb_fsm_current_state[6]_net_1\, un1_ahb_fsm_current_state_7_i_0_a4_0_1, \ahb_fsm_current_state[1]_net_1\, N_N_3_mux, un1_ahb_fsm_current_state_8_0_2, un1_ahb_fsm_current_state_8_0_1, \ahb_fsm_current_state[4]_net_1\, HWDATA_1_sqmuxa_0_a5_0_a4_2_0, un1_ahb_fsm_current_state_12_i_0_a0_1, un1_ahb_fsm_current_state_8_0_0_a0_0, N_34, N_N_5_mux, \ahb_fsm_current_state_ns[4]\, N_74, N_188, HWDATA_1_sqmuxa, N_78, \ahb_fsm_current_state_RNO[6]_net_1\, N_89, N_582, N_26, N_583, N_30, N_581, N_580, N_369, N_129, N_32, N_76, \ahb_fsm_current_state_RNIP1UTR[1]_net_1\, \HWRITE_RNO_2\, \HWRITE_RNO_0\, un1_ahb_fsm_current_state_8, N_355, \DATAOUT_0_sqmuxa_i_0_a0\, N_91, \ahb_fsm_current_state_ns[3]\, \ahb_fsm_current_state_ns[5]\, \ahb_fsm_current_state_ns[6]\, ahb_busy_6, HWRITE_4, \ahb_fsm_current_state_RNO[5]_net_1\, N_379, N_86, N_84, \HWDATA_int[0]_net_1\, \HWDATA_int[1]_net_1\, \HWDATA_int[2]_net_1\, \HWDATA_int[3]_net_1\, \HWDATA_int[4]_net_1\, \HWDATA_int[5]_net_1\, \HWDATA_int[6]_net_1\, \HWDATA_int[7]_net_1\, \GND\, \VCC\ : std_logic; begin \HADDR_int[29]\ : DFN1E0 port map(D => ADDR_c_27, CLK => HCLK_c, E => N_86, Q => \HADDR_int[29]_net_1\); \ahb_fsm_current_state[2]\ : DFN1C0 port map(D => \ahb_fsm_current_state_ns[4]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \ahb_fsm_current_state[2]_net_1\); \DATAOUT[6]\ : DFN1E0C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HRDATA(6), CLK => HCLK_c, CLR => HRESETn_c, E => N_355, Q => DATAOUT_c(6)); \ahb_fsm_current_state[1]\ : DFN1C0 port map(D => \ahb_fsm_current_state_ns[5]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \ahb_fsm_current_state[1]_net_1\); HWRITE : DFN1E1C0 port map(D => HWRITE_4, CLK => HCLK_c, CLR => HRESETn_c, E => un1_ahb_fsm_current_state_8, Q => AHBMASTER_FIC_0_AHBmaster_HWRITE); \HADDR[4]\ : DFN1E0C0 port map(D => N_74, CLK => HCLK_c, CLR => HRESETn_c, E => \ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q => AHBMASTER_FIC_0_AHBmaster_HADDR_2); \HADDR_RNO_0[4]\ : AO1A port map(A => \HADDR_int[4]_net_1\, B => N_87, C => \ahb_fsm_current_state[0]_net_1\, Y => \HADDR_7_i_0[4]\); \ahb_fsm_current_state_RNO_1[6]\ : NOR2A port map(A => N_91, B => N_89, Y => N_125); \ahb_fsm_current_state_RNIN71O4[4]\ : NOR2A port map(A => \ahb_fsm_current_state[4]_net_1\, B => N_340, Y => HWDATA_1_sqmuxa_0_a5_0_a4_2_0); \ahb_fsm_current_state_RNO[1]\ : AO1 port map(A => \ahb_fsm_current_state[1]_net_1\, B => N_163, C => \ahb_fsm_current_state[2]_net_1\, Y => \ahb_fsm_current_state_ns[5]\); \ahb_fsm_current_state_RNI151J[3]\ : OR2 port map(A => \ahb_fsm_current_state[3]_net_1\, B => \ahb_fsm_current_state[0]_net_1\, Y => N_89); \ahb_fsm_current_state_RNO[5]\ : NOR2B port map(A => LWRITE_c, B => \ahb_fsm_current_state[6]_net_1\, Y => \ahb_fsm_current_state_RNO[5]_net_1\); \ahb_fsm_current_state_RNI2H6Q[1]\ : NOR2B port map(A => \ahb_fsm_current_state[1]_net_1\, B => N_398, Y => un1_ahb_fsm_current_state_8_0_0_a0_0); \ahb_fsm_current_state_RNO[6]\ : AOI1 port map(A => N_89, B => N_163, C => \ahb_fsm_current_state_ns_i_0_2[0]\, Y => \ahb_fsm_current_state_RNO[6]_net_1\); \HADDR[30]\ : DFN1E0C0 port map(D => N_581, CLK => HCLK_c, CLR => HRESETn_c, E => \ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q => AHBMASTER_FIC_0_AHBmaster_HADDR_28); \DATAOUT[1]\ : DFN1E0C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HRDATA(1), CLK => HCLK_c, CLR => HRESETn_c, E => N_355, Q => DATAOUT_c(1)); \ahb_fsm_current_state_RNO[3]\ : AO1 port map(A => \ahb_fsm_current_state[3]_net_1\, B => N_163, C => HWDATA_1_sqmuxa, Y => \ahb_fsm_current_state_ns[3]\); \HADDR_RNO[2]\ : NOR2A port map(A => N_N_5_mux, B => \HADDR_7_i_0[2]\, Y => N_78); \HADDR_int[27]\ : DFN1E0 port map(D => ADDR_c_25, CLK => HCLK_c, E => N_86, Q => \HADDR_int[27]_net_1\); \HADDR_int[25]\ : DFN1E0 port map(D => ADDR_c_23, CLK => HCLK_c, E => N_86, Q => \HADDR_int[25]_net_1\); \ahb_fsm_current_state_RNIKNNML[1]\ : NOR2A port map(A => un1_ahb_fsm_current_state_7_i_0_a4_0_1, B => \DATAOUT_0_sqmuxa_i_0_a0\, Y => N_129); \ahb_fsm_current_state_RNO[0]\ : AO1 port map(A => \ahb_fsm_current_state[0]_net_1\, B => N_163, C => N_129, Y => \ahb_fsm_current_state_ns[6]\); \HTRANS_1_RNO_0[1]\ : OR2 port map(A => \ahb_fsm_current_state[3]_net_1\, B => \ahb_fsm_current_state[6]_net_1\, Y => un1_ahb_fsm_current_state_7_i_0_0); \HADDR_RNO_0[27]\ : MX2C port map(A => ADDR_c_25, B => \HADDR_int[27]_net_1\, S => N_87, Y => \HADDR_7_i_0[27]\); \HWDATA_int[5]\ : DFN1E0 port map(D => DATAIN_c(5), CLK => HCLK_c, E => N_84, Q => \HWDATA_int[5]_net_1\); \ahb_fsm_current_state_RNI0AID8[1]\ : NOR3A port map(A => \ahb_fsm_current_state[1]_net_1\, B => N_340, C => PREVDATASLAVEREADY_iv_i_0_i_o4_1, Y => un1_ahb_fsm_current_state_12_i_0_a0_1); \HADDR_RNO_0[29]\ : MX2C port map(A => ADDR_c_27, B => \HADDR_int[29]_net_1\, S => N_87, Y => \HADDR_7_i_0[29]\); \DATAOUT[0]\ : DFN1E0C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HRDATA(0), CLK => HCLK_c, CLR => HRESETn_c, E => N_355, Q => DATAOUT_c(0)); \ahb_fsm_current_state_RNIP1UTR[1]\ : AO1A port map(A => PREVDATASLAVEREADY_iv_i_0_i_o4_0, B => un1_ahb_fsm_current_state_12_i_0_a0_1, C => un1_ahb_fsm_current_state_12_i_3, Y => \ahb_fsm_current_state_RNIP1UTR[1]_net_1\); VCC_i : VCC port map(Y => \VCC\); \HADDR_RNO_0[25]\ : MX2C port map(A => ADDR_c_23, B => \HADDR_int[25]_net_1\, S => N_87, Y => \HADDR_7_i_0[25]\); \HADDR[31]\ : DFN1E0C0 port map(D => N_580, CLK => HCLK_c, CLR => HRESETn_c, E => \ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q => AHBMASTER_FIC_0_AHBmaster_HADDR_29); \ahb_fsm_current_state_RNIPSK31[6]\ : OR3C port map(A => \ahb_fsm_current_state[6]_net_1\, B => HRESETn_c, C => N_91, Y => N_86); \ahb_fsm_current_state[6]\ : DFN1P0 port map(D => \ahb_fsm_current_state_RNO[6]_net_1\, CLK => HCLK_c, PRE => HRESETn_c, Q => \ahb_fsm_current_state[6]_net_1\); \ahb_fsm_current_state[0]\ : DFN1C0 port map(D => \ahb_fsm_current_state_ns[6]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \ahb_fsm_current_state[0]_net_1\); \HADDR_RNO_1[4]\ : NOR2 port map(A => ADDR_c_2, B => N_87, Y => N_188); \HADDR_RNO[24]\ : NOR2A port map(A => N_N_5_mux, B => \HADDR_7_i_0[24]\, Y => N_34); \ahb_fsm_current_state_RNI98I87[1]\ : AO1A port map(A => N_340, B => un1_ahb_fsm_current_state_12_i_0_a1_0, C => un1_ahb_fsm_current_state_12_i_2, Y => un1_ahb_fsm_current_state_12_i_3); \HTRANS_1_RNO[1]\ : OR2 port map(A => un1_ahb_fsm_current_state_7_i_0_0, B => N_129, Y => N_369); \DATAOUT[4]\ : DFN1E0C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HRDATA(4), CLK => HCLK_c, CLR => HRESETn_c, E => N_355, Q => DATAOUT_c(4)); \HADDR_int[31]\ : DFN1E0 port map(D => ADDR_c_29, CLK => HCLK_c, E => N_86, Q => \HADDR_int[31]_net_1\); \HADDR_int[26]\ : DFN1E0 port map(D => ADDR_c_24, CLK => HCLK_c, E => N_86, Q => \HADDR_int[26]_net_1\); \HWDATA[0]\ : DFN1E1C0 port map(D => \HWDATA_int[0]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, E => HWDATA_1_sqmuxa, Q => AHBMASTER_FIC_0_AHBmaster_HWDATA(0)); \HADDR_RNO_0[31]\ : MX2C port map(A => ADDR_c_29, B => \HADDR_int[31]_net_1\, S => N_87, Y => \HADDR_7_i_0[31]\); \HWDATA_int[0]\ : DFN1E0 port map(D => DATAIN_c(0), CLK => HCLK_c, E => N_84, Q => \HWDATA_int[0]_net_1\); \HWDATA[4]\ : DFN1E1C0 port map(D => \HWDATA_int[4]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, E => HWDATA_1_sqmuxa, Q => AHBMASTER_FIC_0_AHBmaster_HWDATA(4)); \HWDATA_int[1]\ : DFN1E0 port map(D => DATAIN_c(1), CLK => HCLK_c, E => N_84, Q => \HWDATA_int[1]_net_1\); \HADDR_RNO_0[3]\ : MX2C port map(A => ADDR_c_1, B => \HADDR_int[3]_net_1\, S => N_87, Y => \HADDR_7_i_0[3]\); ahb_busy_RNO : OR2A port map(A => N_89, B => N_163, Y => ahb_busy_6); \HADDR_RNO_0[2]\ : MX2C port map(A => ADDR_c_0, B => \HADDR_int[2]_net_1\, S => N_87, Y => \HADDR_7_i_0[2]\); \ahb_fsm_current_state_RNI298U8[1]\ : NOR3A port map(A => \ahb_fsm_current_state[1]_net_1\, B => N_340, C => N_N_3_mux, Y => un1_ahb_fsm_current_state_7_i_0_a4_0_1); \HADDR_RNO[29]\ : NOR2A port map(A => N_N_5_mux, B => \HADDR_7_i_0[29]\, Y => N_582); HWRITE_RNO_1 : AO1 port map(A => \ahb_fsm_current_state[1]_net_1\, B => N_340, C => un1_ahb_fsm_current_state_8_0_1, Y => un1_ahb_fsm_current_state_8_0_2); \HADDR_int[28]\ : DFN1E0 port map(D => ADDR_c_26, CLK => HCLK_c, E => N_86, Q => \HADDR_int[28]_net_1\); \ahb_fsm_current_state[3]\ : DFN1C0 port map(D => \ahb_fsm_current_state_ns[3]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \ahb_fsm_current_state[3]_net_1\); \ahb_fsm_current_state_RNIJ4RV1[3]\ : OR3 port map(A => un1_ahb_fsm_current_state_12_i_0, B => \ahb_fsm_current_state[3]_net_1\, C => N_197, Y => un1_ahb_fsm_current_state_12_i_2); \HADDR_RNO[31]\ : NOR2A port map(A => N_N_5_mux, B => \HADDR_7_i_0[31]\, Y => N_580); \HADDR[3]\ : DFN1E0C0 port map(D => N_76, CLK => HCLK_c, CLR => HRESETn_c, E => \ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q => AHBMASTER_FIC_0_AHBmaster_HADDR_1); \HADDR[24]\ : DFN1E0C0 port map(D => N_34, CLK => HCLK_c, CLR => HRESETn_c, E => \ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q => AHBMASTER_FIC_0_AHBmaster_HADDR_22); N_m1_e : NOR2B port map(A => PREVDATASLAVEREADY_iv_i_0_i_o4_1, B => N_398, Y => N_N_3_mux); HWRITE_RNO_3 : OR3 port map(A => \ahb_fsm_current_state[5]_net_1\, B => \ahb_fsm_current_state[4]_net_1\, C => \ahb_fsm_current_state[2]_net_1\, Y => un1_ahb_fsm_current_state_8_0_1); \HADDR_RNO_0[28]\ : MX2C port map(A => ADDR_c_26, B => \HADDR_int[28]_net_1\, S => N_87, Y => \HADDR_7_i_0[28]\); \HWDATA_int[7]\ : DFN1E0 port map(D => DATAIN_c(7), CLK => HCLK_c, E => N_84, Q => \HWDATA_int[7]_net_1\); \HWDATA_int[3]\ : DFN1E0 port map(D => DATAIN_c(3), CLK => HCLK_c, E => N_84, Q => \HWDATA_int[3]_net_1\); \ahb_fsm_current_state_RNO[2]\ : NOR3B port map(A => LREAD_c, B => \ahb_fsm_current_state[6]_net_1\, C => LWRITE_c, Y => \ahb_fsm_current_state_ns[4]\); \ahb_fsm_current_state_RNI2H6Q_0[1]\ : NOR2A port map(A => \ahb_fsm_current_state[1]_net_1\, B => N_398, Y => un1_ahb_fsm_current_state_12_i_0_a1_0); \HADDR_RNO[3]\ : NOR2A port map(A => N_N_5_mux, B => \HADDR_7_i_0[3]\, Y => N_76); \ahb_fsm_current_state_RNI371J[4]\ : OR2 port map(A => \ahb_fsm_current_state[1]_net_1\, B => \ahb_fsm_current_state[4]_net_1\, Y => N_87); HWRITE_RNO : OR3 port map(A => \HWRITE_RNO_0\, B => un1_ahb_fsm_current_state_8_0_2, C => \HWRITE_RNO_2\, Y => un1_ahb_fsm_current_state_8); \HADDR_RNO[27]\ : NOR2A port map(A => N_N_5_mux, B => \HADDR_7_i_0[27]\, Y => N_583); \HADDR_RNO[25]\ : NOR2A port map(A => N_N_5_mux, B => \HADDR_7_i_0[25]\, Y => N_32); \HWDATA[3]\ : DFN1E1C0 port map(D => \HWDATA_int[3]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, E => HWDATA_1_sqmuxa, Q => AHBMASTER_FIC_0_AHBmaster_HWDATA(3)); \HADDR[29]\ : DFN1E0C0 port map(D => N_582, CLK => HCLK_c, CLR => HRESETn_c, E => \ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q => AHBMASTER_FIC_0_AHBmaster_HADDR_27); \HADDR[25]\ : DFN1E0C0 port map(D => N_32, CLK => HCLK_c, CLR => HRESETn_c, E => \ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q => AHBMASTER_FIC_0_AHBmaster_HADDR_23); GND_i : GND port map(Y => \GND\); \ahb_fsm_current_state[5]\ : DFN1C0 port map(D => \ahb_fsm_current_state_RNO[5]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, Q => \ahb_fsm_current_state[5]_net_1\); \ahb_fsm_current_state_RNITLON[6]\ : OR3C port map(A => \ahb_fsm_current_state[6]_net_1\, B => HRESETn_c, C => LWRITE_c, Y => N_84); HWRITE_RNO_0 : NOR2B port map(A => un1_ahb_fsm_current_state_8_0_0_a0_0, B => PREVDATASLAVEREADY_iv_i_0_i_o4_1, Y => \HWRITE_RNO_0\); \ahb_fsm_current_state[4]\ : DFN1C0 port map(D => HWRITE_4, CLK => HCLK_c, CLR => HRESETn_c, Q => \ahb_fsm_current_state[4]_net_1\); \HWDATA[5]\ : DFN1E1C0 port map(D => \HWDATA_int[5]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, E => HWDATA_1_sqmuxa, Q => AHBMASTER_FIC_0_AHBmaster_HWDATA(5)); \HADDR[27]\ : DFN1E0C0 port map(D => N_583, CLK => HCLK_c, CLR => HRESETn_c, E => \ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q => AHBMASTER_FIC_0_AHBmaster_HADDR_25); \HADDR_int[3]\ : DFN1E0 port map(D => ADDR_c_1, CLK => HCLK_c, E => N_86, Q => \HADDR_int[3]_net_1\); \HADDR_int[2]\ : DFN1E0 port map(D => ADDR_c_0, CLK => HCLK_c, E => N_86, Q => \HADDR_int[2]_net_1\); \HADDR[26]\ : DFN1E0C0 port map(D => N_30, CLK => HCLK_c, CLR => HRESETn_c, E => \ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q => AHBMASTER_FIC_0_AHBmaster_HADDR_24); \ahb_fsm_current_state_RNIPHIFL[5]\ : AO1 port map(A => \ahb_fsm_current_state[4]_net_1\, B => N_163, C => \ahb_fsm_current_state[5]_net_1\, Y => HWRITE_4); \ahb_fsm_current_state_RNIJ31O4[0]\ : OR2A port map(A => \ahb_fsm_current_state[0]_net_1\, B => N_340, Y => DATAOUT_0_sqmuxa_i_0); DATAOUT_0_sqmuxa_i_0_a0 : NOR2B port map(A => N_398, B => PREVDATASLAVEREADY_iv_i_0_i_o4_0, Y => \DATAOUT_0_sqmuxa_i_0_a0\); \HADDR[28]\ : DFN1E0C0 port map(D => N_26, CLK => HCLK_c, CLR => HRESETn_c, E => \ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q => AHBMASTER_FIC_0_AHBmaster_HADDR_26); \ahb_fsm_current_state_RNINQNML[4]\ : NOR3A port map(A => HWDATA_1_sqmuxa_0_a5_0_a4_2_0, B => \DATAOUT_0_sqmuxa_i_0_a0\, C => N_N_3_mux, Y => HWDATA_1_sqmuxa); \DATAOUT[3]\ : DFN1E0C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HRDATA(3), CLK => HCLK_c, CLR => HRESETn_c, E => N_355, Q => DATAOUT_c(3)); \HWDATA[7]\ : DFN1E1C0 port map(D => \HWDATA_int[7]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, E => HWDATA_1_sqmuxa, Q => AHBMASTER_FIC_0_AHBmaster_HWDATA(7)); \HADDR_RNO[26]\ : NOR2A port map(A => N_N_5_mux, B => \HADDR_7_i_0[26]\, Y => N_30); \ahb_fsm_current_state_RNIMB80M[0]\ : NOR2 port map(A => \ahb_fsm_current_state[0]_net_1\, B => HWDATA_1_sqmuxa, Y => N_N_5_mux); \DATAOUT[7]\ : DFN1E0C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HRDATA(7), CLK => HCLK_c, CLR => HRESETn_c, E => N_355, Q => DATAOUT_c(7)); \HWDATA[1]\ : DFN1E1C0 port map(D => \HWDATA_int[1]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, E => HWDATA_1_sqmuxa, Q => AHBMASTER_FIC_0_AHBmaster_HWDATA(1)); \HADDR_RNO_0[24]\ : MX2C port map(A => ADDR_c_22, B => \HADDR_int[24]_net_1\, S => N_87, Y => \HADDR_7_i_0[24]\); \HADDR_int[30]\ : DFN1E0 port map(D => ADDR_c_28, CLK => HCLK_c, E => N_86, Q => \HADDR_int[30]_net_1\); \HWDATA[6]\ : DFN1E1C0 port map(D => \HWDATA_int[6]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, E => HWDATA_1_sqmuxa, Q => AHBMASTER_FIC_0_AHBmaster_HWDATA(6)); \ahb_fsm_current_state_RNO_0[6]\ : OR3 port map(A => N_125, B => un1_ahb_fsm_current_state_12_i_0, C => N_87, Y => \ahb_fsm_current_state_ns_i_0_2[0]\); \HTRANS_1[1]\ : DFN1E0C0 port map(D => N_N_5_mux, CLK => HCLK_c, CLR => HRESETn_c, E => N_369, Q => AHBMASTER_FIC_0_AHBmaster_HTRANS_0); \HADDR_RNO[4]\ : NOR3 port map(A => \HADDR_7_i_0[4]\, B => N_188, C => HWDATA_1_sqmuxa, Y => N_74); \DATAOUT[2]\ : DFN1E0C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HRDATA(2), CLK => HCLK_c, CLR => HRESETn_c, E => N_355, Q => DATAOUT_c(2)); \ahb_fsm_current_state_RNI591J[2]\ : OR2 port map(A => \ahb_fsm_current_state[5]_net_1\, B => \ahb_fsm_current_state[2]_net_1\, Y => un1_ahb_fsm_current_state_12_i_0); \ahb_fsm_current_state_ns_i_0_o3_0[0]\ : OR2 port map(A => LREAD_c, B => LWRITE_c, Y => N_91); \HWDATA[2]\ : DFN1E1C0 port map(D => \HWDATA_int[2]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, E => HWDATA_1_sqmuxa, Q => AHBMASTER_FIC_0_AHBmaster_HWDATA(2)); \HADDR_RNO[28]\ : NOR2A port map(A => N_N_5_mux, B => \HADDR_7_i_0[28]\, Y => N_26); \DATAOUT[5]\ : DFN1E0C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HRDATA(5), CLK => HCLK_c, CLR => HRESETn_c, E => N_355, Q => DATAOUT_c(5)); ahb_busy : DFN1E0C0 port map(D => ahb_busy_6, CLK => HCLK_c, CLR => HRESETn_c, E => N_379, Q => ahb_busy_c); HWRITE_RNO_2 : NOR2B port map(A => un1_ahb_fsm_current_state_8_0_0_a0_0, B => PREVDATASLAVEREADY_iv_i_0_i_o4_0, Y => \HWRITE_RNO_2\); \HADDR_int[24]\ : DFN1E0 port map(D => ADDR_c_22, CLK => HCLK_c, E => N_86, Q => \HADDR_int[24]_net_1\); \HADDR_RNO_0[26]\ : MX2C port map(A => ADDR_c_24, B => \HADDR_int[26]_net_1\, S => N_87, Y => \HADDR_7_i_0[26]\); \HADDR_RNO[30]\ : NOR2A port map(A => N_N_5_mux, B => \HADDR_7_i_0[30]\, Y => N_581); \ahb_fsm_current_state_RNIC7931[6]\ : NOR2A port map(A => \ahb_fsm_current_state[6]_net_1\, B => N_91, Y => N_197); ahb_busy_RNO_0 : OR2 port map(A => N_197, B => N_129, Y => N_379); \HADDR_RNO_0[30]\ : MX2C port map(A => ADDR_c_28, B => \HADDR_int[30]_net_1\, S => N_87, Y => \HADDR_7_i_0[30]\); \HADDR[2]\ : DFN1E0C0 port map(D => N_78, CLK => HCLK_c, CLR => HRESETn_c, E => \ahb_fsm_current_state_RNIP1UTR[1]_net_1\, Q => AHBMASTER_FIC_0_AHBmaster_HADDR_0); \HWDATA_int[6]\ : DFN1E0 port map(D => DATAIN_c(6), CLK => HCLK_c, E => N_84, Q => \HWDATA_int[6]_net_1\); \HWDATA_int[4]\ : DFN1E0 port map(D => DATAIN_c(4), CLK => HCLK_c, E => N_84, Q => \HWDATA_int[4]_net_1\); \HADDR_int[4]\ : DFN1E0 port map(D => ADDR_c_2, CLK => HCLK_c, E => N_86, Q => \HADDR_int[4]_net_1\); \ahb_fsm_current_state_RNIJMNML[0]\ : OR3 port map(A => N_N_3_mux, B => DATAOUT_0_sqmuxa_i_0, C => \DATAOUT_0_sqmuxa_i_0_a0\, Y => N_355); \HWDATA_int[2]\ : DFN1E0 port map(D => DATAIN_c(2), CLK => HCLK_c, E => N_84, Q => \HWDATA_int[2]_net_1\); end DEF_ARCH; library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity COReAPB_l is port( CoreAHB2APB_0_APBmaster_PSELx : in std_logic_vector(15 downto 1); PRDATA_0_sqmuxa_0_a2_12 : out std_logic; CoreAPB_0_APBmslave0_PSELx : in std_logic; PRDATA_0_sqmuxa_0_a2_13 : out std_logic ); end COReAPB_l; architecture DEF_ARCH of COReAPB_l is component NOR3A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3C port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; component NOR3 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; signal \PRDATA_0_sqmuxa_0_a2_7\, \PRDATA_0_sqmuxa_0_a2_10\, \PRDATA_0_sqmuxa_0_a2_2\, \PRDATA_0_sqmuxa_0_a2_1\, \PRDATA_0_sqmuxa_0_a2_9\, \PRDATA_0_sqmuxa_0_a2_6\, \PRDATA_0_sqmuxa_0_a2_4\, \GND\, \VCC\ : std_logic; begin PRDATA_0_sqmuxa_0_a2_10 : NOR3A port map(A => \PRDATA_0_sqmuxa_0_a2_6\, B => CoreAHB2APB_0_APBmaster_PSELx(3), C => CoreAHB2APB_0_APBmaster_PSELx(2), Y => \PRDATA_0_sqmuxa_0_a2_10\); PRDATA_0_sqmuxa_0_a2_9 : NOR3A port map(A => \PRDATA_0_sqmuxa_0_a2_4\, B => CoreAHB2APB_0_APBmaster_PSELx(5), C => CoreAHB2APB_0_APBmaster_PSELx(9), Y => \PRDATA_0_sqmuxa_0_a2_9\); PRDATA_0_sqmuxa_0_a2_6 : NOR2 port map(A => CoreAHB2APB_0_APBmaster_PSELx(1), B => CoreAHB2APB_0_APBmaster_PSELx(12), Y => \PRDATA_0_sqmuxa_0_a2_6\); PRDATA_0_sqmuxa_0_a2_2 : NOR2 port map(A => CoreAHB2APB_0_APBmaster_PSELx(11), B => CoreAHB2APB_0_APBmaster_PSELx(7), Y => \PRDATA_0_sqmuxa_0_a2_2\); \PRDATA_0_sqmuxa_0_a2_12\ : NOR3C port map(A => \PRDATA_0_sqmuxa_0_a2_2\, B => \PRDATA_0_sqmuxa_0_a2_1\, C => \PRDATA_0_sqmuxa_0_a2_9\, Y => PRDATA_0_sqmuxa_0_a2_12); PRDATA_0_sqmuxa_0_a2_1 : NOR2 port map(A => CoreAHB2APB_0_APBmaster_PSELx(15), B => CoreAHB2APB_0_APBmaster_PSELx(8), Y => \PRDATA_0_sqmuxa_0_a2_1\); VCC_i : VCC port map(Y => \VCC\); \PRDATA_0_sqmuxa_0_a2_13\ : NOR3C port map(A => \PRDATA_0_sqmuxa_0_a2_7\, B => CoreAPB_0_APBmslave0_PSELx, C => \PRDATA_0_sqmuxa_0_a2_10\, Y => PRDATA_0_sqmuxa_0_a2_13); GND_i : GND port map(Y => \GND\); PRDATA_0_sqmuxa_0_a2_7 : NOR3 port map(A => CoreAHB2APB_0_APBmaster_PSELx(13), B => CoreAHB2APB_0_APBmaster_PSELx(10), C => CoreAHB2APB_0_APBmaster_PSELx(14), Y => \PRDATA_0_sqmuxa_0_a2_7\); PRDATA_0_sqmuxa_0_a2_4 : NOR2 port map(A => CoreAHB2APB_0_APBmaster_PSELx(6), B => CoreAHB2APB_0_APBmaster_PSELx(4), Y => \PRDATA_0_sqmuxa_0_a2_4\); end DEF_ARCH; library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity COREAPB is port( CoreAHB2APB_0_APBmaster_PSELx : in std_logic_vector(15 downto 1); PRDATA_0_sqmuxa_0_a2_13 : out std_logic; CoreAPB_0_APBmslave0_PSELx : in std_logic; PRDATA_0_sqmuxa_0_a2_12 : out std_logic ); end COREAPB; architecture DEF_ARCH of COREAPB is component COReAPB_l port( CoreAHB2APB_0_APBmaster_PSELx : in std_logic_vector(15 downto 1) := (others => 'U'); PRDATA_0_sqmuxa_0_a2_12 : out std_logic; CoreAPB_0_APBmslave0_PSELx : in std_logic := 'U'; PRDATA_0_sqmuxa_0_a2_13 : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; signal \GND\, \VCC\ : std_logic; for all : COReAPB_l Use entity work.COReAPB_l(DEF_ARCH); begin COREAPB_oi0 : COReAPB_l port map(CoreAHB2APB_0_APBmaster_PSELx(15) => CoreAHB2APB_0_APBmaster_PSELx(15), CoreAHB2APB_0_APBmaster_PSELx(14) => CoreAHB2APB_0_APBmaster_PSELx(14), CoreAHB2APB_0_APBmaster_PSELx(13) => CoreAHB2APB_0_APBmaster_PSELx(13), CoreAHB2APB_0_APBmaster_PSELx(12) => CoreAHB2APB_0_APBmaster_PSELx(12), CoreAHB2APB_0_APBmaster_PSELx(11) => CoreAHB2APB_0_APBmaster_PSELx(11), CoreAHB2APB_0_APBmaster_PSELx(10) => CoreAHB2APB_0_APBmaster_PSELx(10), CoreAHB2APB_0_APBmaster_PSELx(9) => CoreAHB2APB_0_APBmaster_PSELx(9), CoreAHB2APB_0_APBmaster_PSELx(8) => CoreAHB2APB_0_APBmaster_PSELx(8), CoreAHB2APB_0_APBmaster_PSELx(7) => CoreAHB2APB_0_APBmaster_PSELx(7), CoreAHB2APB_0_APBmaster_PSELx(6) => CoreAHB2APB_0_APBmaster_PSELx(6), CoreAHB2APB_0_APBmaster_PSELx(5) => CoreAHB2APB_0_APBmaster_PSELx(5), CoreAHB2APB_0_APBmaster_PSELx(4) => CoreAHB2APB_0_APBmaster_PSELx(4), CoreAHB2APB_0_APBmaster_PSELx(3) => CoreAHB2APB_0_APBmaster_PSELx(3), CoreAHB2APB_0_APBmaster_PSELx(2) => CoreAHB2APB_0_APBmaster_PSELx(2), CoreAHB2APB_0_APBmaster_PSELx(1) => CoreAHB2APB_0_APBmaster_PSELx(1), PRDATA_0_sqmuxa_0_a2_12 => PRDATA_0_sqmuxa_0_a2_12, CoreAPB_0_APBmslave0_PSELx => CoreAPB_0_APBmslave0_PSELx, PRDATA_0_sqmuxa_0_a2_13 => PRDATA_0_sqmuxa_0_a2_13); VCC_i : VCC port map(Y => \VCC\); GND_i : GND port map(Y => \GND\); end DEF_ARCH; library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity COREAHBLITE_SLAVEARBITER_0 is port( arbRegSMCurrentState_i_0_3 : out std_logic; arbRegSMCurrentState_i_0_0 : out std_logic; masterAddrInProg : out std_logic_vector(3 downto 1); masterAddrInProg_i_1_0 : out std_logic; arbRegSMCurrentState_RNICAHF7_0 : out std_logic; xhdl1221_0 : in std_logic; HRESETn_c : in std_logic; HCLK_c : in std_logic; N_300 : in std_logic; N_18 : out std_logic; N_326 : in std_logic; N_135 : out std_logic; N_301 : in std_logic; N_20 : out std_logic; N_302 : in std_logic; N_22 : out std_logic; N_323 : in std_logic; N_120 : out std_logic; N_322 : in std_logic; N_324 : in std_logic; N_325 : in std_logic; N_124 : out std_logic; HADDR_26_0_a3_i_a0_3 : in std_logic; N_128 : out std_logic; un4_m5_0_a3_2 : in std_logic; HADDR_24_0_a3_i_out : out std_logic; HTRANS_0_a3_i_a2_2_0 : in std_logic; HTRANS_0_a3_i_a2_0_a0_1 : in std_logic; N_363 : out std_logic; CoreAHBLite_0_AHBmslave0_HSELx : out std_logic; un1_N_11_mux_i_5_a1_1 : in std_logic; N_403 : in std_logic; N_367 : out std_logic; un1_m1_e_0_0 : in std_logic; HADDR_m5_0_m3 : in std_logic; HSEL_1_0_0_a1_0 : in std_logic; HSEL_1_0_0_a0_0 : in std_logic; N_254 : in std_logic; N_263 : out std_logic; N_171 : out std_logic; N_330 : in std_logic; HSEL_1_0_0_1_0 : in std_logic; N_397 : in std_logic; N_327 : in std_logic; un4_m5_0_a3_1 : in std_logic; CoreAHBLite_0_AHBmslave0_HREADY : in std_logic ); end COREAHBLITE_SLAVEARBITER_0; architecture DEF_ARCH of COREAHBLITE_SLAVEARBITER_0 is component NOR2B port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1P0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; PRE : in std_logic := 'U'; Q : out std_logic ); end component; component OA1C port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component AO1A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3B port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; Q : out std_logic ); end component; component NOR3C port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component OR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component OR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component OA1A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component AO1 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component OA1 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; component AO1C port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component AO1B port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component OR3 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component AOI1B port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component MIN3X port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; signal \arbRegSMCurrentState_ns_i_a2_1[1]\, \arbRegSMCurrentState_i_0[14]\, \arbRegSMCurrentState_i_0[13]\, \arbRegSMCurrentState_i_0[15]\, \arbRegSMCurrentState_ns_i_a2_0_0[1]\, HSEL_1_0_4, HSEL_1_0_0_a0_4, HSEL_1_0_2, HSEL_1_0_3, HSEL_1_0_0, \arbRegSMCurrentState_RNIAS4K1_0[0]_net_1\, \arbRegSMCurrentState_RNIJM9G2[0]_net_1\, HSEL_1_0_0_a4_0, HSEL_1_0_0_a7_0, HSEL_1_0_0_0_tz, HADDR_26_0_a3_i_a0_2, \N_171\, HADDR_26_0_a3_i_out, HADDR_27_0_a3_i_a0_2, HADDR_27_0_a3_i_out, \N_263\, HSEL_1_0_0_a0_1, HSEL_1_0_0_a1_2, HADDR_m5_0_a3_1, \arbRegSMCurrentState_ns_i_a2_0_0[0]\, \arbRegSMCurrentState[2]_net_1\, N_156, N_172, N_171_1, \arbRegSMCurrentState_RNIG8815[14]_net_1\, \arbRegSMCurrentState_RNIB4DT5[0]_net_1\, \HADDR_24_0_a3_i_out\, \masterAddrInProg_i_1[0]\, \arbRegSMCurrentState_RNI289E2[0]_net_1\, \arbRegSMCurrentState_RNI069E2[0]_net_1\, \masterAddrInProg[3]\, \masterAddrInProg[2]\, \masterAddrInProg[1]\, \arbRegSMCurrentState_RNO[15]_net_1\, N_152, \arbRegSMCurrentState_RNO[14]_net_1\, N_153, \arbRegSMCurrentState_RNO[13]_net_1\, \arbRegSMCurrentState_i_0[12]\, \arbRegSMCurrentState_RNO[12]_net_1\, \arbRegSMCurrentState[6]_net_1\, \arbRegSMCurrentState[10]_net_1\, \arbRegSMCurrentState_ns[5]\, \arbRegSMCurrentState[9]_net_1\, \arbRegSMCurrentState_ns[9]\, \arbRegSMCurrentState[5]_net_1\, \arbRegSMCurrentState_ns[13]\, \arbRegSMCurrentState[1]_net_1\, \arbRegSMCurrentState_RNO[5]_net_1\, \arbRegSMCurrentState_RNO[4]_net_1\, \arbRegSMCurrentState_RNO[1]_net_1\, \arbRegSMCurrentState_RNO[0]_net_1\, \arbRegSMCurrentState_RNO[9]_net_1\, \arbRegSMCurrentState_RNO[8]_net_1\, \GND\, \VCC\ : std_logic; begin arbRegSMCurrentState_i_0_3 <= \arbRegSMCurrentState_i_0[15]\; arbRegSMCurrentState_i_0_0 <= \arbRegSMCurrentState_i_0[12]\; masterAddrInProg(3) <= \masterAddrInProg[3]\; masterAddrInProg(2) <= \masterAddrInProg[2]\; masterAddrInProg(1) <= \masterAddrInProg[1]\; masterAddrInProg_i_1_0 <= \masterAddrInProg_i_1[0]\; HADDR_24_0_a3_i_out <= \HADDR_24_0_a3_i_out\; N_263 <= \N_263\; N_171 <= \N_171\; \arbRegSMCurrentState_RNO[1]\ : NOR2B port map(A => \masterAddrInProg[3]\, B => CoreAHBLite_0_AHBmslave0_HREADY, Y => \arbRegSMCurrentState_RNO[1]_net_1\); \arbRegSMCurrentState[12]\ : DFN1P0 port map(D => \arbRegSMCurrentState_RNO[12]_net_1\, CLK => HCLK_c, PRE => HRESETn_c, Q => \arbRegSMCurrentState_i_0[12]\); \arbRegSMCurrentState_RNICAHF7[0]\ : OA1C port map(A => un1_m1_e_0_0, B => \arbRegSMCurrentState_RNIG8815[14]_net_1\, C => \HADDR_24_0_a3_i_out\, Y => arbRegSMCurrentState_RNICAHF7_0); \arbRegSMCurrentState_RNO[2]\ : AO1A port map(A => xhdl1221_0, B => \arbRegSMCurrentState[2]_net_1\, C => \arbRegSMCurrentState[1]_net_1\, Y => \arbRegSMCurrentState_ns[13]\); \arbRegSMCurrentState_RNIR8JU2[0]\ : NOR3B port map(A => HSEL_1_0_0_a1_0, B => \N_263\, C => \N_171\, Y => HSEL_1_0_0_a1_2); \arbRegSMCurrentState[8]\ : DFN1C0 port map(D => \arbRegSMCurrentState_RNO[8]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, Q => \masterAddrInProg[1]\); \arbRegSMCurrentState[10]\ : DFN1C0 port map(D => \arbRegSMCurrentState_ns[5]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \arbRegSMCurrentState[10]_net_1\); \arbRegSMCurrentState_RNO_4[14]\ : NOR3C port map(A => \arbRegSMCurrentState_i_0[14]\, B => \arbRegSMCurrentState_i_0[13]\, C => \arbRegSMCurrentState_i_0[15]\, Y => \arbRegSMCurrentState_ns_i_a2_1[1]\); \arbRegSMCurrentState_RNI069E2[0]\ : NOR2 port map(A => HADDR_26_0_a3_i_out, B => un1_m1_e_0_0, Y => \arbRegSMCurrentState_RNI069E2[0]_net_1\); \arbRegSMCurrentState_RNO_0[15]\ : OR2A port map(A => xhdl1221_0, B => \N_171\, Y => N_152); \arbRegSMCurrentState_RNIQQIS2[14]\ : NOR3A port map(A => HADDR_m5_0_m3, B => \N_171\, C => N_327, Y => HADDR_m5_0_a3_1); \arbRegSMCurrentState_RNIECHF7[0]\ : NOR3A port map(A => \masterAddrInProg_i_1[0]\, B => N_323, C => \N_263\, Y => N_120); \arbRegSMCurrentState_RNI289E2[0]\ : NOR2 port map(A => HADDR_27_0_a3_i_out, B => un1_m1_e_0_0, Y => \arbRegSMCurrentState_RNI289E2[0]_net_1\); \arbRegSMCurrentState_RNO_0[14]\ : NOR2A port map(A => \arbRegSMCurrentState_i_0[13]\, B => CoreAHBLite_0_AHBmslave0_HREADY, Y => \arbRegSMCurrentState_ns_i_a2_0_0[1]\); VCC_i : VCC port map(Y => \VCC\); \arbRegSMCurrentState_RNINQPT1[0]\ : OR2 port map(A => \N_263\, B => N_325, Y => HADDR_27_0_a3_i_out); \arbRegSMCurrentState_RNO_2[14]\ : OA1A port map(A => xhdl1221_0, B => N_172, C => \arbRegSMCurrentState_ns_i_a2_1[1]\, Y => N_156); \arbRegSMCurrentState_RNIJM9G2[0]\ : NOR2A port map(A => HSEL_1_0_0_a4_0, B => N_254, Y => \arbRegSMCurrentState_RNIJM9G2[0]_net_1\); \arbRegSMCurrentState_RNILM274[0]\ : AO1A port map(A => HSEL_1_0_0_a7_0, B => HSEL_1_0_0_1_0, C => HSEL_1_0_0_0_tz, Y => HSEL_1_0_0); \arbRegSMCurrentState_RNITMNO1[14]\ : NOR2B port map(A => \N_171\, B => un1_m1_e_0_0, Y => HSEL_1_0_0_a7_0); \arbRegSMCurrentState_RNI9BBD9[0]\ : AO1 port map(A => HADDR_26_0_a3_i_a0_3, B => HADDR_27_0_a3_i_a0_2, C => \arbRegSMCurrentState_RNI289E2[0]_net_1\, Y => N_128); \arbRegSMCurrentState_RNI8ECA7[0]\ : NOR3A port map(A => \masterAddrInProg_i_1[0]\, B => \N_263\, C => N_302, Y => N_22); \arbRegSMCurrentState_RNO[0]\ : NOR2A port map(A => \masterAddrInProg[3]\, B => CoreAHBLite_0_AHBmslave0_HREADY, Y => \arbRegSMCurrentState_RNO[0]_net_1\); \arbRegSMCurrentState[0]\ : DFN1C0 port map(D => \arbRegSMCurrentState_RNO[0]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, Q => \masterAddrInProg[3]\); \arbRegSMCurrentState_RNI6CCA7[0]\ : NOR3A port map(A => \masterAddrInProg_i_1[0]\, B => \N_263\, C => N_301, Y => N_20); \arbRegSMCurrentState_RNO[12]\ : OR2 port map(A => \arbRegSMCurrentState_i_0[12]\, B => CoreAHBLite_0_AHBmslave0_HREADY, Y => \arbRegSMCurrentState_RNO[12]_net_1\); \arbRegSMCurrentState_RNO[15]\ : AO1 port map(A => N_152, B => \arbRegSMCurrentState_i_0[15]\, C => CoreAHBLite_0_AHBmslave0_HREADY, Y => \arbRegSMCurrentState_RNO[15]_net_1\); \arbRegSMCurrentState_RNO[8]\ : NOR2A port map(A => \masterAddrInProg[1]\, B => CoreAHBLite_0_AHBmslave0_HREADY, Y => \arbRegSMCurrentState_RNO[8]_net_1\); \arbRegSMCurrentState[14]\ : DFN1P0 port map(D => \arbRegSMCurrentState_RNO[14]_net_1\, CLK => HCLK_c, PRE => HRESETn_c, Q => \arbRegSMCurrentState_i_0[14]\); \arbRegSMCurrentState_RNIL5804[0]\ : NOR3 port map(A => N_330, B => \N_171\, C => HADDR_26_0_a3_i_out, Y => HADDR_26_0_a3_i_a0_2); \arbRegSMCurrentState[6]\ : DFN1C0 port map(D => \arbRegSMCurrentState_ns[9]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \arbRegSMCurrentState[6]_net_1\); \arbRegSMCurrentState_RNI57BD9[0]\ : AO1 port map(A => HADDR_26_0_a3_i_a0_3, B => HADDR_26_0_a3_i_a0_2, C => \arbRegSMCurrentState_RNI069E2[0]_net_1\, Y => N_124); \arbRegSMCurrentState[1]\ : DFN1C0 port map(D => \arbRegSMCurrentState_RNO[1]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, Q => \arbRegSMCurrentState[1]_net_1\); \arbRegSMCurrentState_RNO[6]\ : AO1A port map(A => xhdl1221_0, B => \arbRegSMCurrentState[6]_net_1\, C => \arbRegSMCurrentState[5]_net_1\, Y => \arbRegSMCurrentState_ns[9]\); \arbRegSMCurrentState_RNO[10]\ : AO1A port map(A => xhdl1221_0, B => \arbRegSMCurrentState[10]_net_1\, C => \arbRegSMCurrentState[9]_net_1\, Y => \arbRegSMCurrentState_ns[5]\); \arbRegSMCurrentState_RNIN7804[0]\ : NOR3 port map(A => N_330, B => \N_171\, C => HADDR_27_0_a3_i_out, Y => HADDR_27_0_a3_i_a0_2); \arbRegSMCurrentState_RNO[4]\ : NOR2A port map(A => \masterAddrInProg[2]\, B => CoreAHBLite_0_AHBmslave0_HREADY, Y => \arbRegSMCurrentState_RNO[4]_net_1\); \arbRegSMCurrentState_RNO[13]\ : OR2A port map(A => CoreAHBLite_0_AHBmslave0_HREADY, B => \arbRegSMCurrentState_i_0[12]\, Y => \arbRegSMCurrentState_RNO[13]_net_1\); \arbRegSMCurrentState_RNIDJS95[0]\ : OA1 port map(A => HTRANS_0_a3_i_a2_0_a0_1, B => \N_263\, C => HTRANS_0_a3_i_a2_2_0, Y => N_363); GND_i : GND port map(Y => \GND\); \arbRegSMCurrentState_RNO_1[14]\ : OR2 port map(A => \arbRegSMCurrentState_i_0[14]\, B => xhdl1221_0, Y => N_153); \arbRegSMCurrentState_RNIP44K[10]\ : NOR2 port map(A => \arbRegSMCurrentState[6]_net_1\, B => \arbRegSMCurrentState[10]_net_1\, Y => N_171_1); \arbRegSMCurrentState_RNIP3DR3[0]\ : NOR3C port map(A => \N_263\, B => HSEL_1_0_0_a0_1, C => N_254, Y => HSEL_1_0_0_a0_4); \arbRegSMCurrentState_RNO_3[14]\ : NOR2A port map(A => N_171_1, B => \arbRegSMCurrentState[2]_net_1\, Y => N_172); \arbRegSMCurrentState_RNO[14]\ : AO1 port map(A => \arbRegSMCurrentState_ns_i_a2_0_0[1]\, B => N_153, C => N_156, Y => \arbRegSMCurrentState_RNO[14]_net_1\); \arbRegSMCurrentState[9]\ : DFN1C0 port map(D => \arbRegSMCurrentState_RNO[9]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, Q => \arbRegSMCurrentState[9]_net_1\); \arbRegSMCurrentState[4]\ : DFN1C0 port map(D => \arbRegSMCurrentState_RNO[4]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, Q => \masterAddrInProg[2]\); \arbRegSMCurrentState[13]\ : DFN1P0 port map(D => \arbRegSMCurrentState_RNO[13]_net_1\, CLK => HCLK_c, PRE => HRESETn_c, Q => \arbRegSMCurrentState_i_0[13]\); \arbRegSMCurrentState_RNIP44K[14]\ : NOR2A port map(A => \arbRegSMCurrentState_i_0[14]\, B => \arbRegSMCurrentState[2]_net_1\, Y => \arbRegSMCurrentState_ns_i_a2_0_0[0]\); \arbRegSMCurrentState[2]\ : DFN1P0 port map(D => \arbRegSMCurrentState_ns[13]\, CLK => HCLK_c, PRE => HRESETn_c, Q => \arbRegSMCurrentState[2]_net_1\); \arbRegSMCurrentState_RNILOPT1[0]\ : OR2 port map(A => \N_263\, B => N_324, Y => HADDR_26_0_a3_i_out); \arbRegSMCurrentState_RNIHTPM3[0]\ : AO1C port map(A => N_327, B => N_397, C => HSEL_1_0_0_a4_0, Y => HSEL_1_0_2); \arbRegSMCurrentState_RNIAS4K1_0[0]\ : NOR2A port map(A => \N_263\, B => un1_m1_e_0_0, Y => \arbRegSMCurrentState_RNIAS4K1_0[0]_net_1\); \arbRegSMCurrentState_RNI4ACA7[0]\ : NOR3A port map(A => \masterAddrInProg_i_1[0]\, B => \N_263\, C => N_300, Y => N_18); \arbRegSMCurrentState_RNIAS4K1[0]\ : NOR2A port map(A => un1_m1_e_0_0, B => HSEL_1_0_0_0_tz, Y => HSEL_1_0_0_a4_0); \arbRegSMCurrentState_RNIG8815[14]\ : NOR3C port map(A => N_254, B => N_397, C => HADDR_m5_0_a3_1, Y => \arbRegSMCurrentState_RNIG8815[14]_net_1\); MASTERADDRINPROG_m2_0_a2 : AO1B port map(A => un4_m5_0_a3_2, B => un4_m5_0_a3_1, C => un1_m1_e_0_0, Y => \masterAddrInProg_i_1[0]\); \arbRegSMCurrentState_RNIVEL31[0]\ : OR3 port map(A => \masterAddrInProg[3]\, B => \masterAddrInProg[2]\, C => \masterAddrInProg[1]\, Y => \N_263\); \arbRegSMCurrentState_RNIHKPT1[0]\ : OR2 port map(A => \N_263\, B => N_322, Y => \HADDR_24_0_a3_i_out\); \arbRegSMCurrentState[5]\ : DFN1C0 port map(D => \arbRegSMCurrentState_RNO[5]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, Q => \arbRegSMCurrentState[5]_net_1\); \arbRegSMCurrentState_RNIHQIR1[14]\ : NOR2A port map(A => HSEL_1_0_0_a0_0, B => \N_171\, Y => HSEL_1_0_0_a0_1); \arbRegSMCurrentState[15]\ : DFN1P0 port map(D => \arbRegSMCurrentState_RNO[15]_net_1\, CLK => HCLK_c, PRE => HRESETn_c, Q => \arbRegSMCurrentState_i_0[15]\); \arbRegSMCurrentState_RNII9881[14]\ : NOR2B port map(A => \arbRegSMCurrentState_ns_i_a2_0_0[0]\, B => N_171_1, Y => \N_171\); \arbRegSMCurrentState_RNII9HB8[0]\ : NOR3A port map(A => HSEL_1_0_0, B => \arbRegSMCurrentState_RNIAS4K1_0[0]_net_1\, C => \arbRegSMCurrentState_RNIJM9G2[0]_net_1\, Y => HSEL_1_0_3); \arbRegSMCurrentState_RNIEGQTN[0]\ : NOR3B port map(A => HSEL_1_0_3, B => HSEL_1_0_4, C => \arbRegSMCurrentState_RNIB4DT5[0]_net_1\, Y => CoreAHBLite_0_AHBmslave0_HSELx); \arbRegSMCurrentState_RNIDJS95_0[0]\ : OA1 port map(A => N_403, B => \N_263\, C => un1_N_11_mux_i_5_a1_1, Y => N_367); \arbRegSMCurrentState_RNIB4DT5[0]\ : NOR3C port map(A => N_254, B => HSEL_1_0_0_a1_2, C => un4_m5_0_a3_1, Y => \arbRegSMCurrentState_RNIB4DT5[0]_net_1\); \arbRegSMCurrentState_RNIH2SK9[0]\ : AOI1B port map(A => HSEL_1_0_0_a0_4, B => un4_m5_0_a3_1, C => HSEL_1_0_2, Y => HSEL_1_0_4); \arbRegSMCurrentState_RNIGOLP7[0]\ : NOR3A port map(A => \masterAddrInProg_i_1[0]\, B => \N_263\, C => N_326, Y => N_135); \arbRegSMCurrentState_RNO[5]\ : NOR2B port map(A => \masterAddrInProg[2]\, B => CoreAHBLite_0_AHBmslave0_HREADY, Y => \arbRegSMCurrentState_RNO[5]_net_1\); \arbRegSMCurrentState_RNO[9]\ : NOR2B port map(A => \masterAddrInProg[1]\, B => CoreAHBLite_0_AHBmslave0_HREADY, Y => \arbRegSMCurrentState_RNO[9]_net_1\); \arbRegSMCurrentState_RNIVEL31_0[0]\ : MIN3X port map(A => \masterAddrInProg[3]\, B => \masterAddrInProg[2]\, C => \masterAddrInProg[1]\, Y => HSEL_1_0_0_0_tz); end DEF_ARCH; library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity COREAHBLITE_SLAVESTAGE_16 is port( xhdl1221_0 : in std_logic; arbRegSMCurrentState_RNICAHF7_0 : out std_logic; arbRegSMCurrentState_i_0_3 : out std_logic; arbRegSMCurrentState_i_0_0 : out std_logic; masterAddrInProg_i_1_0 : out std_logic; regHADDR_29 : in std_logic; regHADDR_22 : in std_logic; regHADDR_23 : in std_logic; regHADDR_24 : in std_logic; regHADDR_25 : in std_logic; regHADDR_2 : in std_logic; regHADDR_1 : in std_logic; regHADDR_0 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_29 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_22 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_23 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_24 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_25 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_2 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_1 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_0 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HWDATA : in std_logic_vector(7 downto 0); CoreAHBLite_0_AHBmslave0_HWDATA : out std_logic_vector(7 downto 0); AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : in std_logic; masterDataInProg_0 : out std_logic; SDATASELInt_2 : in std_logic; SDATASELInt_4 : in std_logic; SDATASELInt_0 : in std_logic; N_327 : in std_logic; N_397 : in std_logic; N_330 : in std_logic; N_171 : out std_logic; N_263 : out std_logic; N_367 : out std_logic; N_403 : in std_logic; un1_N_11_mux_i_5_a1_1 : in std_logic; CoreAHBLite_0_AHBmslave0_HSELx : out std_logic; N_363 : out std_logic; HADDR_24_0_a3_i_out : out std_logic; un4_m5_0_a3_2 : in std_logic; N_128 : out std_logic; N_124 : out std_logic; N_120 : out std_logic; N_22 : out std_logic; N_20 : out std_logic; N_135 : out std_logic; N_18 : out std_logic; CoreAHBLite_0_AHBmslave0_HREADY : in std_logic; HRESETn_c : in std_logic; HCLK_c : in std_logic; regHWRITE : in std_logic; AHBMASTER_FIC_0_AHBmaster_HWRITE : in std_logic; N_326 : out std_logic; N_323 : out std_logic; regHTRANS : in std_logic; N_389 : in std_logic; N_377 : in std_logic; N_378 : in std_logic; N_390 : in std_logic; N_379 : in std_logic; N_380 : in std_logic; HTRANS_0_a3_i_a2_3_0 : out std_logic; HTRANS_0_a3_i_a2_4_0 : out std_logic; N_392 : in std_logic; N_365_1 : out std_logic; N_365 : out std_logic; N_394 : in std_logic; N_364_1 : out std_logic; N_364 : out std_logic; N_391 : in std_logic; un1_m1_e_0_0 : in std_logic; N_393 : out std_logic; N_398 : in std_logic; masterRegAddrSel : in std_logic; un4_m5_0_a3_1 : in std_logic; N_254 : out std_logic ); end COREAHBLITE_SLAVESTAGE_16; architecture DEF_ARCH of COREAHBLITE_SLAVESTAGE_16 is component DFN1E1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; E : in std_logic := 'U'; Q : out std_logic ); end component; component MX2C port( A : in std_logic := 'U'; B : in std_logic := 'U'; S : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3C port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component NOR2B port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component OR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; component COREAHBLITE_SLAVEARBITER_0 port( arbRegSMCurrentState_i_0_3 : out std_logic; arbRegSMCurrentState_i_0_0 : out std_logic; masterAddrInProg : out std_logic_vector(3 downto 1); masterAddrInProg_i_1_0 : out std_logic; arbRegSMCurrentState_RNICAHF7_0 : out std_logic; xhdl1221_0 : in std_logic := 'U'; HRESETn_c : in std_logic := 'U'; HCLK_c : in std_logic := 'U'; N_300 : in std_logic := 'U'; N_18 : out std_logic; N_326 : in std_logic := 'U'; N_135 : out std_logic; N_301 : in std_logic := 'U'; N_20 : out std_logic; N_302 : in std_logic := 'U'; N_22 : out std_logic; N_323 : in std_logic := 'U'; N_120 : out std_logic; N_322 : in std_logic := 'U'; N_324 : in std_logic := 'U'; N_325 : in std_logic := 'U'; N_124 : out std_logic; HADDR_26_0_a3_i_a0_3 : in std_logic := 'U'; N_128 : out std_logic; un4_m5_0_a3_2 : in std_logic := 'U'; HADDR_24_0_a3_i_out : out std_logic; HTRANS_0_a3_i_a2_2_0 : in std_logic := 'U'; HTRANS_0_a3_i_a2_0_a0_1 : in std_logic := 'U'; N_363 : out std_logic; CoreAHBLite_0_AHBmslave0_HSELx : out std_logic; un1_N_11_mux_i_5_a1_1 : in std_logic := 'U'; N_403 : in std_logic := 'U'; N_367 : out std_logic; un1_m1_e_0_0 : in std_logic := 'U'; HADDR_m5_0_m3 : in std_logic := 'U'; HSEL_1_0_0_a1_0 : in std_logic := 'U'; HSEL_1_0_0_a0_0 : in std_logic := 'U'; N_254 : in std_logic := 'U'; N_263 : out std_logic; N_171 : out std_logic; N_330 : in std_logic := 'U'; HSEL_1_0_0_1_0 : in std_logic := 'U'; N_397 : in std_logic := 'U'; N_327 : in std_logic := 'U'; un4_m5_0_a3_1 : in std_logic := 'U'; CoreAHBLite_0_AHBmslave0_HREADY : in std_logic := 'U' ); end component; component MX2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; S : in std_logic := 'U'; Y : out std_logic ); end component; component XA1 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component OA1 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; signal \HADDR_26_0_a3_i_a0_3\, \N_254\, \HSEL_1_0_0_a0_0\, \HSEL_1_0_0_a1_0\, \HTRANS_0_a3_i_a2_2_0\, \N_393\, \HSEL_1_0_0_1_0\, \HSEL_1_0_0_1_tz_tz\, \HTRANS_0_a3_i_a2_0_a0_1_0\, hwdata10_1, \masterDataInProg[0]_net_1\, \masterDataInProg[3]_net_1\, hwdata10_0, \masterDataInProg[1]_net_1\, \masterDataInProg[2]_net_1\, \N_364_1\, \N_365_1\, \HTRANS_0_a3_i_a2_0_a0_1\, \HADDR_m5_0_m3\, N_322, \N_323\, N_324, N_325, N_302, N_301, \N_326\, N_300, \masterAddrInProg_i_1[0]\, \masterAddrInProg[1]\, \masterAddrInProg[2]\, \masterAddrInProg[3]\, \GND\, \VCC\ : std_logic; for all : COREAHBLITE_SLAVEARBITER_0 Use entity work.COREAHBLITE_SLAVEARBITER_0(DEF_ARCH); begin masterAddrInProg_i_1_0 <= \masterAddrInProg_i_1[0]\; masterDataInProg_0 <= \masterDataInProg[0]_net_1\; N_326 <= \N_326\; N_323 <= \N_323\; N_365_1 <= \N_365_1\; N_364_1 <= \N_364_1\; N_393 <= \N_393\; N_254 <= \N_254\; \masterDataInProg[3]\ : DFN1E1C0 port map(D => \masterAddrInProg[3]\, CLK => HCLK_c, CLR => HRESETn_c, E => CoreAHBLite_0_AHBmslave0_HREADY, Q => \masterDataInProg[3]_net_1\); HADDR_26_0_a3_i_m2 : MX2C port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_24, B => regHADDR_24, S => masterRegAddrSel, Y => N_324); \masterDataInProg_RNI6OM22[1]\ : NOR3C port map(A => hwdata10_0, B => hwdata10_1, C => AHBMASTER_FIC_0_AHBmaster_HWDATA(2), Y => CoreAHBLite_0_AHBmslave0_HWDATA(2)); \HTRANS_0_a3_i_a2_4_0\ : NOR3A port map(A => SDATASELInt_0, B => SDATASELInt_4, C => SDATASELInt_2, Y => HTRANS_0_a3_i_a2_4_0); \masterDataInProg_RNIBTM22[1]\ : NOR3C port map(A => hwdata10_0, B => hwdata10_1, C => AHBMASTER_FIC_0_AHBmaster_HWDATA(7), Y => CoreAHBLite_0_AHBmslave0_HWDATA(7)); HADDR_4_0_a3_i_m2 : MX2C port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_2, B => regHADDR_2, S => masterRegAddrSel, Y => N_302); HTRANS_m2_e_0_0 : NOR3 port map(A => SDATASELInt_4, B => SDATASELInt_2, C => SDATASELInt_0, Y => \N_393\); HTRANS_0_a3_i_a2_0_a0_1_0 : NOR2A port map(A => N_391, B => SDATASELInt_0, Y => \HTRANS_0_a3_i_a2_0_a0_1_0\); \masterDataInProg_RNI4MM22[1]\ : NOR3C port map(A => hwdata10_0, B => hwdata10_1, C => AHBMASTER_FIC_0_AHBmaster_HWDATA(0), Y => CoreAHBLite_0_AHBmslave0_HWDATA(0)); VCC_i : VCC port map(Y => \VCC\); \masterDataInProg[2]\ : DFN1E1C0 port map(D => \masterAddrInProg[2]\, CLK => HCLK_c, CLR => HRESETn_c, E => CoreAHBLite_0_AHBmslave0_HREADY, Q => \masterDataInProg[2]_net_1\); \masterDataInProg_RNI5NM22[1]\ : NOR3C port map(A => hwdata10_0, B => hwdata10_1, C => AHBMASTER_FIC_0_AHBmaster_HWDATA(1), Y => CoreAHBLite_0_AHBmslave0_HWDATA(1)); HADDR_3_0_a3_i_m2 : MX2C port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_1, B => regHADDR_1, S => masterRegAddrSel, Y => N_301); HADDR_2_0_a3_i_m2 : MX2C port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_0, B => regHADDR_0, S => masterRegAddrSel, Y => N_300); HADDR_24_0_a3_i_m2 : MX2C port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_22, B => regHADDR_22, S => masterRegAddrSel, Y => N_322); HADDR_25_0_a3_i_m2 : MX2C port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_23, B => regHADDR_23, S => masterRegAddrSel, Y => \N_323\); \HTRANS_0_a3_i_a2_3_0\ : NOR2B port map(A => N_398, B => \N_393\, Y => HTRANS_0_a3_i_a2_3_0); HWRITE_0_0_a3_i_m2 : MX2C port map(A => AHBMASTER_FIC_0_AHBmaster_HWRITE, B => regHWRITE, S => masterRegAddrSel, Y => \N_326\); \masterDataInProg[1]\ : DFN1E1C0 port map(D => \masterAddrInProg[1]\, CLK => HCLK_c, CLR => HRESETn_c, E => CoreAHBLite_0_AHBmslave0_HREADY, Q => \masterDataInProg[1]_net_1\); \masterDataInProg[0]\ : DFN1E1C0 port map(D => \masterAddrInProg_i_1[0]\, CLK => HCLK_c, CLR => HRESETn_c, E => CoreAHBLite_0_AHBmslave0_HREADY, Q => \masterDataInProg[0]_net_1\); \masterDataInProg_RNIVM5U[1]\ : NOR2 port map(A => \masterDataInProg[1]_net_1\, B => \masterDataInProg[2]_net_1\, Y => hwdata10_0); \masterDataInProg_RNI8QM22[1]\ : NOR3C port map(A => hwdata10_0, B => hwdata10_1, C => AHBMASTER_FIC_0_AHBmaster_HWDATA(4), Y => CoreAHBLite_0_AHBmslave0_HWDATA(4)); \masterDataInProg_RNIASM22[1]\ : NOR3C port map(A => hwdata10_0, B => hwdata10_1, C => AHBMASTER_FIC_0_AHBmaster_HWDATA(6), Y => CoreAHBLite_0_AHBmslave0_HWDATA(6)); HSEL_1_0_0_1_0 : OR2A port map(A => un1_m1_e_0_0, B => \HSEL_1_0_0_1_tz_tz\, Y => \HSEL_1_0_0_1_0\); GND_i : GND port map(Y => \GND\); HTRANS_0_a3_i_a2_1 : NOR3C port map(A => N_398, B => \N_364_1\, C => N_394, Y => N_364); HSEL_1_0_0_a1_0 : NOR2A port map(A => masterRegAddrSel, B => regHADDR_29, Y => \HSEL_1_0_0_a1_0\); \masterDataInProg_RNI7PM22[1]\ : NOR3C port map(A => hwdata10_0, B => hwdata10_1, C => AHBMASTER_FIC_0_AHBmaster_HWDATA(3), Y => CoreAHBLite_0_AHBmslave0_HWDATA(3)); HSEL_1_0_0_a0_0 : NOR2 port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_29, B => masterRegAddrSel, Y => \HSEL_1_0_0_a0_0\); \masterDataInProg_RNIVM5U[3]\ : NOR2A port map(A => \masterDataInProg[0]_net_1\, B => \masterDataInProg[3]_net_1\, Y => hwdata10_1); HADDR_m5_0_m3 : MX2C port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_29, B => regHADDR_29, S => masterRegAddrSel, Y => \HADDR_m5_0_m3\); HADDR_26_0_a3_i_a0_3 : NOR2B port map(A => \N_254\, B => un4_m5_0_a3_1, Y => \HADDR_26_0_a3_i_a0_3\); HTRANS_m2_e_0 : NOR3C port map(A => N_394, B => \N_365_1\, C => N_398, Y => N_365); slave_arbiter : COREAHBLITE_SLAVEARBITER_0 port map(arbRegSMCurrentState_i_0_3 => arbRegSMCurrentState_i_0_3, arbRegSMCurrentState_i_0_0 => arbRegSMCurrentState_i_0_0, masterAddrInProg(3) => \masterAddrInProg[3]\, masterAddrInProg(2) => \masterAddrInProg[2]\, masterAddrInProg(1) => \masterAddrInProg[1]\, masterAddrInProg_i_1_0 => \masterAddrInProg_i_1[0]\, arbRegSMCurrentState_RNICAHF7_0 => arbRegSMCurrentState_RNICAHF7_0, xhdl1221_0 => xhdl1221_0, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, N_300 => N_300, N_18 => N_18, N_326 => \N_326\, N_135 => N_135, N_301 => N_301, N_20 => N_20, N_302 => N_302, N_22 => N_22, N_323 => \N_323\, N_120 => N_120, N_322 => N_322, N_324 => N_324, N_325 => N_325, N_124 => N_124, HADDR_26_0_a3_i_a0_3 => \HADDR_26_0_a3_i_a0_3\, N_128 => N_128, un4_m5_0_a3_2 => un4_m5_0_a3_2, HADDR_24_0_a3_i_out => HADDR_24_0_a3_i_out, HTRANS_0_a3_i_a2_2_0 => \HTRANS_0_a3_i_a2_2_0\, HTRANS_0_a3_i_a2_0_a0_1 => \HTRANS_0_a3_i_a2_0_a0_1\, N_363 => N_363, CoreAHBLite_0_AHBmslave0_HSELx => CoreAHBLite_0_AHBmslave0_HSELx, un1_N_11_mux_i_5_a1_1 => un1_N_11_mux_i_5_a1_1, N_403 => N_403, N_367 => N_367, un1_m1_e_0_0 => un1_m1_e_0_0, HADDR_m5_0_m3 => \HADDR_m5_0_m3\, HSEL_1_0_0_a1_0 => \HSEL_1_0_0_a1_0\, HSEL_1_0_0_a0_0 => \HSEL_1_0_0_a0_0\, N_254 => \N_254\, N_263 => N_263, N_171 => N_171, N_330 => N_330, HSEL_1_0_0_1_0 => \HSEL_1_0_0_1_0\, N_397 => N_397, N_327 => N_327, un4_m5_0_a3_1 => un4_m5_0_a3_1, CoreAHBLite_0_AHBmslave0_HREADY => CoreAHBLite_0_AHBmslave0_HREADY); HTRANS_0_a3_i_a2_0_a0_1 : NOR2B port map(A => \HTRANS_0_a3_i_a2_0_a0_1_0\, B => N_392, Y => \HTRANS_0_a3_i_a2_0_a0_1\); HTRANS_0_a3_i_o4 : MX2 port map(A => AHBMASTER_FIC_0_AHBmaster_HTRANS_0, B => regHTRANS, S => masterRegAddrSel, Y => \N_254\); HTRANS_0_a3_i_a2_2_0 : XA1 port map(A => SDATASELInt_2, B => SDATASELInt_4, C => N_398, Y => \HTRANS_0_a3_i_a2_2_0\); HTRANS_0_a3_i_a2_2_1 : OA1 port map(A => N_378, B => N_377, C => N_389, Y => \N_365_1\); HADDR_27_0_a3_i_m2 : MX2C port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_25, B => regHADDR_25, S => masterRegAddrSel, Y => N_325); HTRANS_0_a3_i_a2_1_1 : OA1 port map(A => N_380, B => N_379, C => N_390, Y => \N_364_1\); HSEL_1_0_0_1_tz_tz : MX2C port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_29, B => regHADDR_29, S => masterRegAddrSel, Y => \HSEL_1_0_0_1_tz_tz\); \masterDataInProg_RNI9RM22[1]\ : NOR3C port map(A => hwdata10_0, B => hwdata10_1, C => AHBMASTER_FIC_0_AHBmaster_HWDATA(5), Y => CoreAHBLite_0_AHBmslave0_HWDATA(5)); end DEF_ARCH; library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity COREAHBLITE_DEFAULTSLAVESM_0 is port( HRESETn_c : in std_logic; HCLK_c : in std_logic; N_382 : in std_logic; N_383 : in std_logic; N_390 : in std_logic; N_389 : in std_logic; N_393 : in std_logic; N_391 : out std_logic; N_394 : out std_logic; N_392 : out std_logic; N_399 : out std_logic; defSlaveSMCurrentState : out std_logic ); end COREAHBLITE_DEFAULTSLAVESM_0; architecture DEF_ARCH of COREAHBLITE_DEFAULTSLAVESM_0 is component NOR2B port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component NOR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; component DFN1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; Q : out std_logic ); end component; signal N_28, defSlaveSMCurrentState_net_1, \N_399\, \N_392\, \N_394\, \N_391\, \GND\, \VCC\ : std_logic; begin N_391 <= \N_391\; N_394 <= \N_394\; N_392 <= \N_392\; N_399 <= \N_399\; defSlaveSMCurrentState <= defSlaveSMCurrentState_net_1; defSlaveSMNextState_i_0_a2_0 : NOR2B port map(A => \N_391\, B => N_393, Y => \N_394\); VCC_i : VCC port map(Y => \VCC\); defSlaveSMNextState_i_0_a4 : NOR2B port map(A => \N_392\, B => \N_394\, Y => \N_399\); defSlaveSMNextState_i_0_a2 : NOR2B port map(A => N_389, B => N_390, Y => \N_392\); defSlaveSMCurrentState_RNO : NOR2 port map(A => defSlaveSMCurrentState_net_1, B => \N_399\, Y => N_28); GND_i : GND port map(Y => \GND\); defSlaveSMNextState_i_0_a2_1 : NOR2B port map(A => N_383, B => N_382, Y => \N_391\); \defSlaveSMCurrentState\ : DFN1C0 port map(D => N_28, CLK => HCLK_c, CLR => HRESETn_c, Q => defSlaveSMCurrentState_net_1); end DEF_ARCH; library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity COREAHBLITE_MASTERSTAGE_1_1_0_1_0 is port( AHBMASTER_FIC_0_AHBmaster_HADDR_26 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_27 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_28 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_29 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_0 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_1 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_2 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_22 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_23 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_24 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_25 : in std_logic; regHADDR_29 : out std_logic; regHADDR_0 : out std_logic; regHADDR_1 : out std_logic; regHADDR_2 : out std_logic; regHADDR_22 : out std_logic; regHADDR_23 : out std_logic; regHADDR_24 : out std_logic; regHADDR_25 : out std_logic; masterDataInProg_0 : in std_logic; masterAddrInProg_i_1_0 : in std_logic; xhdl1221_0 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HRDATA : out std_logic_vector(7 downto 0); SDATASELInt_4 : out std_logic; SDATASELInt_2 : out std_logic; SDATASELInt_0 : out std_logic; xhdl1222_0 : out std_logic; CoreAPB_0_APBmslave0_PRDATA : in std_logic_vector(7 downto 0); AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : in std_logic; defSlaveSMCurrentState : out std_logic; AHBMASTER_FIC_0_AHBmaster_HWRITE : in std_logic; regHWRITE : out std_logic; HRESETn_c : in std_logic; HCLK_c : in std_logic; N_163 : out std_logic; CoreAHBLite_0_AHBmslave0_HREADY : in std_logic; N_254 : in std_logic; N_395 : out std_logic; N_393 : in std_logic; N_265 : out std_logic; N_390 : out std_logic; N_389 : out std_logic; N_380 : out std_logic; N_379 : out std_logic; N_378 : out std_logic; N_377 : out std_logic; N_339_c : out std_logic; N_394 : out std_logic; N_364_1 : in std_logic; N_365_1 : in std_logic; PREVDATASLAVEREADY_iv_i_0_i_o4_0 : out std_logic; N_403 : out std_logic; PREVDATASLAVEREADY_iv_i_0_i_o4_1 : out std_logic; N_392 : out std_logic; N_391 : out std_logic; PRDATA_0_sqmuxa_0_a2_13 : in std_logic; PRDATA_0_sqmuxa_0_a2_12 : in std_logic; N_327 : out std_logic; regHTRANS : out std_logic; masterRegAddrSel : out std_logic; N_340 : out std_logic; N_330 : out std_logic; N_397 : out std_logic; N_398 : in std_logic ); end COREAHBLITE_MASTERSTAGE_1_1_0_1_0; architecture DEF_ARCH of COREAHBLITE_MASTERSTAGE_1_1_0_1_0 is component NOR3B port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3C port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component XOR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1E1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; E : in std_logic := 'U'; Q : out std_logic ); end component; component NOR2B port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component OR2B port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component OA1 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component AO1 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; Q : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component MX2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; S : in std_logic := 'U'; Y : out std_logic ); end component; component OR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component XA1 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component OA1A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1E0C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; E : in std_logic := 'U'; Q : out std_logic ); end component; component MIN3X port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; component COREAHBLITE_DEFAULTSLAVESM_0 port( HRESETn_c : in std_logic := 'U'; HCLK_c : in std_logic := 'U'; N_382 : in std_logic := 'U'; N_383 : in std_logic := 'U'; N_390 : in std_logic := 'U'; N_389 : in std_logic := 'U'; N_393 : in std_logic := 'U'; N_391 : out std_logic; N_394 : out std_logic; N_392 : out std_logic; N_399 : out std_logic; defSlaveSMCurrentState : out std_logic ); end component; signal d_masterRegAddrSel_0_0_a2_3_4, \SDATASELInt_RNISKATF_0[1]_net_1\, d_masterRegAddrSel_0_0_a2_3_3, \N_397\, d_masterRegAddrSel_0_0_a2_3_2, \N_330\, d_masterRegAddrSel_0_0_a2_3_1, \N_340\, masterRegAddrSel_net_1, d_masterRegAddrSel_0_0_a2_1, d_masterRegAddrSel_0_0_a2_0, regHTRANS_net_1, \N_327\, \HRDATA_4_6_0\, \HRDATA_4_5_0\, \HRDATA_4_2_0\, \HRDATA_4_0_0\, \HRDATA_4_7_0\, \HRDATA_4_3_0\, \HRDATA_4_4_0\, \HRDATA_4_1_0\, HREADY_m2_e_0_3, HREADY_m2_e_0_1, N_255, \N_391\, HREADY_m2_e_0_0, \SDATASELInt[5]_net_1\, \SDATASELInt[3]_net_1\, \xhdl1222[0]\, \SDATASELInt[1]_net_1\, N_399, \N_392\, masterAddrClockEnable, N_279, \PREVDATASLAVEREADY_iv_i_0_i_o4_1\, \N_403\, PREVDATASLAVEREADY_iv_i_0_i_o4_1_tz, \PREVDATASLAVEREADY_iv_i_0_i_o4_0\, SADDRSEL_N_5_mux, \regHADDR[29]_net_1\, \regHADDR[30]_net_1\, SADDRSEL_N_3_mux, N_361, \PREVDATASLAVEREADY_iv_i_0_i_o4_104\, N_251, \N_394\, N_259_i, \SDATASELInt[2]_net_1\, \SDATASELInt[7]_net_1\, N_258_i, N_384, N_257_i, \SDATASELInt[6]_net_1\, \SDATASELInt[9]_net_1\, N_386, \SDATASELInt[10]_net_1\, \SDATASELInt[8]_net_1\, \SDATASELInt[11]_net_1\, \SDATASELInt[4]_net_1\, \N_389\, \N_390\, \N_265\, \SADDRSEL[14]\, \N_395\, N_408, \SADDRSEL[13]\, N_396, N_404, \SADDRSEL[12]\, \SADDRSEL[8]\, \SADDRSEL[5]\, \SADDRSEL[4]\, \SADDRSEL[1]\, \xhdl1221[0]\, d_masterRegAddrSel, \regHTRANS_RNO\, \regHADDR[28]_net_1\, \regHADDR[31]_net_1\, N_261_i, N_383, N_376, \SDATASELInt[12]_net_1\, \SDATASELInt[13]_net_1\, \SDATASELInt[14]_net_1\, \SDATASELInt[15]_net_1\, N_382, \SADDRSEL[2]\, N_405, N_329, N_328, \SDATASELInt_RNIKCEDK[0]_net_1\, N_334, \SADDRSEL[15]\, \SADDRSEL[11]\, \SADDRSEL[10]\, \SADDRSEL[9]\, \SADDRSEL[7]\, \SADDRSEL[6]\, \SADDRSEL[3]\, \GND\, \VCC\ : std_logic; for all : COREAHBLITE_DEFAULTSLAVESM_0 Use entity work.COREAHBLITE_DEFAULTSLAVESM_0(DEF_ARCH); begin regHADDR_29 <= \regHADDR[31]_net_1\; xhdl1221_0 <= \xhdl1221[0]\; SDATASELInt_4 <= \SDATASELInt[5]_net_1\; SDATASELInt_2 <= \SDATASELInt[3]_net_1\; SDATASELInt_0 <= \SDATASELInt[1]_net_1\; xhdl1222_0 <= \xhdl1222[0]\; N_395 <= \N_395\; N_265 <= \N_265\; N_390 <= \N_390\; N_389 <= \N_389\; N_394 <= \N_394\; PREVDATASLAVEREADY_iv_i_0_i_o4_0 <= \PREVDATASLAVEREADY_iv_i_0_i_o4_0\; N_403 <= \N_403\; PREVDATASLAVEREADY_iv_i_0_i_o4_1 <= \PREVDATASLAVEREADY_iv_i_0_i_o4_1\; N_392 <= \N_392\; N_391 <= \N_391\; N_327 <= \N_327\; regHTRANS <= regHTRANS_net_1; masterRegAddrSel <= masterRegAddrSel_net_1; N_340 <= \N_340\; N_330 <= \N_330\; N_397 <= \N_397\; \SDATASELInt_RNO[2]\ : NOR3B port map(A => \N_395\, B => N_405, C => \N_330\, Y => \SADDRSEL[2]\); \SDATASELInt_RNI5IBF_0[10]\ : NOR2 port map(A => \SDATASELInt[10]_net_1\, B => \SDATASELInt[8]_net_1\, Y => N_384); \SDATASELInt_RNIM05H4[12]\ : NOR3C port map(A => \N_392\, B => \N_265\, C => N_393, Y => N_361); \SDATASELInt_RNIL6TG[2]\ : XOR2 port map(A => \SDATASELInt[7]_net_1\, B => \SDATASELInt[2]_net_1\, Y => N_258_i); HRDATA_4_5_0 : NOR3C port map(A => PRDATA_0_sqmuxa_0_a2_12, B => PRDATA_0_sqmuxa_0_a2_13, C => CoreAPB_0_APBmslave0_PRDATA(5), Y => \HRDATA_4_5_0\); \regHADDR[30]\ : DFN1E1C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_28, CLK => HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q => \regHADDR[30]_net_1\); \regHADDR_RNI8HAK1[29]\ : NOR2B port map(A => N_328, B => N_329, Y => N_408); HRDATA_4_3_0 : NOR3C port map(A => PRDATA_0_sqmuxa_0_a2_12, B => PRDATA_0_sqmuxa_0_a2_13, C => CoreAPB_0_APBmslave0_PRDATA(3), Y => \HRDATA_4_3_0\); \SDATASELInt_RNO[5]\ : NOR3B port map(A => N_396, B => N_404, C => \N_330\, Y => \SADDRSEL[5]\); \SDATASELInt_RNIKIGE4[3]\ : NOR2B port map(A => HREADY_m2_e_0_3, B => \N_392\, Y => \N_340\); \regHADDR_RNI389M1[28]\ : NOR2B port map(A => N_254, B => \N_327\, Y => N_396); d_masterRegAddrSel_0_0_o4 : OR2B port map(A => masterAddrInProg_i_1_0, B => CoreAHBLite_0_AHBmslave0_HREADY, Y => N_279); PREVDATASLAVEREADY_iv_i_0_i_o4_104 : OA1 port map(A => N_365_1, B => N_364_1, C => \N_394\, Y => \PREVDATASLAVEREADY_iv_i_0_i_o4_104\); \SDATASELInt_RNI2FBF_0[11]\ : NOR2 port map(A => \SDATASELInt[11]_net_1\, B => \SDATASELInt[4]_net_1\, Y => N_386); SADDRSEL_m1_0_a2 : NOR2 port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_27, B => AHBMASTER_FIC_0_AHBmaster_HADDR_28, Y => SADDRSEL_N_3_mux); \SDATASELInt_RNO[14]\ : NOR3C port map(A => \N_330\, B => \N_395\, C => N_408, Y => \SADDRSEL[14]\); \SDATASELInt_RNISQ0N8[0]\ : NOR3C port map(A => N_399, B => \xhdl1222[0]\, C => \HRDATA_4_6_0\, Y => AHBMASTER_FIC_0_AHBmaster_HRDATA(6)); \SDATASELInt_RNII6HSK[1]\ : AO1 port map(A => N_398, B => N_251, C => \N_340\, Y => N_163); masterRegAddrSel_RNIJQ0M : NOR3A port map(A => AHBMASTER_FIC_0_AHBmaster_HTRANS_0, B => AHBMASTER_FIC_0_AHBmaster_HADDR_26, C => masterRegAddrSel_net_1, Y => d_masterRegAddrSel_0_0_a2_3_1); \masterRegAddrSel\ : DFN1C0 port map(D => d_masterRegAddrSel, CLK => HCLK_c, CLR => HRESETn_c, Q => masterRegAddrSel_net_1); \SDATASELInt_RNITR0N8[0]\ : NOR3C port map(A => N_399, B => \xhdl1222[0]\, C => \HRDATA_4_7_0\, Y => AHBMASTER_FIC_0_AHBmaster_HRDATA(7)); \regHTRANS\ : DFN1C0 port map(D => \regHTRANS_RNO\, CLK => HCLK_c, CLR => HRESETn_c, Q => regHTRANS_net_1); VCC_i : VCC port map(Y => \VCC\); \SDATASELInt_RNO[9]\ : NOR3C port map(A => \N_330\, B => N_396, C => \N_397\, Y => \SADDRSEL[9]\); \regHADDR_RNISF4Q[29]\ : MX2 port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_27, B => \regHADDR[29]_net_1\, S => masterRegAddrSel_net_1, Y => N_328); \SDATASELInt_RNIJRPD[12]\ : XOR2 port map(A => \SDATASELInt[12]_net_1\, B => \SDATASELInt[13]_net_1\, Y => N_261_i); masterRegAddrSel_RNIUUVO3 : NOR3B port map(A => \N_397\, B => \N_395\, C => \N_330\, Y => \xhdl1221[0]\); \regHADDR[29]\ : DFN1E1C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_27, CLK => HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q => \regHADDR[29]_net_1\); \regHADDR[24]\ : DFN1E1C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_22, CLK => HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q => regHADDR_22); regHTRANS_RNO : OR2 port map(A => regHTRANS_net_1, B => masterAddrClockEnable, Y => \regHTRANS_RNO\); masterRegAddrSel_RNI24877 : NOR3B port map(A => \N_397\, B => d_masterRegAddrSel_0_0_a2_3_2, C => \N_330\, Y => d_masterRegAddrSel_0_0_a2_3_3); \SDATASELInt_RNITR801[6]\ : XA1 port map(A => \SDATASELInt[6]_net_1\, B => \SDATASELInt[9]_net_1\, C => N_386, Y => N_380); \SDATASELInt_RNIQO0N8[0]\ : NOR3C port map(A => N_399, B => \xhdl1222[0]\, C => \HRDATA_4_4_0\, Y => AHBMASTER_FIC_0_AHBmaster_HRDATA(4)); \SDATASELInt_RNI5IBF[10]\ : XOR2 port map(A => \SDATASELInt[10]_net_1\, B => \SDATASELInt[8]_net_1\, Y => N_259_i); \regHADDR_RNI4AMD[29]\ : NOR2 port map(A => \regHADDR[29]_net_1\, B => \regHADDR[30]_net_1\, Y => SADDRSEL_N_5_mux); \regHADDR[28]\ : DFN1E1C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_26, CLK => HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q => \regHADDR[28]_net_1\); \SDATASELInt_RNITTUD2[3]\ : NOR3C port map(A => HREADY_m2_e_0_1, B => N_255, C => \N_391\, Y => HREADY_m2_e_0_3); \SDATASELInt_RNIGFP7C[12]\ : OR2 port map(A => N_361, B => \PREVDATASLAVEREADY_iv_i_0_i_o4_104\, Y => \PREVDATASLAVEREADY_iv_i_0_i_o4_0\); \SDATASELInt_RNIARJR[14]\ : XA1 port map(A => \SDATASELInt[15]_net_1\, B => \SDATASELInt[14]_net_1\, C => N_382, Y => N_376); \regHADDR[31]\ : DFN1E1C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_26, CLK => HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q => \regHADDR[31]_net_1\); \SDATASELInt_RNO[8]\ : NOR3C port map(A => \N_330\, B => \N_395\, C => \N_397\, Y => \SADDRSEL[8]\); masterRegAddrSel_RNI7DH45 : NOR2A port map(A => d_masterRegAddrSel_0_0_a2_3_1, B => \N_340\, Y => d_masterRegAddrSel_0_0_a2_3_2); PREVDATASLAVEREADY_iv_i_0_i_a2_17 : NOR2B port map(A => \N_391\, B => \N_392\, Y => \N_403\); masterRegAddrSel_RNI0O8LN : OA1A port map(A => N_398, B => \SDATASELInt_RNISKATF_0[1]_net_1\, C => d_masterRegAddrSel_0_0_a2_3_3, Y => d_masterRegAddrSel_0_0_a2_3_4); \regHADDR_RNIE36Q[31]\ : MX2 port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_29, B => \regHADDR[31]_net_1\, S => masterRegAddrSel_net_1, Y => \N_330\); \SDATASELInt[4]\ : DFN1E0C0 port map(D => \SADDRSEL[4]\, CLK => HCLK_c, CLR => HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q => \SDATASELInt[4]_net_1\); \regHADDR[2]\ : DFN1E1C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_0, CLK => HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q => regHADDR_0); \SDATASELInt[15]\ : DFN1E0C0 port map(D => \SADDRSEL[15]\, CLK => HCLK_c, CLR => HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q => \SDATASELInt[15]_net_1\); masterRegAddrSel_RNO_1 : NOR3B port map(A => masterRegAddrSel_net_1, B => regHTRANS_net_1, C => \N_327\, Y => d_masterRegAddrSel_0_0_a2_0); HRDATA_4_7_0 : NOR3C port map(A => PRDATA_0_sqmuxa_0_a2_12, B => PRDATA_0_sqmuxa_0_a2_13, C => CoreAPB_0_APBmslave0_PRDATA(7), Y => \HRDATA_4_7_0\); HRDATA_4_0_0 : NOR3C port map(A => PRDATA_0_sqmuxa_0_a2_12, B => PRDATA_0_sqmuxa_0_a2_13, C => CoreAPB_0_APBmslave0_PRDATA(0), Y => \HRDATA_4_0_0\); \SDATASELInt_RNO[6]\ : NOR3B port map(A => \N_395\, B => N_408, C => \N_330\, Y => \SADDRSEL[6]\); \SDATASELInt[14]\ : DFN1E0C0 port map(D => \SADDRSEL[14]\, CLK => HCLK_c, CLR => HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q => \SDATASELInt[14]_net_1\); \SDATASELInt[2]\ : DFN1E0C0 port map(D => \SADDRSEL[2]\, CLK => HCLK_c, CLR => HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q => \SDATASELInt[2]_net_1\); \regHADDR[25]\ : DFN1E1C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_23, CLK => HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q => regHADDR_23); \SDATASELInt_RNI14Q11[3]\ : NOR3A port map(A => HREADY_m2_e_0_0, B => \SDATASELInt[5]_net_1\, C => \SDATASELInt[3]_net_1\, Y => HREADY_m2_e_0_1); \SDATASELInt_RNO[3]\ : NOR3B port map(A => N_396, B => N_405, C => \N_330\, Y => \SADDRSEL[3]\); \SDATASELInt_RNIBLBP[1]\ : MIN3X port map(A => \SDATASELInt[3]_net_1\, B => \SDATASELInt[5]_net_1\, C => \SDATASELInt[1]_net_1\, Y => PREVDATASLAVEREADY_iv_i_0_i_o4_1_tz); \SDATASELInt_RNO[11]\ : NOR3C port map(A => \N_330\, B => N_396, C => N_405, Y => \SADDRSEL[11]\); \SDATASELInt_RNIQO801_0[2]\ : NOR3A port map(A => N_259_i, B => \SDATASELInt[2]_net_1\, C => \SDATASELInt[7]_net_1\, Y => N_377); HRDATA_4_2_0 : NOR3C port map(A => PRDATA_0_sqmuxa_0_a2_12, B => PRDATA_0_sqmuxa_0_a2_13, C => CoreAPB_0_APBmslave0_PRDATA(2), Y => \HRDATA_4_2_0\); \SDATASELInt_RNIC5HL3[1]\ : NOR2B port map(A => \N_403\, B => PREVDATASLAVEREADY_iv_i_0_i_o4_1_tz, Y => \PREVDATASLAVEREADY_iv_i_0_i_o4_1\); \SDATASELInt_RNINL0N8[0]\ : NOR3C port map(A => N_399, B => \xhdl1222[0]\, C => \HRDATA_4_1_0\, Y => AHBMASTER_FIC_0_AHBmaster_HRDATA(1)); GND_i : GND port map(Y => \GND\); \SDATASELInt_RNIQO801[2]\ : NOR3A port map(A => N_384, B => \SDATASELInt[2]_net_1\, C => \SDATASELInt[7]_net_1\, Y => \N_390\); \SDATASELInt_RNIDUSG[1]\ : NOR2A port map(A => \xhdl1222[0]\, B => \SDATASELInt[1]_net_1\, Y => HREADY_m2_e_0_0); \regHADDR_RNI8HAK1_1[29]\ : NOR2A port map(A => N_328, B => N_329, Y => N_405); \SDATASELInt[13]\ : DFN1E0C0 port map(D => \SADDRSEL[13]\, CLK => HCLK_c, CLR => HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q => \SDATASELInt[13]_net_1\); HREADY_M_iv_i_0_i_o4 : OR2B port map(A => masterDataInProg_0, B => CoreAHBLite_0_AHBmslave0_HREADY, Y => N_255); \regHWRITE\ : DFN1E1C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HWRITE, CLK => HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q => regHWRITE); \SDATASELInt_RNINVPD[14]\ : NOR2 port map(A => \SDATASELInt[14]_net_1\, B => \SDATASELInt[15]_net_1\, Y => N_383); \SDATASELInt[9]\ : DFN1E0C0 port map(D => \SADDRSEL[9]\, CLK => HCLK_c, CLR => HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q => \SDATASELInt[9]_net_1\); \SDATASELInt[1]\ : DFN1E0C0 port map(D => \SADDRSEL[1]\, CLK => HCLK_c, CLR => HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q => \SDATASELInt[1]_net_1\); \SDATASELInt[12]\ : DFN1E0C0 port map(D => \SADDRSEL[12]\, CLK => HCLK_c, CLR => HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q => \SDATASELInt[12]_net_1\); \SDATASELInt[0]\ : DFN1E0C0 port map(D => \xhdl1221[0]\, CLK => HCLK_c, CLR => HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q => \xhdl1222[0]\); \SDATASELInt[5]\ : DFN1E0C0 port map(D => \SADDRSEL[5]\, CLK => HCLK_c, CLR => HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q => \SDATASELInt[5]_net_1\); \SDATASELInt_RNISKATF[1]\ : OR2 port map(A => \PREVDATASLAVEREADY_iv_i_0_i_o4_1\, B => \PREVDATASLAVEREADY_iv_i_0_i_o4_0\, Y => N_251); \SDATASELInt_RNIPN0N8[0]\ : NOR3C port map(A => N_399, B => \xhdl1222[0]\, C => \HRDATA_4_3_0\, Y => AHBMASTER_FIC_0_AHBmaster_HRDATA(3)); HRDATA_4_6_0 : NOR3C port map(A => PRDATA_0_sqmuxa_0_a2_12, B => PRDATA_0_sqmuxa_0_a2_13, C => CoreAPB_0_APBmslave0_PRDATA(6), Y => \HRDATA_4_6_0\); \SDATASELInt_RNO[12]\ : NOR3C port map(A => \N_330\, B => \N_395\, C => N_404, Y => \SADDRSEL[12]\); \regHADDR[3]\ : DFN1E1C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_1, CLK => HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q => regHADDR_1); masterRegAddrSel_RNIFIE8T : NOR2B port map(A => d_masterRegAddrSel_0_0_a2_3_4, B => N_279, Y => masterAddrClockEnable); \SDATASELInt_RNIJRPD_0[12]\ : NOR2 port map(A => \SDATASELInt[12]_net_1\, B => \SDATASELInt[13]_net_1\, Y => N_382); \SDATASELInt[3]\ : DFN1E0C0 port map(D => \SADDRSEL[3]\, CLK => HCLK_c, CLR => HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q => \SDATASELInt[3]_net_1\); masterRegAddrSel_RNO_0 : NOR3B port map(A => \N_397\, B => d_masterRegAddrSel_0_0_a2_0, C => \N_330\, Y => d_masterRegAddrSel_0_0_a2_1); masterRegAddrSel_RNIDJG81 : MX2 port map(A => SADDRSEL_N_3_mux, B => SADDRSEL_N_5_mux, S => masterRegAddrSel_net_1, Y => \N_397\); \SDATASELInt_RNO[15]\ : NOR3C port map(A => \N_330\, B => N_396, C => N_408, Y => \SADDRSEL[15]\); \SDATASELInt_RNISKATF_0[1]\ : NOR2 port map(A => \PREVDATASLAVEREADY_iv_i_0_i_o4_1\, B => \PREVDATASLAVEREADY_iv_i_0_i_o4_0\, Y => \SDATASELInt_RNISKATF_0[1]_net_1\); \SDATASELInt_RNIKM7N1[12]\ : AO1 port map(A => N_261_i, B => N_383, C => N_376, Y => \N_265\); \regHADDR_RNI8HAK1_0[29]\ : NOR2A port map(A => N_329, B => N_328, Y => N_404); \SDATASELInt_RNO[13]\ : NOR3C port map(A => \N_330\, B => N_396, C => N_404, Y => \SADDRSEL[13]\); \SDATASELInt[7]\ : DFN1E0C0 port map(D => \SADDRSEL[7]\, CLK => HCLK_c, CLR => HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q => \SDATASELInt[7]_net_1\); \SDATASELInt_RNII3P5G[0]\ : NOR2A port map(A => N_251, B => \xhdl1222[0]\, Y => N_339_c); \SDATASELInt_RNO[10]\ : NOR3C port map(A => \N_330\, B => \N_395\, C => N_405, Y => \SADDRSEL[10]\); \regHADDR_RNIC16Q[30]\ : MX2 port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_28, B => \regHADDR[30]_net_1\, S => masterRegAddrSel_net_1, Y => N_329); HRDATA_4_1_0 : NOR3C port map(A => PRDATA_0_sqmuxa_0_a2_12, B => PRDATA_0_sqmuxa_0_a2_13, C => CoreAPB_0_APBmslave0_PRDATA(1), Y => \HRDATA_4_1_0\); \SDATASELInt_RNIKCEDK[0]\ : AO1 port map(A => N_398, B => N_251, C => N_334, Y => \SDATASELInt_RNIKCEDK[0]_net_1\); \SDATASELInt_RNIOM0N8[0]\ : NOR3C port map(A => N_399, B => \xhdl1222[0]\, C => \HRDATA_4_2_0\, Y => AHBMASTER_FIC_0_AHBmaster_HRDATA(2)); \SDATASELInt_RNIRP0N8[0]\ : NOR3C port map(A => N_399, B => \xhdl1222[0]\, C => \HRDATA_4_5_0\, Y => AHBMASTER_FIC_0_AHBmaster_HRDATA(5)); \SDATASELInt_RNIMODV3[0]\ : NOR3B port map(A => N_399, B => \xhdl1222[0]\, C => CoreAHBLite_0_AHBmslave0_HREADY, Y => N_334); \SDATASELInt_RNI2FBF[11]\ : XOR2 port map(A => \SDATASELInt[11]_net_1\, B => \SDATASELInt[4]_net_1\, Y => N_257_i); \SDATASELInt[6]\ : DFN1E0C0 port map(D => \SADDRSEL[6]\, CLK => HCLK_c, CLR => HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q => \SDATASELInt[6]_net_1\); masterRegAddrSel_RNO : AO1 port map(A => d_masterRegAddrSel_0_0_a2_1, B => N_279, C => masterAddrClockEnable, Y => d_masterRegAddrSel); HRDATA_4_4_0 : NOR3C port map(A => PRDATA_0_sqmuxa_0_a2_12, B => PRDATA_0_sqmuxa_0_a2_13, C => CoreAPB_0_APBmslave0_PRDATA(4), Y => \HRDATA_4_4_0\); \regHADDR[27]\ : DFN1E1C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_25, CLK => HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q => regHADDR_25); \regHADDR_RNI389M1_0[28]\ : NOR2A port map(A => N_254, B => \N_327\, Y => \N_395\); \SDATASELInt_RNIMK0N8[0]\ : NOR3C port map(A => N_399, B => \xhdl1222[0]\, C => \HRDATA_4_0_0\, Y => AHBMASTER_FIC_0_AHBmaster_HRDATA(0)); \SDATASELInt_RNO[4]\ : NOR3B port map(A => \N_395\, B => N_404, C => \N_330\, Y => \SADDRSEL[4]\); \SDATASELInt_RNIQO801_1[2]\ : NOR2B port map(A => N_258_i, B => N_384, Y => N_378); \SDATASELInt[11]\ : DFN1E0C0 port map(D => \SADDRSEL[11]\, CLK => HCLK_c, CLR => HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q => \SDATASELInt[11]_net_1\); \SDATASELInt[8]\ : DFN1E0C0 port map(D => \SADDRSEL[8]\, CLK => HCLK_c, CLR => HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q => \SDATASELInt[8]_net_1\); \SDATASELInt_RNO[7]\ : NOR3B port map(A => N_396, B => N_408, C => \N_330\, Y => \SADDRSEL[7]\); \SDATASELInt_RNO[1]\ : NOR3B port map(A => \N_397\, B => N_396, C => \N_330\, Y => \SADDRSEL[1]\); \SDATASELInt_RNITR801_1[6]\ : NOR3A port map(A => N_257_i, B => \SDATASELInt[6]_net_1\, C => \SDATASELInt[9]_net_1\, Y => N_379); \regHADDR[4]\ : DFN1E1C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_2, CLK => HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q => regHADDR_2); \regHADDR[26]\ : DFN1E1C0 port map(D => AHBMASTER_FIC_0_AHBmaster_HADDR_24, CLK => HCLK_c, CLR => HRESETn_c, E => masterAddrClockEnable, Q => regHADDR_24); \SDATASELInt[10]\ : DFN1E0C0 port map(D => \SADDRSEL[10]\, CLK => HCLK_c, CLR => HRESETn_c, E => \SDATASELInt_RNIKCEDK[0]_net_1\, Q => \SDATASELInt[10]_net_1\); \SDATASELInt_RNITR801_0[6]\ : NOR3A port map(A => N_386, B => \SDATASELInt[6]_net_1\, C => \SDATASELInt[9]_net_1\, Y => \N_389\); \regHADDR_RNIQD4Q[28]\ : MX2 port map(A => AHBMASTER_FIC_0_AHBmaster_HADDR_26, B => \regHADDR[28]_net_1\, S => masterRegAddrSel_net_1, Y => \N_327\); default_slave_sm : COREAHBLITE_DEFAULTSLAVESM_0 port map(HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, N_382 => N_382, N_383 => N_383, N_390 => \N_390\, N_389 => \N_389\, N_393 => N_393, N_391 => \N_391\, N_394 => \N_394\, N_392 => \N_392\, N_399 => N_399, defSlaveSMCurrentState => defSlaveSMCurrentState); end DEF_ARCH; library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity COREAHBLITE_MATRIX4X16 is port( CoreAHBLite_0_AHBmslave0_HWDATA : out std_logic_vector(7 downto 0); AHBMASTER_FIC_0_AHBmaster_HWDATA : in std_logic_vector(7 downto 0); arbRegSMCurrentState_i_0_3 : out std_logic; arbRegSMCurrentState_i_0_0 : out std_logic; arbRegSMCurrentState_RNICAHF7_0 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : in std_logic; CoreAPB_0_APBmslave0_PRDATA : in std_logic_vector(7 downto 0); xhdl1222_0 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HRDATA : out std_logic_vector(7 downto 0); masterAddrInProg_i_1_0 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_26 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_27 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_28 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_29 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_0 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_1 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_2 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_22 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_23 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_24 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_25 : in std_logic; un4_m5_0_a3_1 : in std_logic; un1_m1_e_0_0 : in std_logic; N_364 : out std_logic; N_365 : out std_logic; HTRANS_0_a3_i_a2_4_0 : out std_logic; HTRANS_0_a3_i_a2_3_0 : out std_logic; N_323 : out std_logic; N_326 : out std_logic; N_18 : out std_logic; N_135 : out std_logic; N_20 : out std_logic; N_22 : out std_logic; N_120 : out std_logic; N_124 : out std_logic; N_128 : out std_logic; un4_m5_0_a3_2 : in std_logic; HADDR_24_0_a3_i_out : out std_logic; N_363 : out std_logic; CoreAHBLite_0_AHBmslave0_HSELx : out std_logic; un1_N_11_mux_i_5_a1_1 : in std_logic; N_367 : out std_logic; N_263 : out std_logic; N_171 : out std_logic; N_398 : in std_logic; N_397 : out std_logic; N_330 : out std_logic; N_340 : out std_logic; N_327 : out std_logic; PRDATA_0_sqmuxa_0_a2_12 : in std_logic; PRDATA_0_sqmuxa_0_a2_13 : in std_logic; N_391 : out std_logic; N_392 : out std_logic; PREVDATASLAVEREADY_iv_i_0_i_o4_1 : out std_logic; PREVDATASLAVEREADY_iv_i_0_i_o4_0 : out std_logic; N_339_c : out std_logic; N_265 : out std_logic; N_395 : out std_logic; N_254 : out std_logic; CoreAHBLite_0_AHBmslave0_HREADY : in std_logic; N_163 : out std_logic; HCLK_c : in std_logic; HRESETn_c : in std_logic; AHBMASTER_FIC_0_AHBmaster_HWRITE : in std_logic; defSlaveSMCurrentState : out std_logic ); end COREAHBLITE_MATRIX4X16; architecture DEF_ARCH of COREAHBLITE_MATRIX4X16 is component COREAHBLITE_SLAVESTAGE_16 port( xhdl1221_0 : in std_logic := 'U'; arbRegSMCurrentState_RNICAHF7_0 : out std_logic; arbRegSMCurrentState_i_0_3 : out std_logic; arbRegSMCurrentState_i_0_0 : out std_logic; masterAddrInProg_i_1_0 : out std_logic; regHADDR_29 : in std_logic := 'U'; regHADDR_22 : in std_logic := 'U'; regHADDR_23 : in std_logic := 'U'; regHADDR_24 : in std_logic := 'U'; regHADDR_25 : in std_logic := 'U'; regHADDR_2 : in std_logic := 'U'; regHADDR_1 : in std_logic := 'U'; regHADDR_0 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_29 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_22 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_23 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_24 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_25 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_2 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_1 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_0 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HWDATA : in std_logic_vector(7 downto 0) := (others => 'U'); CoreAHBLite_0_AHBmslave0_HWDATA : out std_logic_vector(7 downto 0); AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : in std_logic := 'U'; masterDataInProg_0 : out std_logic; SDATASELInt_2 : in std_logic := 'U'; SDATASELInt_4 : in std_logic := 'U'; SDATASELInt_0 : in std_logic := 'U'; N_327 : in std_logic := 'U'; N_397 : in std_logic := 'U'; N_330 : in std_logic := 'U'; N_171 : out std_logic; N_263 : out std_logic; N_367 : out std_logic; N_403 : in std_logic := 'U'; un1_N_11_mux_i_5_a1_1 : in std_logic := 'U'; CoreAHBLite_0_AHBmslave0_HSELx : out std_logic; N_363 : out std_logic; HADDR_24_0_a3_i_out : out std_logic; un4_m5_0_a3_2 : in std_logic := 'U'; N_128 : out std_logic; N_124 : out std_logic; N_120 : out std_logic; N_22 : out std_logic; N_20 : out std_logic; N_135 : out std_logic; N_18 : out std_logic; CoreAHBLite_0_AHBmslave0_HREADY : in std_logic := 'U'; HRESETn_c : in std_logic := 'U'; HCLK_c : in std_logic := 'U'; regHWRITE : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HWRITE : in std_logic := 'U'; N_326 : out std_logic; N_323 : out std_logic; regHTRANS : in std_logic := 'U'; N_389 : in std_logic := 'U'; N_377 : in std_logic := 'U'; N_378 : in std_logic := 'U'; N_390 : in std_logic := 'U'; N_379 : in std_logic := 'U'; N_380 : in std_logic := 'U'; HTRANS_0_a3_i_a2_3_0 : out std_logic; HTRANS_0_a3_i_a2_4_0 : out std_logic; N_392 : in std_logic := 'U'; N_365_1 : out std_logic; N_365 : out std_logic; N_394 : in std_logic := 'U'; N_364_1 : out std_logic; N_364 : out std_logic; N_391 : in std_logic := 'U'; un1_m1_e_0_0 : in std_logic := 'U'; N_393 : out std_logic; N_398 : in std_logic := 'U'; masterRegAddrSel : in std_logic := 'U'; un4_m5_0_a3_1 : in std_logic := 'U'; N_254 : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component COREAHBLITE_MASTERSTAGE_1_1_0_1_0 port( AHBMASTER_FIC_0_AHBmaster_HADDR_26 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_27 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_28 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_29 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_0 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_1 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_2 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_22 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_23 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_24 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_25 : in std_logic := 'U'; regHADDR_29 : out std_logic; regHADDR_0 : out std_logic; regHADDR_1 : out std_logic; regHADDR_2 : out std_logic; regHADDR_22 : out std_logic; regHADDR_23 : out std_logic; regHADDR_24 : out std_logic; regHADDR_25 : out std_logic; masterDataInProg_0 : in std_logic := 'U'; masterAddrInProg_i_1_0 : in std_logic := 'U'; xhdl1221_0 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HRDATA : out std_logic_vector(7 downto 0); SDATASELInt_4 : out std_logic; SDATASELInt_2 : out std_logic; SDATASELInt_0 : out std_logic; xhdl1222_0 : out std_logic; CoreAPB_0_APBmslave0_PRDATA : in std_logic_vector(7 downto 0) := (others => 'U'); AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : in std_logic := 'U'; defSlaveSMCurrentState : out std_logic; AHBMASTER_FIC_0_AHBmaster_HWRITE : in std_logic := 'U'; regHWRITE : out std_logic; HRESETn_c : in std_logic := 'U'; HCLK_c : in std_logic := 'U'; N_163 : out std_logic; CoreAHBLite_0_AHBmslave0_HREADY : in std_logic := 'U'; N_254 : in std_logic := 'U'; N_395 : out std_logic; N_393 : in std_logic := 'U'; N_265 : out std_logic; N_390 : out std_logic; N_389 : out std_logic; N_380 : out std_logic; N_379 : out std_logic; N_378 : out std_logic; N_377 : out std_logic; N_339_c : out std_logic; N_394 : out std_logic; N_364_1 : in std_logic := 'U'; N_365_1 : in std_logic := 'U'; PREVDATASLAVEREADY_iv_i_0_i_o4_0 : out std_logic; N_403 : out std_logic; PREVDATASLAVEREADY_iv_i_0_i_o4_1 : out std_logic; N_392 : out std_logic; N_391 : out std_logic; PRDATA_0_sqmuxa_0_a2_13 : in std_logic := 'U'; PRDATA_0_sqmuxa_0_a2_12 : in std_logic := 'U'; N_327 : out std_logic; regHTRANS : out std_logic; masterRegAddrSel : out std_logic; N_340 : out std_logic; N_330 : out std_logic; N_397 : out std_logic; N_398 : in std_logic := 'U' ); end component; component GND port( Y : out std_logic ); end component; signal \regHADDR[31]\, \regHADDR[2]\, \regHADDR[3]\, \regHADDR[4]\, \regHADDR[24]\, \regHADDR[25]\, \regHADDR[26]\, \regHADDR[27]\, \masterDataInProg[0]\, \masterAddrInProg_i_1[0]\, \xhdl1221[0]\, \SDATASELInt[5]\, \SDATASELInt[3]\, \SDATASELInt[1]\, regHWRITE, \N_254\, N_393, N_390, N_389, N_380, N_379, N_378, N_377, N_394, N_364_1, N_365_1, N_403, \N_392\, \N_391\, \N_327\, regHTRANS, masterRegAddrSel, \N_330\, \N_397\, \GND\, \VCC\ : std_logic; for all : COREAHBLITE_SLAVESTAGE_16 Use entity work.COREAHBLITE_SLAVESTAGE_16(DEF_ARCH); for all : COREAHBLITE_MASTERSTAGE_1_1_0_1_0 Use entity work.COREAHBLITE_MASTERSTAGE_1_1_0_1_0(DEF_ARCH); begin masterAddrInProg_i_1_0 <= \masterAddrInProg_i_1[0]\; N_397 <= \N_397\; N_330 <= \N_330\; N_327 <= \N_327\; N_391 <= \N_391\; N_392 <= \N_392\; N_254 <= \N_254\; slavestage_0 : COREAHBLITE_SLAVESTAGE_16 port map(xhdl1221_0 => \xhdl1221[0]\, arbRegSMCurrentState_RNICAHF7_0 => arbRegSMCurrentState_RNICAHF7_0, arbRegSMCurrentState_i_0_3 => arbRegSMCurrentState_i_0_3, arbRegSMCurrentState_i_0_0 => arbRegSMCurrentState_i_0_0, masterAddrInProg_i_1_0 => \masterAddrInProg_i_1[0]\, regHADDR_29 => \regHADDR[31]\, regHADDR_22 => \regHADDR[24]\, regHADDR_23 => \regHADDR[25]\, regHADDR_24 => \regHADDR[26]\, regHADDR_25 => \regHADDR[27]\, regHADDR_2 => \regHADDR[4]\, regHADDR_1 => \regHADDR[3]\, regHADDR_0 => \regHADDR[2]\, AHBMASTER_FIC_0_AHBmaster_HADDR_29 => AHBMASTER_FIC_0_AHBmaster_HADDR_29, AHBMASTER_FIC_0_AHBmaster_HADDR_22 => AHBMASTER_FIC_0_AHBmaster_HADDR_22, AHBMASTER_FIC_0_AHBmaster_HADDR_23 => AHBMASTER_FIC_0_AHBmaster_HADDR_23, AHBMASTER_FIC_0_AHBmaster_HADDR_24 => AHBMASTER_FIC_0_AHBmaster_HADDR_24, AHBMASTER_FIC_0_AHBmaster_HADDR_25 => AHBMASTER_FIC_0_AHBmaster_HADDR_25, AHBMASTER_FIC_0_AHBmaster_HADDR_2 => AHBMASTER_FIC_0_AHBmaster_HADDR_2, AHBMASTER_FIC_0_AHBmaster_HADDR_1 => AHBMASTER_FIC_0_AHBmaster_HADDR_1, AHBMASTER_FIC_0_AHBmaster_HADDR_0 => AHBMASTER_FIC_0_AHBmaster_HADDR_0, AHBMASTER_FIC_0_AHBmaster_HWDATA(7) => AHBMASTER_FIC_0_AHBmaster_HWDATA(7), AHBMASTER_FIC_0_AHBmaster_HWDATA(6) => AHBMASTER_FIC_0_AHBmaster_HWDATA(6), AHBMASTER_FIC_0_AHBmaster_HWDATA(5) => AHBMASTER_FIC_0_AHBmaster_HWDATA(5), AHBMASTER_FIC_0_AHBmaster_HWDATA(4) => AHBMASTER_FIC_0_AHBmaster_HWDATA(4), AHBMASTER_FIC_0_AHBmaster_HWDATA(3) => AHBMASTER_FIC_0_AHBmaster_HWDATA(3), AHBMASTER_FIC_0_AHBmaster_HWDATA(2) => AHBMASTER_FIC_0_AHBmaster_HWDATA(2), AHBMASTER_FIC_0_AHBmaster_HWDATA(1) => AHBMASTER_FIC_0_AHBmaster_HWDATA(1), AHBMASTER_FIC_0_AHBmaster_HWDATA(0) => AHBMASTER_FIC_0_AHBmaster_HWDATA(0), CoreAHBLite_0_AHBmslave0_HWDATA(7) => CoreAHBLite_0_AHBmslave0_HWDATA(7), CoreAHBLite_0_AHBmslave0_HWDATA(6) => CoreAHBLite_0_AHBmslave0_HWDATA(6), CoreAHBLite_0_AHBmslave0_HWDATA(5) => CoreAHBLite_0_AHBmslave0_HWDATA(5), CoreAHBLite_0_AHBmslave0_HWDATA(4) => CoreAHBLite_0_AHBmslave0_HWDATA(4), CoreAHBLite_0_AHBmslave0_HWDATA(3) => CoreAHBLite_0_AHBmslave0_HWDATA(3), CoreAHBLite_0_AHBmslave0_HWDATA(2) => CoreAHBLite_0_AHBmslave0_HWDATA(2), CoreAHBLite_0_AHBmslave0_HWDATA(1) => CoreAHBLite_0_AHBmslave0_HWDATA(1), CoreAHBLite_0_AHBmslave0_HWDATA(0) => CoreAHBLite_0_AHBmslave0_HWDATA(0), AHBMASTER_FIC_0_AHBmaster_HTRANS_0 => AHBMASTER_FIC_0_AHBmaster_HTRANS_0, masterDataInProg_0 => \masterDataInProg[0]\, SDATASELInt_2 => \SDATASELInt[3]\, SDATASELInt_4 => \SDATASELInt[5]\, SDATASELInt_0 => \SDATASELInt[1]\, N_327 => \N_327\, N_397 => \N_397\, N_330 => \N_330\, N_171 => N_171, N_263 => N_263, N_367 => N_367, N_403 => N_403, un1_N_11_mux_i_5_a1_1 => un1_N_11_mux_i_5_a1_1, CoreAHBLite_0_AHBmslave0_HSELx => CoreAHBLite_0_AHBmslave0_HSELx, N_363 => N_363, HADDR_24_0_a3_i_out => HADDR_24_0_a3_i_out, un4_m5_0_a3_2 => un4_m5_0_a3_2, N_128 => N_128, N_124 => N_124, N_120 => N_120, N_22 => N_22, N_20 => N_20, N_135 => N_135, N_18 => N_18, CoreAHBLite_0_AHBmslave0_HREADY => CoreAHBLite_0_AHBmslave0_HREADY, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, regHWRITE => regHWRITE, AHBMASTER_FIC_0_AHBmaster_HWRITE => AHBMASTER_FIC_0_AHBmaster_HWRITE, N_326 => N_326, N_323 => N_323, regHTRANS => regHTRANS, N_389 => N_389, N_377 => N_377, N_378 => N_378, N_390 => N_390, N_379 => N_379, N_380 => N_380, HTRANS_0_a3_i_a2_3_0 => HTRANS_0_a3_i_a2_3_0, HTRANS_0_a3_i_a2_4_0 => HTRANS_0_a3_i_a2_4_0, N_392 => \N_392\, N_365_1 => N_365_1, N_365 => N_365, N_394 => N_394, N_364_1 => N_364_1, N_364 => N_364, N_391 => \N_391\, un1_m1_e_0_0 => un1_m1_e_0_0, N_393 => N_393, N_398 => N_398, masterRegAddrSel => masterRegAddrSel, un4_m5_0_a3_1 => un4_m5_0_a3_1, N_254 => \N_254\); VCC_i : VCC port map(Y => \VCC\); masterstage_0 : COREAHBLITE_MASTERSTAGE_1_1_0_1_0 port map(AHBMASTER_FIC_0_AHBmaster_HADDR_26 => AHBMASTER_FIC_0_AHBmaster_HADDR_26, AHBMASTER_FIC_0_AHBmaster_HADDR_27 => AHBMASTER_FIC_0_AHBmaster_HADDR_27, AHBMASTER_FIC_0_AHBmaster_HADDR_28 => AHBMASTER_FIC_0_AHBmaster_HADDR_28, AHBMASTER_FIC_0_AHBmaster_HADDR_29 => AHBMASTER_FIC_0_AHBmaster_HADDR_29, AHBMASTER_FIC_0_AHBmaster_HADDR_0 => AHBMASTER_FIC_0_AHBmaster_HADDR_0, AHBMASTER_FIC_0_AHBmaster_HADDR_1 => AHBMASTER_FIC_0_AHBmaster_HADDR_1, AHBMASTER_FIC_0_AHBmaster_HADDR_2 => AHBMASTER_FIC_0_AHBmaster_HADDR_2, AHBMASTER_FIC_0_AHBmaster_HADDR_22 => AHBMASTER_FIC_0_AHBmaster_HADDR_22, AHBMASTER_FIC_0_AHBmaster_HADDR_23 => AHBMASTER_FIC_0_AHBmaster_HADDR_23, AHBMASTER_FIC_0_AHBmaster_HADDR_24 => AHBMASTER_FIC_0_AHBmaster_HADDR_24, AHBMASTER_FIC_0_AHBmaster_HADDR_25 => AHBMASTER_FIC_0_AHBmaster_HADDR_25, regHADDR_29 => \regHADDR[31]\, regHADDR_0 => \regHADDR[2]\, regHADDR_1 => \regHADDR[3]\, regHADDR_2 => \regHADDR[4]\, regHADDR_22 => \regHADDR[24]\, regHADDR_23 => \regHADDR[25]\, regHADDR_24 => \regHADDR[26]\, regHADDR_25 => \regHADDR[27]\, masterDataInProg_0 => \masterDataInProg[0]\, masterAddrInProg_i_1_0 => \masterAddrInProg_i_1[0]\, xhdl1221_0 => \xhdl1221[0]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(7) => AHBMASTER_FIC_0_AHBmaster_HRDATA(7), AHBMASTER_FIC_0_AHBmaster_HRDATA(6) => AHBMASTER_FIC_0_AHBmaster_HRDATA(6), AHBMASTER_FIC_0_AHBmaster_HRDATA(5) => AHBMASTER_FIC_0_AHBmaster_HRDATA(5), AHBMASTER_FIC_0_AHBmaster_HRDATA(4) => AHBMASTER_FIC_0_AHBmaster_HRDATA(4), AHBMASTER_FIC_0_AHBmaster_HRDATA(3) => AHBMASTER_FIC_0_AHBmaster_HRDATA(3), AHBMASTER_FIC_0_AHBmaster_HRDATA(2) => AHBMASTER_FIC_0_AHBmaster_HRDATA(2), AHBMASTER_FIC_0_AHBmaster_HRDATA(1) => AHBMASTER_FIC_0_AHBmaster_HRDATA(1), AHBMASTER_FIC_0_AHBmaster_HRDATA(0) => AHBMASTER_FIC_0_AHBmaster_HRDATA(0), SDATASELInt_4 => \SDATASELInt[5]\, SDATASELInt_2 => \SDATASELInt[3]\, SDATASELInt_0 => \SDATASELInt[1]\, xhdl1222_0 => xhdl1222_0, CoreAPB_0_APBmslave0_PRDATA(7) => CoreAPB_0_APBmslave0_PRDATA(7), CoreAPB_0_APBmslave0_PRDATA(6) => CoreAPB_0_APBmslave0_PRDATA(6), CoreAPB_0_APBmslave0_PRDATA(5) => CoreAPB_0_APBmslave0_PRDATA(5), CoreAPB_0_APBmslave0_PRDATA(4) => CoreAPB_0_APBmslave0_PRDATA(4), CoreAPB_0_APBmslave0_PRDATA(3) => CoreAPB_0_APBmslave0_PRDATA(3), CoreAPB_0_APBmslave0_PRDATA(2) => CoreAPB_0_APBmslave0_PRDATA(2), CoreAPB_0_APBmslave0_PRDATA(1) => CoreAPB_0_APBmslave0_PRDATA(1), CoreAPB_0_APBmslave0_PRDATA(0) => CoreAPB_0_APBmslave0_PRDATA(0), AHBMASTER_FIC_0_AHBmaster_HTRANS_0 => AHBMASTER_FIC_0_AHBmaster_HTRANS_0, defSlaveSMCurrentState => defSlaveSMCurrentState, AHBMASTER_FIC_0_AHBmaster_HWRITE => AHBMASTER_FIC_0_AHBmaster_HWRITE, regHWRITE => regHWRITE, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, N_163 => N_163, CoreAHBLite_0_AHBmslave0_HREADY => CoreAHBLite_0_AHBmslave0_HREADY, N_254 => \N_254\, N_395 => N_395, N_393 => N_393, N_265 => N_265, N_390 => N_390, N_389 => N_389, N_380 => N_380, N_379 => N_379, N_378 => N_378, N_377 => N_377, N_339_c => N_339_c, N_394 => N_394, N_364_1 => N_364_1, N_365_1 => N_365_1, PREVDATASLAVEREADY_iv_i_0_i_o4_0 => PREVDATASLAVEREADY_iv_i_0_i_o4_0, N_403 => N_403, PREVDATASLAVEREADY_iv_i_0_i_o4_1 => PREVDATASLAVEREADY_iv_i_0_i_o4_1, N_392 => \N_392\, N_391 => \N_391\, PRDATA_0_sqmuxa_0_a2_13 => PRDATA_0_sqmuxa_0_a2_13, PRDATA_0_sqmuxa_0_a2_12 => PRDATA_0_sqmuxa_0_a2_12, N_327 => \N_327\, regHTRANS => regHTRANS, masterRegAddrSel => masterRegAddrSel, N_340 => N_340, N_330 => \N_330\, N_397 => \N_397\, N_398 => N_398); GND_i : GND port map(Y => \GND\); end DEF_ARCH; library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity top_CoreAHBLite_0_CoreAHBLite is port( AHBMASTER_FIC_0_AHBmaster_HADDR_26 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_27 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_28 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_29 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_0 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_1 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_2 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_22 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_23 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_24 : in std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_25 : in std_logic; masterAddrInProg_i_1_0 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HRDATA : out std_logic_vector(7 downto 0); xhdl1222_0 : out std_logic; CoreAPB_0_APBmslave0_PRDATA : in std_logic_vector(7 downto 0); AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : in std_logic; arbRegSMCurrentState_RNICAHF7_0 : out std_logic; arbRegSMCurrentState_i_0_3 : out std_logic; arbRegSMCurrentState_i_0_0 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HWDATA : in std_logic_vector(7 downto 0); CoreAHBLite_0_AHBmslave0_HWDATA : out std_logic_vector(7 downto 0); defSlaveSMCurrentState : out std_logic; AHBMASTER_FIC_0_AHBmaster_HWRITE : in std_logic; HRESETn_c : in std_logic; HCLK_c : in std_logic; N_163 : out std_logic; CoreAHBLite_0_AHBmslave0_HREADY : in std_logic; N_254 : out std_logic; N_395 : out std_logic; N_265 : out std_logic; N_339_c : out std_logic; PREVDATASLAVEREADY_iv_i_0_i_o4_0 : out std_logic; PREVDATASLAVEREADY_iv_i_0_i_o4_1 : out std_logic; N_392 : out std_logic; N_391 : out std_logic; PRDATA_0_sqmuxa_0_a2_13 : in std_logic; PRDATA_0_sqmuxa_0_a2_12 : in std_logic; N_327 : out std_logic; N_340 : out std_logic; N_330 : out std_logic; N_397 : out std_logic; N_398 : in std_logic; N_171 : out std_logic; N_263 : out std_logic; N_367 : out std_logic; un1_N_11_mux_i_5_a1_1 : in std_logic; CoreAHBLite_0_AHBmslave0_HSELx : out std_logic; N_363 : out std_logic; HADDR_24_0_a3_i_out : out std_logic; un4_m5_0_a3_2 : in std_logic; N_128 : out std_logic; N_124 : out std_logic; N_120 : out std_logic; N_22 : out std_logic; N_20 : out std_logic; N_135 : out std_logic; N_18 : out std_logic; N_326 : out std_logic; N_323 : out std_logic; HTRANS_0_a3_i_a2_3_0 : out std_logic; HTRANS_0_a3_i_a2_4_0 : out std_logic; N_365 : out std_logic; N_364 : out std_logic; un1_m1_e_0_0 : in std_logic; un4_m5_0_a3_1 : in std_logic ); end top_CoreAHBLite_0_CoreAHBLite; architecture DEF_ARCH of top_CoreAHBLite_0_CoreAHBLite is component COREAHBLITE_MATRIX4X16 port( CoreAHBLite_0_AHBmslave0_HWDATA : out std_logic_vector(7 downto 0); AHBMASTER_FIC_0_AHBmaster_HWDATA : in std_logic_vector(7 downto 0) := (others => 'U'); arbRegSMCurrentState_i_0_3 : out std_logic; arbRegSMCurrentState_i_0_0 : out std_logic; arbRegSMCurrentState_RNICAHF7_0 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : in std_logic := 'U'; CoreAPB_0_APBmslave0_PRDATA : in std_logic_vector(7 downto 0) := (others => 'U'); xhdl1222_0 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HRDATA : out std_logic_vector(7 downto 0); masterAddrInProg_i_1_0 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_26 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_27 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_28 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_29 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_0 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_1 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_2 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_22 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_23 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_24 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_25 : in std_logic := 'U'; un4_m5_0_a3_1 : in std_logic := 'U'; un1_m1_e_0_0 : in std_logic := 'U'; N_364 : out std_logic; N_365 : out std_logic; HTRANS_0_a3_i_a2_4_0 : out std_logic; HTRANS_0_a3_i_a2_3_0 : out std_logic; N_323 : out std_logic; N_326 : out std_logic; N_18 : out std_logic; N_135 : out std_logic; N_20 : out std_logic; N_22 : out std_logic; N_120 : out std_logic; N_124 : out std_logic; N_128 : out std_logic; un4_m5_0_a3_2 : in std_logic := 'U'; HADDR_24_0_a3_i_out : out std_logic; N_363 : out std_logic; CoreAHBLite_0_AHBmslave0_HSELx : out std_logic; un1_N_11_mux_i_5_a1_1 : in std_logic := 'U'; N_367 : out std_logic; N_263 : out std_logic; N_171 : out std_logic; N_398 : in std_logic := 'U'; N_397 : out std_logic; N_330 : out std_logic; N_340 : out std_logic; N_327 : out std_logic; PRDATA_0_sqmuxa_0_a2_12 : in std_logic := 'U'; PRDATA_0_sqmuxa_0_a2_13 : in std_logic := 'U'; N_391 : out std_logic; N_392 : out std_logic; PREVDATASLAVEREADY_iv_i_0_i_o4_1 : out std_logic; PREVDATASLAVEREADY_iv_i_0_i_o4_0 : out std_logic; N_339_c : out std_logic; N_265 : out std_logic; N_395 : out std_logic; N_254 : out std_logic; CoreAHBLite_0_AHBmslave0_HREADY : in std_logic := 'U'; N_163 : out std_logic; HCLK_c : in std_logic := 'U'; HRESETn_c : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HWRITE : in std_logic := 'U'; defSlaveSMCurrentState : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; signal \GND\, \VCC\ : std_logic; for all : COREAHBLITE_MATRIX4X16 Use entity work.COREAHBLITE_MATRIX4X16(DEF_ARCH); begin matrix4x16 : COREAHBLITE_MATRIX4X16 port map(CoreAHBLite_0_AHBmslave0_HWDATA(7) => CoreAHBLite_0_AHBmslave0_HWDATA(7), CoreAHBLite_0_AHBmslave0_HWDATA(6) => CoreAHBLite_0_AHBmslave0_HWDATA(6), CoreAHBLite_0_AHBmslave0_HWDATA(5) => CoreAHBLite_0_AHBmslave0_HWDATA(5), CoreAHBLite_0_AHBmslave0_HWDATA(4) => CoreAHBLite_0_AHBmslave0_HWDATA(4), CoreAHBLite_0_AHBmslave0_HWDATA(3) => CoreAHBLite_0_AHBmslave0_HWDATA(3), CoreAHBLite_0_AHBmslave0_HWDATA(2) => CoreAHBLite_0_AHBmslave0_HWDATA(2), CoreAHBLite_0_AHBmslave0_HWDATA(1) => CoreAHBLite_0_AHBmslave0_HWDATA(1), CoreAHBLite_0_AHBmslave0_HWDATA(0) => CoreAHBLite_0_AHBmslave0_HWDATA(0), AHBMASTER_FIC_0_AHBmaster_HWDATA(7) => AHBMASTER_FIC_0_AHBmaster_HWDATA(7), AHBMASTER_FIC_0_AHBmaster_HWDATA(6) => AHBMASTER_FIC_0_AHBmaster_HWDATA(6), AHBMASTER_FIC_0_AHBmaster_HWDATA(5) => AHBMASTER_FIC_0_AHBmaster_HWDATA(5), AHBMASTER_FIC_0_AHBmaster_HWDATA(4) => AHBMASTER_FIC_0_AHBmaster_HWDATA(4), AHBMASTER_FIC_0_AHBmaster_HWDATA(3) => AHBMASTER_FIC_0_AHBmaster_HWDATA(3), AHBMASTER_FIC_0_AHBmaster_HWDATA(2) => AHBMASTER_FIC_0_AHBmaster_HWDATA(2), AHBMASTER_FIC_0_AHBmaster_HWDATA(1) => AHBMASTER_FIC_0_AHBmaster_HWDATA(1), AHBMASTER_FIC_0_AHBmaster_HWDATA(0) => AHBMASTER_FIC_0_AHBmaster_HWDATA(0), arbRegSMCurrentState_i_0_3 => arbRegSMCurrentState_i_0_3, arbRegSMCurrentState_i_0_0 => arbRegSMCurrentState_i_0_0, arbRegSMCurrentState_RNICAHF7_0 => arbRegSMCurrentState_RNICAHF7_0, AHBMASTER_FIC_0_AHBmaster_HTRANS_0 => AHBMASTER_FIC_0_AHBmaster_HTRANS_0, CoreAPB_0_APBmslave0_PRDATA(7) => CoreAPB_0_APBmslave0_PRDATA(7), CoreAPB_0_APBmslave0_PRDATA(6) => CoreAPB_0_APBmslave0_PRDATA(6), CoreAPB_0_APBmslave0_PRDATA(5) => CoreAPB_0_APBmslave0_PRDATA(5), CoreAPB_0_APBmslave0_PRDATA(4) => CoreAPB_0_APBmslave0_PRDATA(4), CoreAPB_0_APBmslave0_PRDATA(3) => CoreAPB_0_APBmslave0_PRDATA(3), CoreAPB_0_APBmslave0_PRDATA(2) => CoreAPB_0_APBmslave0_PRDATA(2), CoreAPB_0_APBmslave0_PRDATA(1) => CoreAPB_0_APBmslave0_PRDATA(1), CoreAPB_0_APBmslave0_PRDATA(0) => CoreAPB_0_APBmslave0_PRDATA(0), xhdl1222_0 => xhdl1222_0, AHBMASTER_FIC_0_AHBmaster_HRDATA(7) => AHBMASTER_FIC_0_AHBmaster_HRDATA(7), AHBMASTER_FIC_0_AHBmaster_HRDATA(6) => AHBMASTER_FIC_0_AHBmaster_HRDATA(6), AHBMASTER_FIC_0_AHBmaster_HRDATA(5) => AHBMASTER_FIC_0_AHBmaster_HRDATA(5), AHBMASTER_FIC_0_AHBmaster_HRDATA(4) => AHBMASTER_FIC_0_AHBmaster_HRDATA(4), AHBMASTER_FIC_0_AHBmaster_HRDATA(3) => AHBMASTER_FIC_0_AHBmaster_HRDATA(3), AHBMASTER_FIC_0_AHBmaster_HRDATA(2) => AHBMASTER_FIC_0_AHBmaster_HRDATA(2), AHBMASTER_FIC_0_AHBmaster_HRDATA(1) => AHBMASTER_FIC_0_AHBmaster_HRDATA(1), AHBMASTER_FIC_0_AHBmaster_HRDATA(0) => AHBMASTER_FIC_0_AHBmaster_HRDATA(0), masterAddrInProg_i_1_0 => masterAddrInProg_i_1_0, AHBMASTER_FIC_0_AHBmaster_HADDR_26 => AHBMASTER_FIC_0_AHBmaster_HADDR_26, AHBMASTER_FIC_0_AHBmaster_HADDR_27 => AHBMASTER_FIC_0_AHBmaster_HADDR_27, AHBMASTER_FIC_0_AHBmaster_HADDR_28 => AHBMASTER_FIC_0_AHBmaster_HADDR_28, AHBMASTER_FIC_0_AHBmaster_HADDR_29 => AHBMASTER_FIC_0_AHBmaster_HADDR_29, AHBMASTER_FIC_0_AHBmaster_HADDR_0 => AHBMASTER_FIC_0_AHBmaster_HADDR_0, AHBMASTER_FIC_0_AHBmaster_HADDR_1 => AHBMASTER_FIC_0_AHBmaster_HADDR_1, AHBMASTER_FIC_0_AHBmaster_HADDR_2 => AHBMASTER_FIC_0_AHBmaster_HADDR_2, AHBMASTER_FIC_0_AHBmaster_HADDR_22 => AHBMASTER_FIC_0_AHBmaster_HADDR_22, AHBMASTER_FIC_0_AHBmaster_HADDR_23 => AHBMASTER_FIC_0_AHBmaster_HADDR_23, AHBMASTER_FIC_0_AHBmaster_HADDR_24 => AHBMASTER_FIC_0_AHBmaster_HADDR_24, AHBMASTER_FIC_0_AHBmaster_HADDR_25 => AHBMASTER_FIC_0_AHBmaster_HADDR_25, un4_m5_0_a3_1 => un4_m5_0_a3_1, un1_m1_e_0_0 => un1_m1_e_0_0, N_364 => N_364, N_365 => N_365, HTRANS_0_a3_i_a2_4_0 => HTRANS_0_a3_i_a2_4_0, HTRANS_0_a3_i_a2_3_0 => HTRANS_0_a3_i_a2_3_0, N_323 => N_323, N_326 => N_326, N_18 => N_18, N_135 => N_135, N_20 => N_20, N_22 => N_22, N_120 => N_120, N_124 => N_124, N_128 => N_128, un4_m5_0_a3_2 => un4_m5_0_a3_2, HADDR_24_0_a3_i_out => HADDR_24_0_a3_i_out, N_363 => N_363, CoreAHBLite_0_AHBmslave0_HSELx => CoreAHBLite_0_AHBmslave0_HSELx, un1_N_11_mux_i_5_a1_1 => un1_N_11_mux_i_5_a1_1, N_367 => N_367, N_263 => N_263, N_171 => N_171, N_398 => N_398, N_397 => N_397, N_330 => N_330, N_340 => N_340, N_327 => N_327, PRDATA_0_sqmuxa_0_a2_12 => PRDATA_0_sqmuxa_0_a2_12, PRDATA_0_sqmuxa_0_a2_13 => PRDATA_0_sqmuxa_0_a2_13, N_391 => N_391, N_392 => N_392, PREVDATASLAVEREADY_iv_i_0_i_o4_1 => PREVDATASLAVEREADY_iv_i_0_i_o4_1, PREVDATASLAVEREADY_iv_i_0_i_o4_0 => PREVDATASLAVEREADY_iv_i_0_i_o4_0, N_339_c => N_339_c, N_265 => N_265, N_395 => N_395, N_254 => N_254, CoreAHBLite_0_AHBmslave0_HREADY => CoreAHBLite_0_AHBmslave0_HREADY, N_163 => N_163, HCLK_c => HCLK_c, HRESETn_c => HRESETn_c, AHBMASTER_FIC_0_AHBmaster_HWRITE => AHBMASTER_FIC_0_AHBmaster_HWRITE, defSlaveSMCurrentState => defSlaveSMCurrentState); VCC_i : VCC port map(Y => \VCC\); GND_i : GND port map(Y => \GND\); end DEF_ARCH; library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity top_CoreUARTapb_0_Tx_async is port( tx_hold_reg : in std_logic_vector(7 downto 0); HRESETn_c : in std_logic; HCLK_c : in std_logic; TX_c : out std_logic; TXRDY : out std_logic; xmit_pulse : in std_logic; un1_csn : in std_logic ); end top_CoreUARTapb_0_Tx_async; architecture DEF_ARCH of top_CoreUARTapb_0_Tx_async is component DFN1E0P0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; PRE : in std_logic := 'U'; E : in std_logic := 'U'; Q : out std_logic ); end component; component NOR2B port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; Q : out std_logic ); end component; component MX2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; S : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1E1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; E : in std_logic := 'U'; Q : out std_logic ); end component; component XA1 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component MX2C port( A : in std_logic := 'U'; B : in std_logic := 'U'; S : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1P0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; PRE : in std_logic := 'U'; Q : out std_logic ); end component; component OR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component AO1C port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; component AXOI5 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3B port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component MX2B port( A : in std_logic := 'U'; B : in std_logic := 'U'; S : in std_logic := 'U'; Y : out std_logic ); end component; component INV port( A : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; signal un1_csn_i, m35_0, \xmit_state_i_0[4]\, \xmit_state[3]_net_1\, \xmit_state_ns[0]\, \xmit_state[2]_net_1\, N_33, N_132, \xmit_state[5]_net_1\, N_4_0, \xmit_bit_sel[0]_net_1\, \xmit_bit_sel[1]_net_1\, N_5_0, \xmit_bit_sel[2]_net_1\, N_7_0, \xmit_bit_sel[3]_net_1\, N_11_0, N_14_0, N_20_0, \xmit_state[0]_net_1\, N_21_0, N_24_0, \xmit_state_ns[5]\, N_26_0, N_27_0, \xmit_state_RNO[2]_net_1\, \TXRDY\, N_41, N_44, N_56, N_47, N_53, N_50, \tx_byte[3]_net_1\, \tx_byte[7]_net_1\, \tx_byte[1]_net_1\, \tx_byte[5]_net_1\, i0_i, i1_i, \tx_byte[2]_net_1\, \tx_byte[6]_net_1\, \tx_byte[0]_net_1\, \tx_byte[4]_net_1\, xmit_bit_sel_e0, N_64_mux, \xmit_state_ns[1]\, txrdy_int_1_sqmuxa, \GND\, \VCC\ : std_logic; begin TXRDY <= \TXRDY\; txrdy_int : DFN1E0P0 port map(D => un1_csn_i, CLK => HCLK_c, PRE => HRESETn_c, E => txrdy_int_1_sqmuxa, Q => \TXRDY\); \xmit_bit_sel_RNI5GED1[2]\ : NOR2B port map(A => N_4_0, B => \xmit_bit_sel[2]_net_1\, Y => N_5_0); \xmit_bit_sel_RNIDK9U[0]\ : NOR2B port map(A => \xmit_bit_sel[0]_net_1\, B => \xmit_bit_sel[1]_net_1\, Y => N_4_0); \xmit_state[3]\ : DFN1C0 port map(D => N_64_mux, CLK => HCLK_c, CLR => HRESETn_c, Q => \xmit_state[3]_net_1\); tx_xhdl2_RNO_3 : MX2 port map(A => N_53, B => N_50, S => \xmit_bit_sel[1]_net_1\, Y => N_47); \tx_byte[0]\ : DFN1E1C0 port map(D => tx_hold_reg(0), CLK => HCLK_c, CLR => HRESETn_c, E => N_26_0, Q => \tx_byte[0]_net_1\); \xmit_state[0]\ : DFN1C0 port map(D => \xmit_state_ns[5]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \xmit_state[0]_net_1\); \tx_byte[4]\ : DFN1E1C0 port map(D => tx_hold_reg(4), CLK => HCLK_c, CLR => HRESETn_c, E => N_26_0, Q => \tx_byte[4]_net_1\); \xmit_bit_sel_RNO[1]\ : XA1 port map(A => \xmit_bit_sel[1]_net_1\, B => \xmit_bit_sel[0]_net_1\, C => \xmit_state[2]_net_1\, Y => N_14_0); VCC_i : VCC port map(Y => \VCC\); \xmit_state_RNO_1[5]\ : MX2C port map(A => \TXRDY\, B => xmit_pulse, S => \xmit_state[0]_net_1\, Y => N_33); \tx_byte[5]\ : DFN1E1C0 port map(D => tx_hold_reg(5), CLK => HCLK_c, CLR => HRESETn_c, E => N_26_0, Q => \tx_byte[5]_net_1\); \xmit_state_RNO_0[5]\ : NOR2A port map(A => \xmit_state_i_0[4]\, B => \xmit_state[3]_net_1\, Y => m35_0); \xmit_state[5]\ : DFN1P0 port map(D => \xmit_state_ns[0]\, CLK => HCLK_c, PRE => HRESETn_c, Q => \xmit_state[5]_net_1\); \xmit_bit_sel_RNIUCJS1[3]\ : NOR2A port map(A => N_5_0, B => \xmit_bit_sel[3]_net_1\, Y => N_21_0); tx_xhdl2_RNO : MX2C port map(A => \xmit_state[3]_net_1\, B => N_44, S => \xmit_state[2]_net_1\, Y => N_41); \xmit_state_RNO[4]\ : OR2A port map(A => \xmit_state[5]_net_1\, B => \TXRDY\, Y => \xmit_state_ns[1]\); \xmit_state[2]\ : DFN1C0 port map(D => \xmit_state_RNO[2]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, Q => \xmit_state[2]_net_1\); \xmit_bit_sel[3]\ : DFN1E1C0 port map(D => N_7_0, CLK => HCLK_c, CLR => HRESETn_c, E => xmit_pulse, Q => \xmit_bit_sel[3]_net_1\); \xmit_state_RNO_0[0]\ : NOR2A port map(A => \xmit_state[0]_net_1\, B => xmit_pulse, Y => N_20_0); tx_xhdl2_RNO_1 : MX2 port map(A => N_56, B => N_47, S => \xmit_bit_sel[0]_net_1\, Y => N_44); tx_xhdl2 : DFN1E0P0 port map(D => N_41, CLK => HCLK_c, PRE => HRESETn_c, E => N_132, Q => TX_c); \xmit_bit_sel[2]\ : DFN1E1C0 port map(D => N_11_0, CLK => HCLK_c, CLR => HRESETn_c, E => xmit_pulse, Q => \xmit_bit_sel[2]_net_1\); \tx_byte[3]\ : DFN1E1C0 port map(D => tx_hold_reg(3), CLK => HCLK_c, CLR => HRESETn_c, E => N_26_0, Q => \tx_byte[3]_net_1\); \xmit_state_RNO_1[0]\ : MX2 port map(A => \xmit_state[0]_net_1\, B => N_21_0, S => xmit_pulse, Y => N_24_0); \tx_byte[7]\ : DFN1E1C0 port map(D => tx_hold_reg(7), CLK => HCLK_c, CLR => HRESETn_c, E => N_26_0, Q => \tx_byte[7]_net_1\); \xmit_state_RNIEME51[3]\ : NOR2B port map(A => \xmit_state[3]_net_1\, B => xmit_pulse, Y => N_26_0); \xmit_state_RNO[3]\ : AO1C port map(A => xmit_pulse, B => \xmit_state[3]_net_1\, C => \xmit_state_i_0[4]\, Y => N_64_mux); GND_i : GND port map(Y => \GND\); \xmit_bit_sel_RNO[2]\ : XA1 port map(A => \xmit_bit_sel[2]_net_1\, B => N_4_0, C => \xmit_state[2]_net_1\, Y => N_11_0); \xmit_state_RNO[0]\ : MX2 port map(A => N_20_0, B => N_24_0, S => \xmit_state[2]_net_1\, Y => \xmit_state_ns[5]\); \xmit_bit_sel_RNO[0]\ : AXOI5 port map(A => \xmit_state[2]_net_1\, B => xmit_pulse, C => \xmit_bit_sel[0]_net_1\, Y => xmit_bit_sel_e0); tx_xhdl2_RNO_0 : NOR3A port map(A => \xmit_state_i_0[4]\, B => \xmit_state[5]_net_1\, C => xmit_pulse, Y => N_132); tx_xhdl2_RNO_4 : MX2C port map(A => \tx_byte[0]_net_1\, B => \tx_byte[4]_net_1\, S => \xmit_bit_sel[2]_net_1\, Y => i0_i); tx_xhdl2_RNO_2 : MX2 port map(A => i0_i, B => i1_i, S => \xmit_bit_sel[1]_net_1\, Y => N_56); \xmit_state_RNO[5]\ : NOR3A port map(A => m35_0, B => \xmit_state[2]_net_1\, C => N_33, Y => \xmit_state_ns[0]\); tx_xhdl2_RNO_5 : MX2C port map(A => \tx_byte[2]_net_1\, B => \tx_byte[6]_net_1\, S => \xmit_bit_sel[2]_net_1\, Y => i1_i); \tx_byte[6]\ : DFN1E1C0 port map(D => tx_hold_reg(6), CLK => HCLK_c, CLR => HRESETn_c, E => N_26_0, Q => \tx_byte[6]_net_1\); \xmit_bit_sel[1]\ : DFN1E1C0 port map(D => N_14_0, CLK => HCLK_c, CLR => HRESETn_c, E => xmit_pulse, Q => \xmit_bit_sel[1]_net_1\); \xmit_state_RNO_0[2]\ : NOR3B port map(A => xmit_pulse, B => N_21_0, C => \xmit_state[3]_net_1\, Y => N_27_0); \xmit_bit_sel[0]\ : DFN1C0 port map(D => xmit_bit_sel_e0, CLK => HCLK_c, CLR => HRESETn_c, Q => \xmit_bit_sel[0]_net_1\); \xmit_state_RNO[2]\ : MX2B port map(A => N_26_0, B => N_27_0, S => \xmit_state[2]_net_1\, Y => \xmit_state_RNO[2]_net_1\); \tx_byte[2]\ : DFN1E1C0 port map(D => tx_hold_reg(2), CLK => HCLK_c, CLR => HRESETn_c, E => N_26_0, Q => \tx_byte[2]_net_1\); txrdy_int_RNO : INV port map(A => un1_csn, Y => un1_csn_i); tx_xhdl2_RNO_7 : MX2C port map(A => \tx_byte[3]_net_1\, B => \tx_byte[7]_net_1\, S => \xmit_bit_sel[2]_net_1\, Y => N_50); \tx_byte[1]\ : DFN1E1C0 port map(D => tx_hold_reg(1), CLK => HCLK_c, CLR => HRESETn_c, E => N_26_0, Q => \tx_byte[1]_net_1\); \xmit_state[4]\ : DFN1P0 port map(D => \xmit_state_ns[1]\, CLK => HCLK_c, PRE => HRESETn_c, Q => \xmit_state_i_0[4]\); \xmit_bit_sel_RNO[3]\ : XA1 port map(A => \xmit_bit_sel[3]_net_1\, B => N_5_0, C => \xmit_state[2]_net_1\, Y => N_7_0); txrdy_int_RNO_0 : NOR2 port map(A => N_26_0, B => un1_csn, Y => txrdy_int_1_sqmuxa); tx_xhdl2_RNO_6 : MX2C port map(A => \tx_byte[1]_net_1\, B => \tx_byte[5]_net_1\, S => \xmit_bit_sel[2]_net_1\, Y => N_53); end DEF_ARCH; library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity top_CoreUARTapb_0_Clock_gen is port( HRESETn_c : in std_logic; HCLK_c : in std_logic; baud_clock : out std_logic; xmit_pulse : out std_logic ); end top_CoreUARTapb_0_Clock_gen; architecture DEF_ARCH of top_CoreUARTapb_0_Clock_gen is component OR3 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2B port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; Q : out std_logic ); end component; component AX1C port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component XNOR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1E1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; E : in std_logic := 'U'; Q : out std_logic ); end component; component NOR3A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component OR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component XOR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component NOR3 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3C port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; component OR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; signal N_12, \baud_cntr[1]_net_1\, \baud_cntr[0]_net_1\, N_10, \baud_cntr[3]_net_1\, \DWACT_FDEC_E[0]\, N_5, \baud_cntr[8]_net_1\, \DWACT_FDEC_E[4]\, N_2, \DWACT_FDEC_E[7]\, \DWACT_FDEC_E[6]\, un2_baud_cntr_9, un2_baud_cntr_6, \baud_cntr[9]_net_1\, un2_baud_cntr_8, un2_baud_cntr_4, \baud_cntr[4]_net_1\, un2_baud_cntr_7, un2_baud_cntr_2, \baud_cntr[5]_net_1\, \baud_cntr[2]_net_1\, \baud_cntr[11]_net_1\, \baud_cntr[12]_net_1\, \baud_cntr[6]_net_1\, \baud_cntr[7]_net_1\, \baud_cntr[10]_net_1\, un2_baud_cntr, un8_baud_clock_int, \xmit_cntr[2]_net_1\, \xmit_cntr[3]_net_1\, xmit_cntr_c1, \baud_clock\, \xmit_clock\, xmit_cntr_n1, \xmit_cntr[0]_net_1\, \xmit_cntr[1]_net_1\, xmit_cntr_n2, xmit_cntr_n3, xmit_cntr_e0, \baud_cntr_4[12]\, \baud_cntr_3[12]\, \baud_cntr_4[11]\, \baud_cntr_3[11]\, \baud_cntr_4[10]\, \baud_cntr_3[10]\, \baud_cntr_4[9]\, \baud_cntr_3[9]\, \baud_cntr_4[8]\, \baud_cntr_3[8]\, \baud_cntr_4[7]\, \baud_cntr_3[7]\, \baud_cntr_4[6]\, \baud_cntr_3[6]\, \baud_cntr_4[5]\, \baud_cntr_3[5]\, \baud_cntr_4[4]\, \baud_cntr_3[4]\, \baud_cntr_4[3]\, \baud_cntr_3[3]\, \baud_cntr_4[2]\, \baud_cntr_3[2]\, \baud_cntr_4[1]\, \baud_cntr_3[1]\, \baud_cntr_4[0]\, N_3, \DWACT_FDEC_E[2]\, \DWACT_FDEC_E[5]\, N_4, \DWACT_FDEC_E[3]\, N_6, N_7, N_8, \DWACT_FDEC_E[1]\, N_9, N_11, \GND\, \VCC\ : std_logic; begin baud_clock <= \baud_clock\; \UG10.make_baud_cntr2.baud_cntr_3_I_19\ : OR3 port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C => \baud_cntr[6]_net_1\, Y => N_7); xmit_clock_RNIMD3T : NOR2B port map(A => \baud_clock\, B => \xmit_clock\, Y => xmit_pulse); \baud_cntr[7]\ : DFN1C0 port map(D => \baud_cntr_4[7]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \baud_cntr[7]_net_1\); \xmit_cntr_RNO[3]\ : AX1C port map(A => \xmit_cntr[2]_net_1\, B => xmit_cntr_c1, C => \xmit_cntr[3]_net_1\, Y => xmit_cntr_n3); \UG10.make_baud_cntr2.baud_cntr_3_I_5\ : XNOR2 port map(A => \baud_cntr[0]_net_1\, B => \baud_cntr[1]_net_1\, Y => \baud_cntr_3[1]\); \baud_cntr[0]\ : DFN1C0 port map(D => \baud_cntr_4[0]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \baud_cntr[0]_net_1\); \baud_cntr_RNO[7]\ : NOR2A port map(A => \baud_cntr_3[7]\, B => un2_baud_cntr, Y => \baud_cntr_4[7]\); \baud_cntr[9]\ : DFN1C0 port map(D => \baud_cntr_4[9]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \baud_cntr[9]_net_1\); \xmit_cntr[3]\ : DFN1E1C0 port map(D => xmit_cntr_n3, CLK => HCLK_c, CLR => HRESETn_c, E => \baud_clock\, Q => \xmit_cntr[3]_net_1\); \UG10.make_baud_cntr2.baud_cntr_3_I_13\ : OR3 port map(A => \DWACT_FDEC_E[0]\, B => \baud_cntr[3]_net_1\, C => \baud_cntr[4]_net_1\, Y => N_9); \baud_cntr_RNINP0G1[2]\ : NOR3A port map(A => un2_baud_cntr_2, B => \baud_cntr[5]_net_1\, C => \baud_cntr[2]_net_1\, Y => un2_baud_cntr_7); \baud_cntr_RNI434N[10]\ : NOR2 port map(A => \baud_cntr[7]_net_1\, B => \baud_cntr[10]_net_1\, Y => un2_baud_cntr_2); \UG10.make_baud_cntr2.baud_cntr_3_I_33\ : OR3 port map(A => \baud_cntr[9]_net_1\, B => \baud_cntr[10]_net_1\, C => \baud_cntr[11]_net_1\, Y => \DWACT_FDEC_E[7]\); \UG10.make_baud_cntr2.baud_cntr_3_I_24\ : OR3 port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C => \DWACT_FDEC_E[3]\, Y => \DWACT_FDEC_E[4]\); \baud_cntr_RNO[1]\ : NOR2A port map(A => \baud_cntr_3[1]\, B => un2_baud_cntr, Y => \baud_cntr_4[1]\); \UG10.make_baud_cntr2.baud_cntr_3_I_25\ : OR2 port map(A => \baud_cntr[8]_net_1\, B => \DWACT_FDEC_E[4]\, Y => N_5); \xmit_cntr_RNO[2]\ : XOR2 port map(A => xmit_cntr_c1, B => \xmit_cntr[2]_net_1\, Y => xmit_cntr_n2); \UG10.make_baud_cntr2.baud_cntr_3_I_26\ : XNOR2 port map(A => N_5, B => \baud_cntr[9]_net_1\, Y => \baud_cntr_3[9]\); \UG10.make_baud_cntr2.baud_cntr_3_I_12\ : XNOR2 port map(A => N_10, B => \baud_cntr[4]_net_1\, Y => \baud_cntr_3[4]\); \UG10.make_baud_cntr2.baud_cntr_3_I_32\ : XNOR2 port map(A => N_3, B => \baud_cntr[11]_net_1\, Y => \baud_cntr_3[11]\); \UG10.make_baud_cntr2.baud_cntr_3_I_21\ : OR2 port map(A => \baud_cntr[6]_net_1\, B => \baud_cntr[7]_net_1\, Y => \DWACT_FDEC_E[3]\); VCC_i : VCC port map(Y => \VCC\); \baud_cntr_RNO[12]\ : NOR2A port map(A => \baud_cntr_3[12]\, B => un2_baud_cntr, Y => \baud_cntr_4[12]\); \UG10.make_baud_cntr2.baud_cntr_3_I_27\ : OR3 port map(A => \DWACT_FDEC_E[4]\, B => \baud_cntr[8]_net_1\, C => \baud_cntr[9]_net_1\, Y => N_4); \baud_cntr_RNIAMP11[12]\ : NOR3 port map(A => \baud_cntr[11]_net_1\, B => \baud_cntr[12]_net_1\, C => \baud_cntr[3]_net_1\, Y => un2_baud_cntr_6); \UG10.make_baud_cntr2.baud_cntr_3_I_29\ : OR3 port map(A => \baud_cntr[6]_net_1\, B => \baud_cntr[7]_net_1\, C => \baud_cntr[8]_net_1\, Y => \DWACT_FDEC_E[5]\); \baud_cntr_RNO[9]\ : NOR2A port map(A => \baud_cntr_3[9]\, B => un2_baud_cntr, Y => \baud_cntr_4[9]\); \baud_cntr_RNI1RGS4[1]\ : NOR3C port map(A => un2_baud_cntr_8, B => un2_baud_cntr_7, C => un2_baud_cntr_9, Y => un2_baud_cntr); xmit_clock_RNO : NOR3C port map(A => \xmit_cntr[2]_net_1\, B => \xmit_cntr[3]_net_1\, C => xmit_cntr_c1, Y => un8_baud_clock_int); \UG10.make_baud_cntr2.baud_cntr_3_I_23\ : XNOR2 port map(A => N_6, B => \baud_cntr[8]_net_1\, Y => \baud_cntr_3[8]\); \UG10.make_baud_cntr2.baud_cntr_3_I_8\ : OR3 port map(A => \baud_cntr[0]_net_1\, B => \baud_cntr[1]_net_1\, C => \baud_cntr[2]_net_1\, Y => N_11); \xmit_cntr_RNO[1]\ : XOR2 port map(A => \xmit_cntr[0]_net_1\, B => \xmit_cntr[1]_net_1\, Y => xmit_cntr_n1); \UG10.make_baud_cntr2.baud_cntr_3_I_22\ : OR3 port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C => \DWACT_FDEC_E[3]\, Y => N_6); \baud_cntr[5]\ : DFN1C0 port map(D => \baud_cntr_4[5]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \baud_cntr[5]_net_1\); \UG10.make_baud_cntr2.baud_cntr_3_I_10\ : OR3 port map(A => \baud_cntr[0]_net_1\, B => \baud_cntr[1]_net_1\, C => \baud_cntr[2]_net_1\, Y => \DWACT_FDEC_E[0]\); \UG10.make_baud_cntr2.baud_cntr_3_I_30\ : OR3 port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[2]\, C => \DWACT_FDEC_E[5]\, Y => \DWACT_FDEC_E[6]\); \baud_cntr[3]\ : DFN1C0 port map(D => \baud_cntr_4[3]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \baud_cntr[3]_net_1\); \baud_cntr_RNO[5]\ : NOR2A port map(A => \baud_cntr_3[5]\, B => un2_baud_cntr, Y => \baud_cntr_4[5]\); \baud_cntr[2]\ : DFN1C0 port map(D => \baud_cntr_4[2]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \baud_cntr[2]_net_1\); \UG10.make_baud_cntr2.baud_cntr_3_I_18\ : OR3 port map(A => \baud_cntr[3]_net_1\, B => \baud_cntr[4]_net_1\, C => \baud_cntr[5]_net_1\, Y => \DWACT_FDEC_E[2]\); GND_i : GND port map(Y => \GND\); \baud_cntr_RNO[10]\ : NOR2A port map(A => \baud_cntr_3[10]\, B => un2_baud_cntr, Y => \baud_cntr_4[10]\); \baud_cntr[10]\ : DFN1C0 port map(D => \baud_cntr_4[10]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \baud_cntr[10]_net_1\); \xmit_cntr_RNO[0]\ : XOR2 port map(A => \xmit_cntr[0]_net_1\, B => \baud_clock\, Y => xmit_cntr_e0); \baud_cntr[11]\ : DFN1C0 port map(D => \baud_cntr_4[11]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \baud_cntr[11]_net_1\); \UG10.make_baud_cntr2.baud_cntr_3_I_20\ : XNOR2 port map(A => N_7, B => \baud_cntr[7]_net_1\, Y => \baud_cntr_3[7]\); \baud_cntr_RNIBIPH1[1]\ : NOR3A port map(A => un2_baud_cntr_4, B => \baud_cntr[4]_net_1\, C => \baud_cntr[1]_net_1\, Y => un2_baud_cntr_8); \baud_cntr[6]\ : DFN1C0 port map(D => \baud_cntr_4[6]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \baud_cntr[6]_net_1\); \baud_cntr_RNIVEMQ1[9]\ : NOR3A port map(A => un2_baud_cntr_6, B => \baud_cntr[0]_net_1\, C => \baud_cntr[9]_net_1\, Y => un2_baud_cntr_9); \baud_cntr[4]\ : DFN1C0 port map(D => \baud_cntr_4[4]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \baud_cntr[4]_net_1\); \baud_cntr_RNIQTSO[6]\ : NOR2 port map(A => \baud_cntr[6]_net_1\, B => \baud_cntr[8]_net_1\, Y => un2_baud_cntr_4); \xmit_cntr[2]\ : DFN1E1C0 port map(D => xmit_cntr_n2, CLK => HCLK_c, CLR => HRESETn_c, E => \baud_clock\, Q => \xmit_cntr[2]_net_1\); \UG10.make_baud_cntr2.baud_cntr_3_I_9\ : XNOR2 port map(A => N_11, B => \baud_cntr[3]_net_1\, Y => \baud_cntr_3[3]\); \baud_cntr_RNO[11]\ : NOR2A port map(A => \baud_cntr_3[11]\, B => un2_baud_cntr, Y => \baud_cntr_4[11]\); \UG10.make_baud_cntr2.baud_cntr_3_I_7\ : XNOR2 port map(A => N_12, B => \baud_cntr[2]_net_1\, Y => \baud_cntr_3[2]\); \baud_cntr_RNO[6]\ : NOR2A port map(A => \baud_cntr_3[6]\, B => un2_baud_cntr, Y => \baud_cntr_4[6]\); \UG10.make_baud_cntr2.baud_cntr_3_I_28\ : XNOR2 port map(A => N_4, B => \baud_cntr[10]_net_1\, Y => \baud_cntr_3[10]\); \baud_cntr_RNO[0]\ : OR2A port map(A => \baud_cntr[0]_net_1\, B => un2_baud_cntr, Y => \baud_cntr_4[0]\); \xmit_cntr_RNIPE04[1]\ : NOR2B port map(A => \xmit_cntr[1]_net_1\, B => \xmit_cntr[0]_net_1\, Y => xmit_cntr_c1); \baud_cntr_RNO[3]\ : NOR2A port map(A => \baud_cntr_3[3]\, B => un2_baud_cntr, Y => \baud_cntr_4[3]\); \baud_cntr[1]\ : DFN1C0 port map(D => \baud_cntr_4[1]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \baud_cntr[1]_net_1\); \UG10.make_baud_cntr2.baud_cntr_3_I_6\ : OR2 port map(A => \baud_cntr[1]_net_1\, B => \baud_cntr[0]_net_1\, Y => N_12); xmit_clock : DFN1E1C0 port map(D => un8_baud_clock_int, CLK => HCLK_c, CLR => HRESETn_c, E => \baud_clock\, Q => \xmit_clock\); \baud_cntr_RNO[4]\ : NOR2A port map(A => \baud_cntr_3[4]\, B => un2_baud_cntr, Y => \baud_cntr_4[4]\); \UG10.make_baud_cntr2.baud_cntr_3_I_14\ : XNOR2 port map(A => N_9, B => \baud_cntr[5]_net_1\, Y => \baud_cntr_3[5]\); baud_clock_int : DFN1C0 port map(D => un2_baud_cntr, CLK => HCLK_c, CLR => HRESETn_c, Q => \baud_clock\); \UG10.make_baud_cntr2.baud_cntr_3_I_34\ : OR2 port map(A => \DWACT_FDEC_E[7]\, B => \DWACT_FDEC_E[6]\, Y => N_2); \xmit_cntr[1]\ : DFN1E1C0 port map(D => xmit_cntr_n1, CLK => HCLK_c, CLR => HRESETn_c, E => \baud_clock\, Q => \xmit_cntr[1]_net_1\); \UG10.make_baud_cntr2.baud_cntr_3_I_15\ : OR2 port map(A => \baud_cntr[3]_net_1\, B => \baud_cntr[4]_net_1\, Y => \DWACT_FDEC_E[1]\); \UG10.make_baud_cntr2.baud_cntr_3_I_35\ : XNOR2 port map(A => N_2, B => \baud_cntr[12]_net_1\, Y => \baud_cntr_3[12]\); \baud_cntr[12]\ : DFN1C0 port map(D => \baud_cntr_4[12]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \baud_cntr[12]_net_1\); \UG10.make_baud_cntr2.baud_cntr_3_I_16\ : OR3 port map(A => \DWACT_FDEC_E[0]\, B => \DWACT_FDEC_E[1]\, C => \baud_cntr[5]_net_1\, Y => N_8); \xmit_cntr[0]\ : DFN1C0 port map(D => xmit_cntr_e0, CLK => HCLK_c, CLR => HRESETn_c, Q => \xmit_cntr[0]_net_1\); \baud_cntr_RNO[2]\ : NOR2A port map(A => \baud_cntr_3[2]\, B => un2_baud_cntr, Y => \baud_cntr_4[2]\); \UG10.make_baud_cntr2.baud_cntr_3_I_11\ : OR2 port map(A => \baud_cntr[3]_net_1\, B => \DWACT_FDEC_E[0]\, Y => N_10); \UG10.make_baud_cntr2.baud_cntr_3_I_31\ : OR3 port map(A => \DWACT_FDEC_E[6]\, B => \baud_cntr[9]_net_1\, C => \baud_cntr[10]_net_1\, Y => N_3); \UG10.make_baud_cntr2.baud_cntr_3_I_17\ : XNOR2 port map(A => N_8, B => \baud_cntr[6]_net_1\, Y => \baud_cntr_3[6]\); \baud_cntr_RNO[8]\ : NOR2A port map(A => \baud_cntr_3[8]\, B => un2_baud_cntr, Y => \baud_cntr_4[8]\); \baud_cntr[8]\ : DFN1C0 port map(D => \baud_cntr_4[8]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \baud_cntr[8]_net_1\); end DEF_ARCH; library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity top_CoreUARTapb_0_Rx_async is port( data_out : out std_logic_vector(7 downto 0); OVERFLOW : out std_logic; FRAMING_ERR : out std_logic; stop_strobe : out std_logic; un1_temp_xhdl10_i : in std_logic; HRESETn_c : in std_logic; HCLK_c : in std_logic; PARITY_ERR : out std_logic; CoreAPB_0_APBmslave0_PENABLE : in std_logic; un1_temp_xhdl10 : in std_logic; N_3_0 : in std_logic; m6_0 : in std_logic; N_84_mux : out std_logic; baud_clock : in std_logic; receive_full : out std_logic ); end top_CoreUARTapb_0_Rx_async; architecture DEF_ARCH of top_CoreUARTapb_0_Rx_async is component MX2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; S : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1E1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; E : in std_logic := 'U'; Q : out std_logic ); end component; component NOR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; Q : out std_logic ); end component; component NOR2B port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1E0C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; E : in std_logic := 'U'; Q : out std_logic ); end component; component OR3A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component OR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component AO1 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component NOR3B port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component OA1A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component XA1B port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1P0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; PRE : in std_logic := 'U'; Q : out std_logic ); end component; component MX2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; S : in std_logic := 'U'; Y : out std_logic ); end component; component OAI1 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component AO18 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; component OR2B port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component AXOI4 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component MX2B port( A : in std_logic := 'U'; B : in std_logic := 'U'; S : in std_logic := 'U'; Y : out std_logic ); end component; component AO1D port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component MX2C port( A : in std_logic := 'U'; B : in std_logic := 'U'; S : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3C port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component OR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1E1P0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; PRE : in std_logic := 'U'; E : in std_logic := 'U'; Q : out std_logic ); end component; component XA1 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component XNOR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; signal m65_e_2, \rx_bit_cnt[3]_net_1\, m65_e_1, \rx_bit_cnt[2]_net_1\, \rx_bit_cnt[1]_net_1\, \rx_bit_cnt[0]_net_1\, m24_1, \rx_state[1]_net_1\, \receive_count[3]_net_1\, \rx_state[0]_net_1\, m63_0, \receive_full\, un47_baud_clock_NE_1, m22_0, m6_0_1, \receive_count[1]_net_1\, m6_0_0, \receive_count[2]_net_1\, \receive_count[0]_net_1\, overflow_int_3, un47_baud_clock_i, rx_byte_xhdl5_1_sqmuxa, N_7_0, N_12_0, N_41_mux, N_38_mux, N_40_mux, N_86, framing_error_int_0_sqmuxa, i1_mux, N_78, \rx_shift_12[5]\, \rx_shift[6]_net_1\, N_82, N_82_mux, parity_err_xhdl2_9, \PARITY_ERR\, \rx_shift_12[1]\, \rx_shift[2]_net_1\, \rx_shift_12[0]\, \rx_shift[1]_net_1\, un1_framing_error_i4, framing_error_i_0_sqmuxa, \framing_error_int\, overflow_xhdl1_1_sqmuxa, N_72, \overflow_int\, \samples[1]_net_1\, \samples_i_0[0]\, \samples[2]_net_1\, \samples_RNO[2]_net_1\, \samples_RNO[0]_net_1\, \samples_RNO[1]_net_1\, N_14_i, N_13_0, rx_bit_cnt_n2, N_337, rx_bit_cnt_n3, N_14_0, N_92_mux, N_92, \rx_shift_12[6]\, \rx_shift[7]_net_1\, \rx_shift_12[4]\, \rx_shift[5]_net_1\, \rx_shift_12[3]\, \rx_shift[4]_net_1\, \rx_shift_12[2]\, \rx_shift[3]_net_1\, rx_bit_cnt_n1, N_21, N_341, \last_bit[0]_net_1\, N_329, N_9_0, N_34, N_11_i, N_12_i, framing_error_int_2_sqmuxa, N_33, N_91_mux, N_40, N_258, N_43, N_46, i14_mux, receive_count_e0, N_28, N_347, N_85_mux, \rx_shift[0]_net_1\, \GND\, \VCC\ : std_logic; begin PARITY_ERR <= \PARITY_ERR\; receive_full <= \receive_full\; \rx_state_RNO_1[0]\ : MX2 port map(A => N_14_i, B => N_33, S => \rx_state[0]_net_1\, Y => N_34); \rx_byte_xhdl5[0]\ : DFN1E1C0 port map(D => \rx_shift[0]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, E => rx_byte_xhdl5_1_sqmuxa, Q => data_out(0)); parity_err_xhdl2_RNIO8S9 : NOR2A port map(A => CoreAPB_0_APBmslave0_PENABLE, B => \PARITY_ERR\, Y => N_78); overflow_int : DFN1E1C0 port map(D => overflow_int_3, CLK => HCLK_c, CLR => HRESETn_c, E => baud_clock, Q => \overflow_int\); \rx_shift_RNO[5]\ : NOR2A port map(A => \rx_shift[6]_net_1\, B => N_82, Y => \rx_shift_12[5]\); \rx_bit_cnt_RNIRKEI_0[1]\ : NOR2 port map(A => \rx_bit_cnt[1]_net_1\, B => \rx_bit_cnt[0]_net_1\, Y => m65_e_1); \samples[0]\ : DFN1C0 port map(D => \samples_RNO[0]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, Q => \samples_i_0[0]\); \rx_state_RNO_2[0]\ : NOR2B port map(A => N_91_mux, B => \rx_state[1]_net_1\, Y => N_33); \rx_shift[2]\ : DFN1E0C0 port map(D => \rx_shift_12[2]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_92_mux, Q => \rx_shift[2]_net_1\); \rx_byte_xhdl5[6]\ : DFN1E1C0 port map(D => \rx_shift[6]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, E => rx_byte_xhdl5_1_sqmuxa, Q => data_out(6)); \rx_state_RNI8MII[0]\ : NOR2A port map(A => baud_clock, B => \rx_state[0]_net_1\, Y => m22_0); \rx_bit_cnt_RNIT3MR[3]\ : OR3A port map(A => \rx_bit_cnt[3]_net_1\, B => \rx_bit_cnt[1]_net_1\, C => \rx_bit_cnt[2]_net_1\, Y => un47_baud_clock_NE_1); \rx_shift_RNO[3]\ : NOR2A port map(A => \rx_shift[4]_net_1\, B => N_82, Y => \rx_shift_12[3]\); \receive_count_RNINPCM[2]\ : NOR2B port map(A => N_11_i, B => \receive_count[2]_net_1\, Y => N_12_i); \receive_count[1]\ : DFN1E1C0 port map(D => N_46, CLK => HCLK_c, CLR => HRESETn_c, E => baud_clock, Q => \receive_count[1]_net_1\); \rx_state_RNO_0[1]\ : NOR2B port map(A => \rx_state[0]_net_1\, B => baud_clock, Y => N_347); \rx_shift[7]\ : DFN1E0C0 port map(D => N_82_mux, CLK => HCLK_c, CLR => HRESETn_c, E => N_92_mux, Q => \rx_shift[7]_net_1\); overflow_xhdl1_RNO : NOR2 port map(A => N_72, B => un1_temp_xhdl10, Y => overflow_xhdl1_1_sqmuxa); \rx_shift[0]\ : DFN1E0C0 port map(D => \rx_shift_12[0]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_92_mux, Q => \rx_shift[0]_net_1\); \last_bit_RNITELD1[0]\ : OR2A port map(A => N_12_0, B => un47_baud_clock_NE_1, Y => un47_baud_clock_i); receive_full_int_RNO : AO1 port map(A => N_7_0, B => m65_e_2, C => un1_temp_xhdl10, Y => N_85_mux); \rx_state_RNIRGPT2[1]\ : MX2 port map(A => N_28, B => N_40_mux, S => \rx_state[1]_net_1\, Y => N_258); \receive_count_RNIQRTE[2]\ : NOR2 port map(A => \receive_count[2]_net_1\, B => \receive_count[0]_net_1\, Y => m6_0_0); VCC_i : VCC port map(Y => \VCC\); framing_error_i : DFN1E0C0 port map(D => framing_error_i_0_sqmuxa, CLK => HCLK_c, CLR => HRESETn_c, E => un1_framing_error_i4, Q => FRAMING_ERR); \rx_shift_RNO[1]\ : NOR2A port map(A => \rx_shift[2]_net_1\, B => N_82, Y => \rx_shift_12[1]\); \rx_byte_xhdl5[7]\ : DFN1E1C0 port map(D => \rx_shift[7]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, E => rx_byte_xhdl5_1_sqmuxa, Q => data_out(7)); \receive_count[3]\ : DFN1E1C0 port map(D => N_40, CLK => HCLK_c, CLR => HRESETn_c, E => baud_clock, Q => \receive_count[3]_net_1\); stop_strobe_i_RNO : NOR2A port map(A => N_14_i, B => \rx_state[0]_net_1\, Y => framing_error_int_2_sqmuxa); \receive_count_RNIHN511[3]\ : NOR3B port map(A => \rx_state[0]_net_1\, B => N_86, C => \receive_count[3]_net_1\, Y => N_40_mux); \rx_shift_RNO[2]\ : NOR2A port map(A => \rx_shift[3]_net_1\, B => N_82, Y => \rx_shift_12[2]\); \rx_bit_cnt[2]\ : DFN1E0C0 port map(D => rx_bit_cnt_n2, CLK => HCLK_c, CLR => HRESETn_c, E => N_92_mux, Q => \rx_bit_cnt[2]_net_1\); framing_error_int_RNID1OO : NOR2B port map(A => \framing_error_int\, B => baud_clock, Y => framing_error_i_0_sqmuxa); \rx_bit_cnt[1]\ : DFN1E0C0 port map(D => rx_bit_cnt_n1, CLK => HCLK_c, CLR => HRESETn_c, E => N_92_mux, Q => \rx_bit_cnt[1]_net_1\); \receive_count_RNIMPRT[1]\ : NOR2B port map(A => m6_0_1, B => m6_0_0, Y => N_38_mux); \receive_count_RNIB6D31[3]\ : OA1A port map(A => N_86, B => \receive_count[3]_net_1\, C => i1_mux, Y => N_91_mux); \receive_count_RNIPQTE[1]\ : NOR2B port map(A => \receive_count[1]_net_1\, B => \receive_count[0]_net_1\, Y => N_11_i); \rx_bit_cnt_RNO[0]\ : NOR2A port map(A => N_92, B => \rx_bit_cnt[0]_net_1\, Y => N_21); \receive_count_RNO[2]\ : XA1B port map(A => \receive_count[2]_net_1\, B => N_11_i, C => N_258, Y => N_43); \samples[1]\ : DFN1P0 port map(D => \samples_RNO[1]_net_1\, CLK => HCLK_c, PRE => HRESETn_c, Q => \samples[1]_net_1\); \rx_state_RNINSJ6[1]\ : NOR2 port map(A => \rx_state[0]_net_1\, B => \rx_state[1]_net_1\, Y => N_82); \rx_shift_RNO[6]\ : NOR2A port map(A => \rx_shift[7]_net_1\, B => N_82, Y => \rx_shift_12[6]\); \rx_state_RNO[1]\ : MX2A port map(A => un47_baud_clock_i, B => N_91_mux, S => \rx_state[1]_net_1\, Y => i14_mux); \rx_shift_RNO[0]\ : NOR2A port map(A => \rx_shift[1]_net_1\, B => N_82, Y => \rx_shift_12[0]\); \rx_bit_cnt_RNO[2]\ : XA1B port map(A => \rx_bit_cnt[2]_net_1\, B => N_337, C => N_82, Y => rx_bit_cnt_n2); \receive_count_RNIMPRT[3]\ : NOR2B port map(A => N_12_i, B => \receive_count[3]_net_1\, Y => N_13_0); \receive_count_RNIQEOJ1[3]\ : OAI1 port map(A => N_82, B => N_13_0, C => baud_clock, Y => N_92_mux); \receive_count[2]\ : DFN1E1C0 port map(D => N_43, CLK => HCLK_c, CLR => HRESETn_c, E => baud_clock, Q => \receive_count[2]_net_1\); stop_strobe_i : DFN1E1C0 port map(D => framing_error_int_2_sqmuxa, CLK => HCLK_c, CLR => HRESETn_c, E => baud_clock, Q => stop_strobe); \rx_state[1]\ : DFN1E1C0 port map(D => i14_mux, CLK => HCLK_c, CLR => HRESETn_c, E => N_347, Q => \rx_state[1]_net_1\); \rx_shift_RNO[7]\ : NOR2 port map(A => i1_mux, B => N_82, Y => N_82_mux); \receive_count_RNO[1]\ : XA1B port map(A => \receive_count[0]_net_1\, B => \receive_count[1]_net_1\, C => N_258, Y => N_46); \samples_RNILCH5[0]\ : AO18 port map(A => \samples[1]_net_1\, B => \samples_i_0[0]\, C => \samples[2]_net_1\, Y => i1_mux); \rx_shift[4]\ : DFN1E0C0 port map(D => \rx_shift_12[4]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_92_mux, Q => \rx_shift[4]_net_1\); \last_bit_RNO[0]\ : NOR2A port map(A => \last_bit[0]_net_1\, B => \rx_state[1]_net_1\, Y => N_341); \rx_state_RNIIO511[1]\ : NOR2B port map(A => N_13_0, B => \rx_state[1]_net_1\, Y => N_14_i); receive_full_int_RNI92452 : NOR3A port map(A => N_7_0, B => \receive_full\, C => un47_baud_clock_i, Y => rx_byte_xhdl5_1_sqmuxa); overflow_int_RNO_0 : NOR3B port map(A => \rx_state[0]_net_1\, B => \receive_full\, C => \rx_state[1]_net_1\, Y => m63_0); GND_i : GND port map(Y => \GND\); \receive_count_RNO[3]\ : XA1B port map(A => \receive_count[3]_net_1\, B => N_12_i, C => N_258, Y => N_40); \rx_state_RNIUFEG1[0]\ : OR2B port map(A => m22_0, B => N_38_mux, Y => N_41_mux); framing_error_int_RNO_0 : NOR3B port map(A => \rx_state[1]_net_1\, B => \receive_count[3]_net_1\, C => \rx_state[0]_net_1\, Y => m24_1); receive_full_int : DFN1E1C0 port map(D => un1_temp_xhdl10_i, CLK => HCLK_c, CLR => HRESETn_c, E => N_85_mux, Q => \receive_full\); \rx_state_RNI4LSL_0[1]\ : NOR2A port map(A => baud_clock, B => N_82, Y => N_92); framing_error_i_RNO : NOR2 port map(A => framing_error_i_0_sqmuxa, B => un1_temp_xhdl10, Y => un1_framing_error_i4); \receive_count_RNO[0]\ : AXOI4 port map(A => N_258, B => baud_clock, C => \receive_count[0]_net_1\, Y => receive_count_e0); parity_err_xhdl2 : DFN1E1C0 port map(D => parity_err_xhdl2_9, CLK => HCLK_c, CLR => HRESETn_c, E => un1_temp_xhdl10, Q => \PARITY_ERR\); \samples_RNO[0]\ : MX2B port map(A => \samples_i_0[0]\, B => \samples[1]_net_1\, S => baud_clock, Y => \samples_RNO[0]_net_1\); \rx_byte_xhdl5[4]\ : DFN1E1C0 port map(D => \rx_shift[4]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, E => rx_byte_xhdl5_1_sqmuxa, Q => data_out(4)); \rx_shift[6]\ : DFN1E0C0 port map(D => \rx_shift_12[6]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_92_mux, Q => \rx_shift[6]_net_1\); \rx_state_RNO[0]\ : AO1D port map(A => N_9_0, B => \rx_state[1]_net_1\, C => N_34, Y => N_329); \rx_shift_RNO[4]\ : NOR2A port map(A => \rx_shift[5]_net_1\, B => N_82, Y => \rx_shift_12[4]\); \rx_shift[1]\ : DFN1E0C0 port map(D => \rx_shift_12[1]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_92_mux, Q => \rx_shift[1]_net_1\); \rx_shift[3]\ : DFN1E0C0 port map(D => \rx_shift_12[3]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_92_mux, Q => \rx_shift[3]_net_1\); framing_error_int : DFN1E1C0 port map(D => framing_error_int_0_sqmuxa, CLK => HCLK_c, CLR => HRESETn_c, E => baud_clock, Q => \framing_error_int\); \rx_byte_xhdl5[2]\ : DFN1E1C0 port map(D => \rx_shift[2]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, E => rx_byte_xhdl5_1_sqmuxa, Q => data_out(2)); \rx_state[0]\ : DFN1E1C0 port map(D => N_329, CLK => HCLK_c, CLR => HRESETn_c, E => baud_clock, Q => \rx_state[0]_net_1\); \samples[2]\ : DFN1P0 port map(D => \samples_RNO[2]_net_1\, CLK => HCLK_c, PRE => HRESETn_c, Q => \samples[2]_net_1\); overflow_xhdl1_RNO_0 : NOR2B port map(A => \overflow_int\, B => baud_clock, Y => N_72); \receive_count_RNISTTE[1]\ : NOR2A port map(A => \receive_count[3]_net_1\, B => \receive_count[1]_net_1\, Y => m6_0_1); \receive_count[0]\ : DFN1C0 port map(D => receive_count_e0, CLK => HCLK_c, CLR => HRESETn_c, Q => \receive_count[0]_net_1\); parity_err_xhdl2_RNO : NOR3A port map(A => m65_e_2, B => un1_temp_xhdl10, C => i1_mux, Y => parity_err_xhdl2_9); \rx_state_RNIEQ9P1[0]\ : MX2C port map(A => \rx_state[0]_net_1\, B => N_41_mux, S => i1_mux, Y => N_28); \rx_byte_xhdl5[3]\ : DFN1E1C0 port map(D => \rx_shift[3]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, E => rx_byte_xhdl5_1_sqmuxa, Q => data_out(3)); \rx_bit_cnt_RNIRKEI[1]\ : NOR2B port map(A => \rx_bit_cnt[0]_net_1\, B => \rx_bit_cnt[1]_net_1\, Y => N_337); framing_error_int_RNO : NOR3C port map(A => N_86, B => m24_1, C => i1_mux, Y => framing_error_int_0_sqmuxa); \samples_RNO[2]\ : OR2 port map(A => \samples[2]_net_1\, B => baud_clock, Y => \samples_RNO[2]_net_1\); parity_err_xhdl2_RNI59R11 : NOR3A port map(A => m6_0, B => N_78, C => N_3_0, Y => N_84_mux); \rx_shift[5]\ : DFN1E0C0 port map(D => \rx_shift_12[5]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_92_mux, Q => \rx_shift[5]_net_1\); \rx_state_RNI4LSL[1]\ : NOR3B port map(A => \rx_state[0]_net_1\, B => baud_clock, C => \rx_state[1]_net_1\, Y => N_7_0); \rx_bit_cnt[0]\ : DFN1E0C0 port map(D => N_21, CLK => HCLK_c, CLR => HRESETn_c, E => N_92_mux, Q => \rx_bit_cnt[0]_net_1\); \samples_RNO[1]\ : MX2 port map(A => \samples[1]_net_1\, B => \samples[2]_net_1\, S => baud_clock, Y => \samples_RNO[1]_net_1\); overflow_int_RNO : NOR2A port map(A => m63_0, B => un47_baud_clock_i, Y => overflow_int_3); \rx_byte_xhdl5[1]\ : DFN1E1C0 port map(D => \rx_shift[1]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, E => rx_byte_xhdl5_1_sqmuxa, Q => data_out(1)); \rx_bit_cnt_RNO_0[3]\ : NOR2B port map(A => N_337, B => \rx_bit_cnt[2]_net_1\, Y => N_14_0); \receive_count_RNINPCM[1]\ : NOR3B port map(A => \receive_count[2]_net_1\, B => \receive_count[1]_net_1\, C => \receive_count[0]_net_1\, Y => N_86); \rx_bit_cnt_RNIQDT41[3]\ : NOR3B port map(A => \rx_bit_cnt[3]_net_1\, B => m65_e_1, C => \rx_bit_cnt[2]_net_1\, Y => m65_e_2); \last_bit[0]\ : DFN1E1P0 port map(D => N_41_mux, CLK => HCLK_c, PRE => HRESETn_c, E => N_341, Q => \last_bit[0]_net_1\); \rx_bit_cnt_RNO[3]\ : XA1B port map(A => \rx_bit_cnt[3]_net_1\, B => N_14_0, C => N_82, Y => rx_bit_cnt_n3); \rx_byte_xhdl5[5]\ : DFN1E1C0 port map(D => \rx_shift[5]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, E => rx_byte_xhdl5_1_sqmuxa, Q => data_out(5)); \rx_bit_cnt[3]\ : DFN1E0C0 port map(D => rx_bit_cnt_n3, CLK => HCLK_c, CLR => HRESETn_c, E => N_92_mux, Q => \rx_bit_cnt[3]_net_1\); \rx_state_RNO_0[0]\ : MX2C port map(A => N_38_mux, B => un47_baud_clock_i, S => \rx_state[0]_net_1\, Y => N_9_0); \rx_bit_cnt_RNO[1]\ : XA1 port map(A => \rx_bit_cnt[0]_net_1\, B => \rx_bit_cnt[1]_net_1\, C => N_92, Y => rx_bit_cnt_n1); overflow_xhdl1 : DFN1E0C0 port map(D => un1_temp_xhdl10_i, CLK => HCLK_c, CLR => HRESETn_c, E => overflow_xhdl1_1_sqmuxa, Q => OVERFLOW); \last_bit_RNI0BVH[0]\ : XNOR2 port map(A => \rx_bit_cnt[0]_net_1\, B => \last_bit[0]_net_1\, Y => N_12_0); end DEF_ARCH; library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity top_CoreUARTapb_0_COREUART is port( data_out : out std_logic_vector(7 downto 0); CoreAPB_0_APBmslave0_PWDATA : in std_logic_vector(7 downto 0); CoreAPB_0_APBmslave0_PADDR_0 : in std_logic; N_84_mux : out std_logic; N_3_0 : in std_logic; CoreAPB_0_APBmslave0_PENABLE : in std_logic; PARITY_ERR : out std_logic; FRAMING_ERR : out std_logic; OVERFLOW : out std_logic; TXRDY : out std_logic; TX_c : out std_logic; HRESETn_c : in std_logic; HCLK_c : in std_logic; RXRDY : out std_logic; N_15_0 : in std_logic; m6_0 : in std_logic; CoreAPB_0_APBmslave0_PWRITE : in std_logic; CoreAPB_0_APBmslave0_PSELx : in std_logic ); end top_CoreUARTapb_0_COREUART; architecture DEF_ARCH of top_CoreUARTapb_0_COREUART is component INV port( A : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1E1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; E : in std_logic := 'U'; Q : out std_logic ); end component; component top_CoreUARTapb_0_Tx_async port( tx_hold_reg : in std_logic_vector(7 downto 0) := (others => 'U'); HRESETn_c : in std_logic := 'U'; HCLK_c : in std_logic := 'U'; TX_c : out std_logic; TXRDY : out std_logic; xmit_pulse : in std_logic := 'U'; un1_csn : in std_logic := 'U' ); end component; component NOR2B port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component OR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; component top_CoreUARTapb_0_Clock_gen port( HRESETn_c : in std_logic := 'U'; HCLK_c : in std_logic := 'U'; baud_clock : out std_logic; xmit_pulse : out std_logic ); end component; component NOR3B port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component top_CoreUARTapb_0_Rx_async port( data_out : out std_logic_vector(7 downto 0); OVERFLOW : out std_logic; FRAMING_ERR : out std_logic; stop_strobe : out std_logic; un1_temp_xhdl10_i : in std_logic := 'U'; HRESETn_c : in std_logic := 'U'; HCLK_c : in std_logic := 'U'; PARITY_ERR : out std_logic; CoreAPB_0_APBmslave0_PENABLE : in std_logic := 'U'; un1_temp_xhdl10 : in std_logic := 'U'; N_3_0 : in std_logic := 'U'; m6_0 : in std_logic := 'U'; N_84_mux : out std_logic; baud_clock : in std_logic := 'U'; receive_full : out std_logic ); end component; signal \un1_temp_xhdl10_i\, \un1_temp_xhdl10\, un1_csn_1, \un1_temp_xhdl10_1\, un1_csn, un1_rx_fifo, receive_full, stop_strobe, \tx_hold_reg[0]_net_1\, \tx_hold_reg[1]_net_1\, \tx_hold_reg[2]_net_1\, \tx_hold_reg[3]_net_1\, \tx_hold_reg[4]_net_1\, \tx_hold_reg[5]_net_1\, \tx_hold_reg[6]_net_1\, \tx_hold_reg[7]_net_1\, baud_clock, xmit_pulse, \GND\, \VCC\ : std_logic; for all : top_CoreUARTapb_0_Tx_async Use entity work.top_CoreUARTapb_0_Tx_async(DEF_ARCH); for all : top_CoreUARTapb_0_Clock_gen Use entity work.top_CoreUARTapb_0_Clock_gen(DEF_ARCH); for all : top_CoreUARTapb_0_Rx_async Use entity work.top_CoreUARTapb_0_Rx_async(DEF_ARCH); begin un1_temp_xhdl10_i : INV port map(A => \un1_temp_xhdl10\, Y => \un1_temp_xhdl10_i\); \tx_hold_reg[7]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(7), CLK => HCLK_c, CLR => HRESETn_c, E => un1_csn, Q => \tx_hold_reg[7]_net_1\); make_TX : top_CoreUARTapb_0_Tx_async port map(tx_hold_reg(7) => \tx_hold_reg[7]_net_1\, tx_hold_reg(6) => \tx_hold_reg[6]_net_1\, tx_hold_reg(5) => \tx_hold_reg[5]_net_1\, tx_hold_reg(4) => \tx_hold_reg[4]_net_1\, tx_hold_reg(3) => \tx_hold_reg[3]_net_1\, tx_hold_reg(2) => \tx_hold_reg[2]_net_1\, tx_hold_reg(1) => \tx_hold_reg[1]_net_1\, tx_hold_reg(0) => \tx_hold_reg[0]_net_1\, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, TX_c => TX_c, TXRDY => TXRDY, xmit_pulse => xmit_pulse, un1_csn => un1_csn); \tx_hold_reg[5]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(5), CLK => HCLK_c, CLR => HRESETn_c, E => un1_csn, Q => \tx_hold_reg[5]_net_1\); \tx_hold_reg[0]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(0), CLK => HCLK_c, CLR => HRESETn_c, E => un1_csn, Q => \tx_hold_reg[0]_net_1\); \reg_write.un1_csn\ : NOR2B port map(A => un1_csn_1, B => N_15_0, Y => un1_csn); VCC_i : VCC port map(Y => \VCC\); \tx_hold_reg[3]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(3), CLK => HCLK_c, CLR => HRESETn_c, E => un1_csn, Q => \tx_hold_reg[3]_net_1\); rxrdy_xhdl4_RNO : OR2A port map(A => receive_full, B => stop_strobe, Y => un1_rx_fifo); un1_temp_xhdl10 : NOR2B port map(A => \un1_temp_xhdl10_1\, B => N_15_0, Y => \un1_temp_xhdl10\); \tx_hold_reg[2]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(2), CLK => HCLK_c, CLR => HRESETn_c, E => un1_csn, Q => \tx_hold_reg[2]_net_1\); GND_i : GND port map(Y => \GND\); \tx_hold_reg[1]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(1), CLK => HCLK_c, CLR => HRESETn_c, E => un1_csn, Q => \tx_hold_reg[1]_net_1\); \tx_hold_reg[6]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(6), CLK => HCLK_c, CLR => HRESETn_c, E => un1_csn, Q => \tx_hold_reg[6]_net_1\); un1_temp_xhdl10_1 : NOR2B port map(A => CoreAPB_0_APBmslave0_PADDR_0, B => m6_0, Y => \un1_temp_xhdl10_1\); \tx_hold_reg[4]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(4), CLK => HCLK_c, CLR => HRESETn_c, E => un1_csn, Q => \tx_hold_reg[4]_net_1\); make_top_CoreUARTapb_0_Clock_gen : top_CoreUARTapb_0_Clock_gen port map(HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, baud_clock => baud_clock, xmit_pulse => xmit_pulse); \reg_write.un1_csn_1\ : NOR3B port map(A => CoreAPB_0_APBmslave0_PSELx, B => CoreAPB_0_APBmslave0_PWRITE, C => CoreAPB_0_APBmslave0_PADDR_0, Y => un1_csn_1); make_RX : top_CoreUARTapb_0_Rx_async port map(data_out(7) => data_out(7), data_out(6) => data_out(6), data_out(5) => data_out(5), data_out(4) => data_out(4), data_out(3) => data_out(3), data_out(2) => data_out(2), data_out(1) => data_out(1), data_out(0) => data_out(0), OVERFLOW => OVERFLOW, FRAMING_ERR => FRAMING_ERR, stop_strobe => stop_strobe, un1_temp_xhdl10_i => \un1_temp_xhdl10_i\, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, PARITY_ERR => PARITY_ERR, CoreAPB_0_APBmslave0_PENABLE => CoreAPB_0_APBmslave0_PENABLE, un1_temp_xhdl10 => \un1_temp_xhdl10\, N_3_0 => N_3_0, m6_0 => m6_0, N_84_mux => N_84_mux, baud_clock => baud_clock, receive_full => receive_full); rxrdy_xhdl4 : DFN1E1C0 port map(D => receive_full, CLK => HCLK_c, CLR => HRESETn_c, E => un1_rx_fifo, Q => RXRDY); end DEF_ARCH; library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity top_CoreUARTapb_0_CoreUARTapb is port( CoreAPB_0_APBmslave0_PRDATA : out std_logic_vector(7 downto 0); CoreAPB_0_APBmslave0_PWDATA : in std_logic_vector(7 downto 0); CoreAPB_0_APBmslave0_PADDR : in std_logic_vector(4 downto 2); TX_c : out std_logic; HRESETn_c : in std_logic; HCLK_c : in std_logic; CoreAPB_0_APBmslave0_PENABLE : in std_logic; CoreAPB_0_APBmslave0_PWRITE : in std_logic; CoreAPB_0_APBmslave0_PSELx : in std_logic ); end top_CoreUARTapb_0_CoreUARTapb; architecture DEF_ARCH of top_CoreUARTapb_0_CoreUARTapb is component NOR2B port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1E1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; E : in std_logic := 'U'; Q : out std_logic ); end component; component AOI1 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component MX2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; S : in std_logic := 'U'; Y : out std_logic ); end component; component MX2C port( A : in std_logic := 'U'; B : in std_logic := 'U'; S : in std_logic := 'U'; Y : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component MX2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; S : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3C port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; component top_CoreUARTapb_0_COREUART port( data_out : out std_logic_vector(7 downto 0); CoreAPB_0_APBmslave0_PWDATA : in std_logic_vector(7 downto 0) := (others => 'U'); CoreAPB_0_APBmslave0_PADDR_0 : in std_logic := 'U'; N_84_mux : out std_logic; N_3_0 : in std_logic := 'U'; CoreAPB_0_APBmslave0_PENABLE : in std_logic := 'U'; PARITY_ERR : out std_logic; FRAMING_ERR : out std_logic; OVERFLOW : out std_logic; TXRDY : out std_logic; TX_c : out std_logic; HRESETn_c : in std_logic := 'U'; HCLK_c : in std_logic := 'U'; RXRDY : out std_logic; N_15_0 : in std_logic := 'U'; m6_0 : in std_logic := 'U'; CoreAPB_0_APBmslave0_PWRITE : in std_logic := 'U'; CoreAPB_0_APBmslave0_PSELx : in std_logic := 'U' ); end component; component NOR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3B port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; signal \m6_0\, \m10_1\, N_34_0, N_8_0, \controlReg1[3]_net_1\, N_35_0, N_36_0, OVERFLOW, N_37_0, N_68, \nxtprdata_xhdl7_1[3]\, \data_out[3]\, \controlReg2[3]_net_1\, N_26_0, \controlReg1[7]_net_1\, N_27_0, N_56_0, \nxtprdata_xhdl7_1[7]\, \data_out[7]\, \controlReg2[7]_net_1\, N_3_0, N_15_0, N_20_0, \controlReg1[5]_net_1\, N_21_0, N_62, \nxtprdata_xhdl7_1[5]\, \data_out[5]\, \controlReg2[5]_net_1\, N_74, \data_out[1]\, \controlReg2[1]_net_1\, N_71, \data_out[2]\, \controlReg2[2]_net_1\, N_65, \data_out[4]\, \controlReg2[4]_net_1\, \nxtprdata_xhdl7_1[1]\, N_46_0, N_47_0, N_44_0, N_45_0, RXRDY, \controlReg1[1]_net_1\, \nxtprdata_xhdl7_1[2]\, N_41_0, N_42_0, N_39_0, N_40_0, \controlReg1[2]_net_1\, PARITY_ERR, \nxtprdata_xhdl7_1[4]\, N_31_0, N_32_0, N_29_0, N_30_0, FRAMING_ERR, \controlReg1[4]_net_1\, N_77, \data_out[0]\, \controlReg2[0]_net_1\, N_59_0, \data_out[6]\, \controlReg2[6]_net_1\, \nxtprdata_xhdl7_1[0]\, N_51_0, N_52_0, N_49_0, N_50_0, TXRDY, \controlReg1[0]_net_1\, \nxtprdata_xhdl7_1[6]\, N_23_0, N_24_0, \controlReg1[6]_net_1\, un5_psel, un13_psel, N_84_mux, \GND\, \VCC\ : std_logic; for all : top_CoreUARTapb_0_COREUART Use entity work.top_CoreUARTapb_0_COREUART(DEF_ARCH); begin \iPRDATA_RNO_0[6]\ : NOR2B port map(A => \controlReg1[6]_net_1\, B => N_8_0, Y => N_23_0); \iPRDATA_RNO_1[7]\ : NOR2 port map(A => CoreAPB_0_APBmslave0_PADDR(4), B => N_56_0, Y => N_27_0); \controlReg1[5]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(5), CLK => HCLK_c, CLR => HRESETn_c, E => un5_psel, Q => \controlReg1[5]_net_1\); \iPRDATA_RNO_1[0]\ : NOR2 port map(A => N_77, B => CoreAPB_0_APBmslave0_PADDR(4), Y => N_52_0); \iPRDATA_RNO_2[2]\ : NOR2B port map(A => PARITY_ERR, B => CoreAPB_0_APBmslave0_PADDR(4), Y => N_39_0); \iPRDATA_RNO_2[1]\ : NOR2B port map(A => \controlReg1[1]_net_1\, B => CoreAPB_0_APBmslave0_PADDR(3), Y => N_44_0); \iPRDATA_RNO_3[4]\ : AOI1 port map(A => \controlReg1[4]_net_1\, B => CoreAPB_0_APBmslave0_PADDR(3), C => CoreAPB_0_APBmslave0_PADDR(4), Y => N_30_0); \iPRDATA_RNO_3[3]\ : AOI1 port map(A => \controlReg1[3]_net_1\, B => CoreAPB_0_APBmslave0_PADDR(3), C => CoreAPB_0_APBmslave0_PADDR(4), Y => N_35_0); \controlReg1[7]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(7), CLK => HCLK_c, CLR => HRESETn_c, E => un5_psel, Q => \controlReg1[7]_net_1\); \iPRDATA[1]\ : DFN1E1C0 port map(D => \nxtprdata_xhdl7_1[1]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_84_mux, Q => CoreAPB_0_APBmslave0_PRDATA(1)); \iPRDATA_RNO[5]\ : MX2 port map(A => N_20_0, B => N_21_0, S => CoreAPB_0_APBmslave0_PADDR(2), Y => \nxtprdata_xhdl7_1[5]\); \controlReg2[4]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(4), CLK => HCLK_c, CLR => HRESETn_c, E => un13_psel, Q => \controlReg2[4]_net_1\); \iPRDATA_RNO_2[7]\ : MX2C port map(A => \data_out[7]\, B => \controlReg2[7]_net_1\, S => CoreAPB_0_APBmslave0_PADDR(3), Y => N_56_0); \iPRDATA_RNO_2[5]\ : MX2C port map(A => \data_out[5]\, B => \controlReg2[5]_net_1\, S => CoreAPB_0_APBmslave0_PADDR(3), Y => N_62); VCC_i : VCC port map(Y => \VCC\); \iPRDATA[4]\ : DFN1E1C0 port map(D => \nxtprdata_xhdl7_1[4]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_84_mux, Q => CoreAPB_0_APBmslave0_PRDATA(4)); \iPRDATA_RNO_3[0]\ : AOI1 port map(A => \controlReg1[0]_net_1\, B => CoreAPB_0_APBmslave0_PADDR(3), C => CoreAPB_0_APBmslave0_PADDR(4), Y => N_50_0); \iPRDATA_RNO[1]\ : MX2A port map(A => N_46_0, B => N_47_0, S => CoreAPB_0_APBmslave0_PADDR(2), Y => \nxtprdata_xhdl7_1[1]\); \iPRDATA_RNO[4]\ : MX2A port map(A => N_31_0, B => N_32_0, S => CoreAPB_0_APBmslave0_PADDR(2), Y => \nxtprdata_xhdl7_1[4]\); \iPRDATA[3]\ : DFN1E1C0 port map(D => \nxtprdata_xhdl7_1[3]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_84_mux, Q => CoreAPB_0_APBmslave0_PRDATA(3)); \controlReg2[6]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(6), CLK => HCLK_c, CLR => HRESETn_c, E => un13_psel, Q => \controlReg2[6]_net_1\); \controlReg1[3]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(3), CLK => HCLK_c, CLR => HRESETn_c, E => un5_psel, Q => \controlReg1[3]_net_1\); \iPRDATA_RNO_4[0]\ : MX2C port map(A => \data_out[0]\, B => \controlReg2[0]_net_1\, S => CoreAPB_0_APBmslave0_PADDR(3), Y => N_77); \iPRDATA_RNO_1[2]\ : NOR2 port map(A => N_71, B => CoreAPB_0_APBmslave0_PADDR(4), Y => N_42_0); \controlReg1[6]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(6), CLK => HCLK_c, CLR => HRESETn_c, E => un5_psel, Q => \controlReg1[6]_net_1\); \controlReg2[3]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(3), CLK => HCLK_c, CLR => HRESETn_c, E => un13_psel, Q => \controlReg2[3]_net_1\); \controlReg1[2]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(2), CLK => HCLK_c, CLR => HRESETn_c, E => un5_psel, Q => \controlReg1[2]_net_1\); \iPRDATA_RNO_3[2]\ : AOI1 port map(A => PARITY_ERR, B => CoreAPB_0_APBmslave0_PADDR(4), C => CoreAPB_0_APBmslave0_PADDR(3), Y => N_40_0); \iPRDATA_RNO_0[4]\ : MX2A port map(A => N_29_0, B => N_30_0, S => FRAMING_ERR, Y => N_31_0); \controlReg1[4]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(4), CLK => HCLK_c, CLR => HRESETn_c, E => un5_psel, Q => \controlReg1[4]_net_1\); \iPRDATA[5]\ : DFN1E1C0 port map(D => \nxtprdata_xhdl7_1[5]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_84_mux, Q => CoreAPB_0_APBmslave0_PRDATA(5)); \iPRDATA[7]\ : DFN1E1C0 port map(D => \nxtprdata_xhdl7_1[7]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_84_mux, Q => CoreAPB_0_APBmslave0_PRDATA(7)); m2 : NOR2B port map(A => CoreAPB_0_APBmslave0_PADDR(3), B => CoreAPB_0_APBmslave0_PADDR(4), Y => N_3_0); \controlReg2[1]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(1), CLK => HCLK_c, CLR => HRESETn_c, E => un13_psel, Q => \controlReg2[1]_net_1\); \iPRDATA_RNO[2]\ : MX2A port map(A => N_41_0, B => N_42_0, S => CoreAPB_0_APBmslave0_PADDR(2), Y => \nxtprdata_xhdl7_1[2]\); \iPRDATA_RNO[0]\ : MX2A port map(A => N_51_0, B => N_52_0, S => CoreAPB_0_APBmslave0_PADDR(2), Y => \nxtprdata_xhdl7_1[0]\); m10_1 : NOR3C port map(A => CoreAPB_0_APBmslave0_PWRITE, B => CoreAPB_0_APBmslave0_PENABLE, C => CoreAPB_0_APBmslave0_PSELx, Y => \m10_1\); \iPRDATA_RNO_0[3]\ : MX2A port map(A => N_34_0, B => N_35_0, S => OVERFLOW, Y => N_36_0); \iPRDATA_RNO_3[1]\ : AOI1 port map(A => \controlReg1[1]_net_1\, B => CoreAPB_0_APBmslave0_PADDR(3), C => CoreAPB_0_APBmslave0_PADDR(4), Y => N_45_0); \controlReg2[7]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(7), CLK => HCLK_c, CLR => HRESETn_c, E => un13_psel, Q => \controlReg2[7]_net_1\); \iPRDATA_RNO_0[1]\ : MX2A port map(A => N_44_0, B => N_45_0, S => RXRDY, Y => N_46_0); \iPRDATA[2]\ : DFN1E1C0 port map(D => \nxtprdata_xhdl7_1[2]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_84_mux, Q => CoreAPB_0_APBmslave0_PRDATA(2)); GND_i : GND port map(Y => \GND\); \iPRDATA_RNO_4[1]\ : MX2C port map(A => \data_out[1]\, B => \controlReg2[1]_net_1\, S => CoreAPB_0_APBmslave0_PADDR(3), Y => N_74); \iPRDATA_RNO_4[4]\ : MX2C port map(A => \data_out[4]\, B => \controlReg2[4]_net_1\, S => CoreAPB_0_APBmslave0_PADDR(3), Y => N_65); \controlReg2[5]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(5), CLK => HCLK_c, CLR => HRESETn_c, E => un13_psel, Q => \controlReg2[5]_net_1\); \controlReg2[2]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(2), CLK => HCLK_c, CLR => HRESETn_c, E => un13_psel, Q => \controlReg2[2]_net_1\); \iPRDATA_RNO_1[5]\ : NOR2 port map(A => N_62, B => CoreAPB_0_APBmslave0_PADDR(4), Y => N_21_0); \iPRDATA_RNO_4[3]\ : MX2C port map(A => \data_out[3]\, B => \controlReg2[3]_net_1\, S => CoreAPB_0_APBmslave0_PADDR(3), Y => N_68); \iPRDATA_RNO_0[7]\ : NOR2B port map(A => N_8_0, B => \controlReg1[7]_net_1\, Y => N_26_0); \iPRDATA[6]\ : DFN1E1C0 port map(D => \nxtprdata_xhdl7_1[6]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_84_mux, Q => CoreAPB_0_APBmslave0_PRDATA(6)); \iPRDATA_RNO_1[3]\ : NOR2 port map(A => N_68, B => CoreAPB_0_APBmslave0_PADDR(4), Y => N_37_0); \iPRDATA[0]\ : DFN1E1C0 port map(D => \nxtprdata_xhdl7_1[0]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_84_mux, Q => CoreAPB_0_APBmslave0_PRDATA(0)); uUART : top_CoreUARTapb_0_COREUART port map(data_out(7) => \data_out[7]\, data_out(6) => \data_out[6]\, data_out(5) => \data_out[5]\, data_out(4) => \data_out[4]\, data_out(3) => \data_out[3]\, data_out(2) => \data_out[2]\, data_out(1) => \data_out[1]\, data_out(0) => \data_out[0]\, CoreAPB_0_APBmslave0_PWDATA(7) => CoreAPB_0_APBmslave0_PWDATA(7), CoreAPB_0_APBmslave0_PWDATA(6) => CoreAPB_0_APBmslave0_PWDATA(6), CoreAPB_0_APBmslave0_PWDATA(5) => CoreAPB_0_APBmslave0_PWDATA(5), CoreAPB_0_APBmslave0_PWDATA(4) => CoreAPB_0_APBmslave0_PWDATA(4), CoreAPB_0_APBmslave0_PWDATA(3) => CoreAPB_0_APBmslave0_PWDATA(3), CoreAPB_0_APBmslave0_PWDATA(2) => CoreAPB_0_APBmslave0_PWDATA(2), CoreAPB_0_APBmslave0_PWDATA(1) => CoreAPB_0_APBmslave0_PWDATA(1), CoreAPB_0_APBmslave0_PWDATA(0) => CoreAPB_0_APBmslave0_PWDATA(0), CoreAPB_0_APBmslave0_PADDR_0 => CoreAPB_0_APBmslave0_PADDR(2), N_84_mux => N_84_mux, N_3_0 => N_3_0, CoreAPB_0_APBmslave0_PENABLE => CoreAPB_0_APBmslave0_PENABLE, PARITY_ERR => PARITY_ERR, FRAMING_ERR => FRAMING_ERR, OVERFLOW => OVERFLOW, TXRDY => TXRDY, TX_c => TX_c, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, RXRDY => RXRDY, N_15_0 => N_15_0, m6_0 => \m6_0\, CoreAPB_0_APBmslave0_PWRITE => CoreAPB_0_APBmslave0_PWRITE, CoreAPB_0_APBmslave0_PSELx => CoreAPB_0_APBmslave0_PSELx); \iPRDATA_RNO_2[3]\ : NOR2B port map(A => N_8_0, B => \controlReg1[3]_net_1\, Y => N_34_0); \iPRDATA_RNO_0[2]\ : MX2A port map(A => N_39_0, B => N_40_0, S => \controlReg1[2]_net_1\, Y => N_41_0); \iPRDATA_RNO_0[5]\ : NOR2B port map(A => \controlReg1[5]_net_1\, B => CoreAPB_0_APBmslave0_PADDR(3), Y => N_20_0); m7 : NOR2A port map(A => CoreAPB_0_APBmslave0_PADDR(3), B => CoreAPB_0_APBmslave0_PADDR(4), Y => N_8_0); \iPRDATA_RNO_1[6]\ : NOR2 port map(A => N_59_0, B => CoreAPB_0_APBmslave0_PADDR(4), Y => N_24_0); \iPRDATA_RNO_2[6]\ : MX2C port map(A => \data_out[6]\, B => \controlReg2[6]_net_1\, S => CoreAPB_0_APBmslave0_PADDR(3), Y => N_59_0); \iPRDATA_RNO_1[1]\ : NOR2 port map(A => N_74, B => CoreAPB_0_APBmslave0_PADDR(4), Y => N_47_0); \iPRDATA_RNO_2[0]\ : NOR2B port map(A => \controlReg1[0]_net_1\, B => N_8_0, Y => N_49_0); m6_0 : NOR2A port map(A => CoreAPB_0_APBmslave0_PSELx, B => CoreAPB_0_APBmslave0_PWRITE, Y => \m6_0\); \iPRDATA_RNO_4[2]\ : MX2C port map(A => \data_out[2]\, B => \controlReg2[2]_net_1\, S => CoreAPB_0_APBmslave0_PADDR(3), Y => N_71); \controlReg2[0]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(0), CLK => HCLK_c, CLR => HRESETn_c, E => un13_psel, Q => \controlReg2[0]_net_1\); \iPRDATA_RNO[7]\ : MX2 port map(A => N_26_0, B => N_27_0, S => CoreAPB_0_APBmslave0_PADDR(2), Y => \nxtprdata_xhdl7_1[7]\); \iPRDATA_RNO_2[4]\ : NOR2B port map(A => \controlReg1[4]_net_1\, B => CoreAPB_0_APBmslave0_PADDR(3), Y => N_29_0); m11 : NOR3C port map(A => N_8_0, B => \m10_1\, C => CoreAPB_0_APBmslave0_PADDR(2), Y => un13_psel); \controlReg1[1]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(1), CLK => HCLK_c, CLR => HRESETn_c, E => un5_psel, Q => \controlReg1[1]_net_1\); \iPRDATA_RNO_0[0]\ : MX2A port map(A => N_49_0, B => N_50_0, S => TXRDY, Y => N_51_0); m12 : NOR3B port map(A => N_8_0, B => \m10_1\, C => CoreAPB_0_APBmslave0_PADDR(2), Y => un5_psel); \iPRDATA_RNO_1[4]\ : NOR2 port map(A => N_65, B => CoreAPB_0_APBmslave0_PADDR(4), Y => N_32_0); \iPRDATA_RNO[3]\ : MX2A port map(A => N_36_0, B => N_37_0, S => CoreAPB_0_APBmslave0_PADDR(2), Y => \nxtprdata_xhdl7_1[3]\); m14 : NOR3A port map(A => CoreAPB_0_APBmslave0_PENABLE, B => CoreAPB_0_APBmslave0_PADDR(4), C => CoreAPB_0_APBmslave0_PADDR(3), Y => N_15_0); \controlReg1[0]\ : DFN1E1C0 port map(D => CoreAPB_0_APBmslave0_PWDATA(0), CLK => HCLK_c, CLR => HRESETn_c, E => un5_psel, Q => \controlReg1[0]_net_1\); \iPRDATA_RNO[6]\ : MX2 port map(A => N_23_0, B => N_24_0, S => CoreAPB_0_APBmslave0_PADDR(2), Y => \nxtprdata_xhdl7_1[6]\); end DEF_ARCH; library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity CoreAHB2APB is port( CoreAHBLite_0_AHBmslave0_HWDATA : in std_logic_vector(7 downto 0); CoreAPB_0_APBmslave0_PWDATA : out std_logic_vector(7 downto 0); CoreAPB_0_APBmslave0_PADDR : out std_logic_vector(4 downto 2); CoreAHB2APB_0_APBmaster_PSELx : out std_logic_vector(15 downto 1); arbRegSMCurrentState_i_0_0 : in std_logic; arbRegSMCurrentState_i_0_3 : in std_logic; xhdl1222_0 : in std_logic; masterAddrInProg_i_1_0 : in std_logic; arbRegSMCurrentState_RNICAHF7_0 : in std_logic; CoreAPB_0_APBmslave0_PWRITE : out std_logic; CoreAPB_0_APBmslave0_PSELx : out std_logic; HRESETn_c : in std_logic; HCLK_c : in std_logic; CoreAPB_0_APBmslave0_PENABLE : out std_logic; N_124_0 : in std_logic; N_128_0 : in std_logic; N_22 : in std_logic; N_20 : in std_logic; N_18 : in std_logic; N_395 : in std_logic; N_363 : in std_logic; N_364 : in std_logic; HTRANS_0_a3_i_a2_3_0 : in std_logic; N_265 : in std_logic; N_392 : in std_logic; N_135 : in std_logic; N_367 : in std_logic; defSlaveSMCurrentState : in std_logic; N_391 : in std_logic; HTRANS_0_a3_i_a2_4_0 : in std_logic; N_398 : out std_logic; un1_N_11_mux_i_5_a1_1 : out std_logic; N_327 : in std_logic; un4_m5_0_a3_1 : out std_logic; un4_m5_0_a3_2 : out std_logic; N_171 : in std_logic; N_330 : in std_logic; N_397 : in std_logic; N_326 : in std_logic; un1_m1_e_0_0 : out std_logic; CoreAHBLite_0_AHBmslave0_HREADY : out std_logic; CoreAHBLite_0_AHBmslave0_HSELx : in std_logic; HADDR_24_0_a3_i_out : in std_logic; N_263 : in std_logic; N_323 : in std_logic; N_365 : in std_logic; N_254 : in std_logic; N_120 : in std_logic ); end CoreAHB2APB; architecture DEF_ARCH of CoreAHB2APB is component NOR3B port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3C port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component AO1 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1E0C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; E : in std_logic := 'U'; Q : out std_logic ); end component; component NOR3A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component OAI1 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component NOR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1E1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; E : in std_logic := 'U'; Q : out std_logic ); end component; component NOR2B port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component MX2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; S : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1P0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; PRE : in std_logic := 'U'; Q : out std_logic ); end component; component AO1D port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component AO1B port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component OR2A port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component OR3A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component GND port( Y : out std_logic ); end component; component AOI1B port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component OR3 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component NOR3 port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component OR2 port( A : in std_logic := 'U'; B : in std_logic := 'U'; Y : out std_logic ); end component; component DFN1C0 port( D : in std_logic := 'U'; CLK : in std_logic := 'U'; CLR : in std_logic := 'U'; Q : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component AO1A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component OA1C port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component OA1A port( A : in std_logic := 'U'; B : in std_logic := 'U'; C : in std_logic := 'U'; Y : out std_logic ); end component; component INV port( A : in std_logic := 'U'; Y : out std_logic ); end component; signal \CurrentState_i[6]\, \CurrentState[6]_net_1\, \CurrentState_ns_i_0_0[1]\, N_55, \NextState[2]\, HreadyNext_0_0_0, HreadyNext_m4_0_0, HreadyNext_N_4, Psel1Mux_0_a2_0_1, Psel12Mux_0_a2_6_0, N_117, Psel5Mux_m1_e_2, N_37, Psel0Mux_0_a2_0_1, Psel5Mux_m1_e_1, N_118, Psel8Mux_0_a2_0_1, N_119, Psel9Mux_0_a2_0_1, Psel4Mux_m2_e_0_1, Psel2Mux_0_a2_0_2, Psel14Mux_0_a2_0_1, N_116, Psel13Mux_0_a2_0_1, HreadyNext_0_0_a2_0, N_54, N_34, \un1_N_11_mux_i_0_4\, \un4_valid_4_2\, \un1_N_11_mux_i_0_2\, \un1_N_11_mux_i_0_1\, \un1_N_11_mux_i_5_a0\, \un1_N_11_mux_i_5_a1\, N_366, Psel15Mux_0_a2_0_4, \un4_valid_4\, Psel15Mux_0_a2_0_2, Psel15Mux_0_a2_0_0, un1_m5_0_a2_1_0, un4_valid_2, un4_N_13_mux, un4_valid_0, \CoreAHBLite_0_AHBmslave0_HREADY\, \CurrentState[0]_net_1\, \CurrentState[2]_net_1\, \un4_valid_4_1\, un1_m5_0_a2_5_2, un1_m1_e_0_0_net_1, un1_m5_0_a2_5_1, HreadyNext_m2_e_0, un4_m5_0_a3_2_net_1, un4_m5_0_a3_1_net_1, un1_N_11_mux_i_5_a1_1_net_1, \N_398\, \un1_N_11_mux_i_5_a0_1\, HreadyNext_N_7_mux, \iHREADYOUT_RNIAOEJP1\, HreadyNext, N_98, N_97, \CurrentState_RNO[6]_net_1\, N_520, \CurrentState_i_0[5]\, \CurrentState_i_0[1]\, \CurrentState[7]_net_1\, N_102, un1_N_5_mux, \un1_m5_0_a2_a1\, Psel12Mux, N_71, Psel11Mux, N_73, Psel4Mux_N_7_mux, N_87, Psel6Mux_N_7_mux, N_83, Psel5Mux_N_5_mux_0, N_85, \HaddrReg[26]_net_1\, N_124, \HaddrReg[27]_net_1\, N_91, N_127, N_93, N_128, N_95, N_104, \CurrentState_ns[4]\, N_123, \HaddrReg[24]_net_1\, \HaddrReg[25]_net_1\, N_339, Psel2Mux, Psel1Mux, Psel0Mux, \HwriteReg\, \CurrentState[4]_net_1\, \CurrentState[3]_net_1\, \CurrentState_RNO[2]_net_1\, \CurrentState_ns[7]\, N_326_0, \CurrentState_ns[6]\, Psel3Mux, N_89, Psel7Mux, N_81, Psel8Mux, N_79, Psel9Mux, N_77, Psel10Mux, N_75, Psel13Mux, N_69, Psel14Mux, N_67, Psel15Mux, N_65, \iHREADYOUT_RNI2L8VN\, \HaddrMux[2]\, \HaddrReg[2]_net_1\, \HaddrMux[3]\, \HaddrReg[3]_net_1\, \HaddrMux[4]\, \HaddrReg[4]_net_1\, \GND\, \VCC\ : std_logic; begin N_398 <= \N_398\; un1_N_11_mux_i_5_a1_1 <= un1_N_11_mux_i_5_a1_1_net_1; un4_m5_0_a3_1 <= un4_m5_0_a3_1_net_1; un4_m5_0_a3_2 <= un4_m5_0_a3_2_net_1; un1_m1_e_0_0 <= un1_m1_e_0_0_net_1; CoreAHBLite_0_AHBmslave0_HREADY <= \CoreAHBLite_0_AHBmslave0_HREADY\; \HaddrReg_RNINSQI[24]\ : NOR3B port map(A => \HaddrReg[24]_net_1\, B => \HaddrReg[25]_net_1\, C => N_339, Y => N_123); iPSEL13_RNO_0 : NOR3C port map(A => arbRegSMCurrentState_RNICAHF7_0, B => Psel12Mux_0_a2_6_0, C => N_116, Y => Psel13Mux_0_a2_0_1); iPSEL15_RNO : AO1 port map(A => Psel15Mux_0_a2_0_4, B => N_116, C => N_65, Y => Psel15Mux); \PADDR[2]\ : DFN1E0C0 port map(D => \HaddrMux[2]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_326_0, Q => CoreAPB_0_APBmslave0_PADDR(2)); \HaddrReg_RNINSQI_1[24]\ : NOR3A port map(A => \HaddrReg[25]_net_1\, B => N_339, C => \HaddrReg[24]_net_1\, Y => N_127); un1_m2_0 : OAI1 port map(A => N_327, B => N_171, C => un1_m1_e_0_0_net_1, Y => un1_N_5_mux); iHREADYOUT_RNIJJ351 : NOR2A port map(A => \CoreAHBLite_0_AHBmslave0_HREADY\, B => N_263, Y => un4_valid_0); iHREADYOUT_RNI3NEKC1_0 : NOR2 port map(A => N_37, B => N_120, Y => Psel5Mux_m1_e_2); \HaddrReg[27]\ : DFN1E1C0 port map(D => N_128_0, CLK => HCLK_c, CLR => HRESETn_c, E => \iHREADYOUT_RNI2L8VN\, Q => \HaddrReg[27]_net_1\); iHREADYOUT_RNO_2 : NOR2B port map(A => HreadyNext_0_0_a2_0, B => N_135, Y => N_97); \un4_m5_0_a3_1\ : NOR2A port map(A => N_397, B => N_327, Y => un4_m5_0_a3_1_net_1); un1_N_11_mux_i_5_a0 : NOR3C port map(A => \un1_N_11_mux_i_5_a0_1\, B => HTRANS_0_a3_i_a2_4_0, C => N_392, Y => \un1_N_11_mux_i_5_a0\); \PADDR_RNO[2]\ : MX2 port map(A => \HaddrReg[2]_net_1\, B => N_18, S => N_339, Y => \HaddrMux[2]\); iPSEL10 : DFN1E0C0 port map(D => Psel10Mux, CLK => HCLK_c, CLR => HRESETn_c, E => \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(10)); iHREADYOUT : DFN1P0 port map(D => HreadyNext, CLK => HCLK_c, PRE => HRESETn_c, Q => \CoreAHBLite_0_AHBmslave0_HREADY\); \HaddrReg[3]\ : DFN1E1C0 port map(D => N_20, CLK => HCLK_c, CLR => HRESETn_c, E => \iHREADYOUT_RNI2L8VN\, Q => \HaddrReg[3]_net_1\); iPSEL3_RNO : AO1 port map(A => Psel2Mux_0_a2_0_2, B => Psel1Mux_0_a2_0_1, C => N_89, Y => Psel3Mux); iPSEL1_RNO_0 : NOR3A port map(A => N_128, B => \HaddrReg[27]_net_1\, C => \HaddrReg[26]_net_1\, Y => N_93); iHREADYOUT_RNO_1 : AO1D port map(A => HreadyNext_m4_0_0, B => HreadyNext_N_4, C => \CurrentState[6]_net_1\, Y => HreadyNext_0_0_0); un1_N_11_mux_i_5_a1 : NOR2B port map(A => un1_N_11_mux_i_5_a1_1_net_1, B => N_263, Y => \un1_N_11_mux_i_5_a1\); iPSEL4 : DFN1E0C0 port map(D => Psel4Mux_N_7_mux, CLK => HCLK_c, CLR => HRESETn_c, E => \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(4)); \CurrentState_RNIJ4KGQ_0[4]\ : NOR3C port map(A => arbRegSMCurrentState_RNICAHF7_0, B => Psel12Mux_0_a2_6_0, C => N_118, Y => Psel5Mux_m1_e_1); \CurrentState_RNIJ4KGQ_5[4]\ : NOR3B port map(A => Psel12Mux_0_a2_6_0, B => N_118, C => arbRegSMCurrentState_RNICAHF7_0, Y => Psel4Mux_m2_e_0_1); \CurrentState_RNIJ4KGQ_4[4]\ : NOR3B port map(A => Psel12Mux_0_a2_6_0, B => N_119, C => arbRegSMCurrentState_RNICAHF7_0, Y => Psel8Mux_0_a2_0_1); iPSEL0_RNO_0 : NOR3A port map(A => N_124, B => \HaddrReg[27]_net_1\, C => \HaddrReg[26]_net_1\, Y => N_95); iPSEL9 : DFN1E0C0 port map(D => Psel9Mux, CLK => HCLK_c, CLR => HRESETn_c, E => \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(9)); iPSEL13_RNO : AO1 port map(A => Psel5Mux_m1_e_2, B => Psel13Mux_0_a2_0_1, C => N_69, Y => Psel13Mux); iPSEL15_RNO_1 : NOR3C port map(A => \HaddrReg[27]_net_1\, B => \HaddrReg[26]_net_1\, C => N_123, Y => N_65); un4_m5_0 : AO1B port map(A => un4_m5_0_a3_2_net_1, B => un4_m5_0_a3_1_net_1, C => un1_m1_e_0_0_net_1, Y => un4_N_13_mux); \CurrentState_RNICEQ3[2]\ : NOR2 port map(A => \CurrentState[2]_net_1\, B => N_34, Y => N_339); iHREADYOUT_RNO_7 : AO1D port map(A => \CurrentState[3]_net_1\, B => \CurrentState[2]_net_1\, C => \HwriteReg\, Y => N_54); iHREADYOUT_RNILAT451 : OR2A port map(A => un1_m5_0_a2_1_0, B => \un1_N_11_mux_i_0_4\, Y => N_37); \CurrentState[7]\ : DFN1P0 port map(D => N_104, CLK => HCLK_c, PRE => HRESETn_c, Q => \CurrentState[7]_net_1\); \CurrentState_RNO[1]\ : OR2A port map(A => \CurrentState[3]_net_1\, B => \iHREADYOUT_RNIAOEJP1\, Y => \CurrentState_ns[6]\); iPSEL12 : DFN1E0C0 port map(D => Psel12Mux, CLK => HCLK_c, CLR => HRESETn_c, E => \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(12)); iPSEL3 : DFN1E0C0 port map(D => Psel3Mux, CLK => HCLK_c, CLR => HRESETn_c, E => \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(3)); un1_N_11_mux_i_0_2 : OR3A port map(A => N_254, B => \un1_N_11_mux_i_5_a0\, C => \un1_N_11_mux_i_5_a1\, Y => \un1_N_11_mux_i_0_2\); \CurrentState_RNO[3]\ : NOR2A port map(A => N_55, B => \iHREADYOUT_RNIAOEJP1\, Y => \CurrentState_ns[4]\); \PWDATA[4]\ : DFN1E1C0 port map(D => CoreAHBLite_0_AHBmslave0_HWDATA(4), CLK => HCLK_c, CLR => HRESETn_c, E => N_55, Q => CoreAPB_0_APBmslave0_PWDATA(4)); iPSEL12_RNO : AO1 port map(A => Psel5Mux_m1_e_2, B => Psel14Mux_0_a2_0_1, C => N_71, Y => Psel12Mux); iHREADYOUT_RNI3NEKC1 : NOR2A port map(A => N_120, B => N_37, Y => Psel2Mux_0_a2_0_2); iPSEL2_RNO : AO1 port map(A => Psel2Mux_0_a2_0_2, B => Psel0Mux_0_a2_0_1, C => N_91, Y => Psel2Mux); \un4_m5_0_a3_2\ : NOR3A port map(A => N_254, B => N_330, C => N_171, Y => un4_m5_0_a3_2_net_1); iHREADYOUT_RNO_5 : NOR2A port map(A => N_54, B => N_34, Y => HreadyNext_0_0_a2_0); \PWDATA[7]\ : DFN1E1C0 port map(D => CoreAHBLite_0_AHBmslave0_HWDATA(7), CLK => HCLK_c, CLR => HRESETn_c, E => N_55, Q => CoreAPB_0_APBmslave0_PWDATA(7)); GND_i : GND port map(Y => \GND\); \PWDATA[0]\ : DFN1E1C0 port map(D => CoreAHBLite_0_AHBmslave0_HWDATA(0), CLK => HCLK_c, CLR => HRESETn_c, E => N_55, Q => CoreAPB_0_APBmslave0_PWDATA(0)); iHREADYOUT_RNO_6 : AOI1B port map(A => HreadyNext_m2_e_0, B => N_395, C => un1_m1_e_0_0_net_1, Y => HreadyNext_N_7_mux); \CurrentState_RNIJ4KGQ_2[4]\ : NOR3B port map(A => Psel12Mux_0_a2_6_0, B => N_117, C => arbRegSMCurrentState_RNICAHF7_0, Y => Psel0Mux_0_a2_0_1); un4_valid_4_2 : NOR2 port map(A => N_364, B => N_363, Y => \un4_valid_4_2\); iHREADYOUT_RNO : OR3 port map(A => N_98, B => HreadyNext_0_0_0, C => N_97, Y => HreadyNext); \CurrentState_RNIJ4KGQ[4]\ : NOR3C port map(A => arbRegSMCurrentState_RNICAHF7_0, B => Psel12Mux_0_a2_6_0, C => N_117, Y => Psel1Mux_0_a2_0_1); \HaddrReg[2]\ : DFN1E1C0 port map(D => N_18, CLK => HCLK_c, CLR => HRESETn_c, E => \iHREADYOUT_RNI2L8VN\, Q => \HaddrReg[2]_net_1\); iPSEL12_RNO_0 : NOR3C port map(A => \HaddrReg[27]_net_1\, B => \HaddrReg[26]_net_1\, C => N_124, Y => N_71); iPSEL9_RNO : AO1 port map(A => Psel5Mux_m1_e_2, B => Psel9Mux_0_a2_0_1, C => N_77, Y => Psel9Mux); iPSEL15_RNO_2 : NOR3C port map(A => Psel12Mux_0_a2_6_0, B => Psel15Mux_0_a2_0_0, C => un1_m5_0_a2_1_0, Y => Psel15Mux_0_a2_0_2); \CurrentState_RNIJ4KGQ_3[4]\ : NOR3B port map(A => Psel12Mux_0_a2_6_0, B => N_116, C => arbRegSMCurrentState_RNICAHF7_0, Y => Psel14Mux_0_a2_0_1); iHREADYOUT_RNO_4 : NOR3B port map(A => un4_valid_0, B => \un4_valid_4\, C => HreadyNext_N_7_mux, Y => HreadyNext_N_4); iHREADYOUT_RNO_0 : NOR2A port map(A => \HwriteReg\, B => \iHREADYOUT_RNIAOEJP1\, Y => N_98); iPSEL15_RNO_3 : NOR3 port map(A => N_323, B => N_263, C => HADDR_24_0_a3_i_out, Y => Psel15Mux_0_a2_0_0); iPSEL10_RNO_0 : NOR3B port map(A => \HaddrReg[27]_net_1\, B => N_127, C => \HaddrReg[26]_net_1\, Y => N_75); HwriteReg : DFN1E1C0 port map(D => N_135, CLK => HCLK_c, CLR => HRESETn_c, E => \iHREADYOUT_RNI2L8VN\, Q => \HwriteReg\); iPSEL7_RNO : AO1 port map(A => Psel2Mux_0_a2_0_2, B => Psel5Mux_m1_e_1, C => N_81, Y => Psel7Mux); iHREADYOUT_RNI2L8VN : NOR2B port map(A => CoreAHBLite_0_AHBmslave0_HSELx, B => \CoreAHBLite_0_AHBmslave0_HREADY\, Y => \iHREADYOUT_RNI2L8VN\); iPSEL8_RNO_0 : NOR3B port map(A => \HaddrReg[27]_net_1\, B => N_124, C => \HaddrReg[26]_net_1\, Y => N_79); iPSEL1 : DFN1E0C0 port map(D => Psel1Mux, CLK => HCLK_c, CLR => HRESETn_c, E => \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(1)); iHREADYOUT_RNO_3 : OR2 port map(A => \CurrentState[0]_net_1\, B => \CurrentState[2]_net_1\, Y => HreadyNext_m4_0_0); \CurrentState[1]\ : DFN1P0 port map(D => \CurrentState_ns[6]\, CLK => HCLK_c, PRE => HRESETn_c, Q => \CurrentState_i_0[1]\); \CurrentState_RNO[0]\ : AO1 port map(A => \CurrentState[3]_net_1\, B => \iHREADYOUT_RNIAOEJP1\, C => \CurrentState[2]_net_1\, Y => \CurrentState_ns[7]\); \CurrentState[2]\ : DFN1C0 port map(D => \CurrentState_RNO[2]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, Q => \CurrentState[2]_net_1\); VCC_i : VCC port map(Y => \VCC\); iPSEL6_RNO_0 : NOR3B port map(A => \HaddrReg[26]_net_1\, B => N_127, C => \HaddrReg[27]_net_1\, Y => N_83); \CurrentState_RNO[2]\ : NOR2B port map(A => \iHREADYOUT_RNIAOEJP1\, B => N_55, Y => \CurrentState_RNO[2]_net_1\); iPSEL14_RNO_0 : NOR3C port map(A => \HaddrReg[27]_net_1\, B => \HaddrReg[26]_net_1\, C => N_127, Y => N_67); un1_N_11_mux_i_0_4 : OR3A port map(A => \un4_valid_4_2\, B => \un1_N_11_mux_i_0_2\, C => \un1_N_11_mux_i_0_1\, Y => \un1_N_11_mux_i_0_4\); iPSEL6 : DFN1E0C0 port map(D => Psel6Mux_N_7_mux, CLK => HCLK_c, CLR => HRESETn_c, E => \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(6)); \CurrentState_RNIEI9B51[4]\ : AO1A port map(A => N_34, B => N_37, C => \NextState[2]\, Y => N_326_0); PENABLE : DFN1C0 port map(D => \NextState[2]\, CLK => HCLK_c, CLR => HRESETn_c, Q => CoreAPB_0_APBmslave0_PENABLE); \PWDATA[1]\ : DFN1E1C0 port map(D => CoreAHBLite_0_AHBmslave0_HWDATA(1), CLK => HCLK_c, CLR => HRESETn_c, E => N_55, Q => CoreAPB_0_APBmslave0_PWDATA(1)); \un1_m1_e_0_0\ : NOR2B port map(A => arbRegSMCurrentState_i_0_0, B => arbRegSMCurrentState_i_0_3, Y => un1_m1_e_0_0_net_1); un1_N_11_mux_i_0_1 : OR2 port map(A => N_365, B => N_366, Y => \un1_N_11_mux_i_0_1\); iPSEL1_RNO : AO1 port map(A => Psel5Mux_m1_e_2, B => Psel1Mux_0_a2_0_1, C => N_93, Y => Psel1Mux); iPSEL8 : DFN1E0C0 port map(D => Psel8Mux, CLK => HCLK_c, CLR => HRESETn_c, E => \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(8)); iPSEL11_RNO_0 : NOR3B port map(A => \HaddrReg[27]_net_1\, B => N_123, C => \HaddrReg[26]_net_1\, Y => N_73); \CurrentState_RNO_0[6]\ : OR2 port map(A => N_55, B => \NextState[2]\, Y => \CurrentState_ns_i_0_0[1]\); iPSEL8_RNO : AO1 port map(A => Psel5Mux_m1_e_2, B => Psel8Mux_0_a2_0_1, C => N_79, Y => Psel8Mux); \CurrentState_RNIJLQ3[1]\ : NOR3B port map(A => \CurrentState_i_0[5]\, B => \CurrentState_i_0[1]\, C => \CurrentState[7]_net_1\, Y => N_520); iPSEL4_RNO : AO1 port map(A => Psel5Mux_m1_e_2, B => Psel4Mux_m2_e_0_1, C => N_87, Y => Psel4Mux_N_7_mux); iHREADYOUT_RNISPLKU : NOR3C port map(A => un4_N_13_mux, B => un4_valid_0, C => CoreAHBLite_0_AHBmslave0_HSELx, Y => un4_valid_2); \HaddrReg[26]\ : DFN1E1C0 port map(D => N_124_0, CLK => HCLK_c, CLR => HRESETn_c, E => \iHREADYOUT_RNI2L8VN\, Q => \HaddrReg[26]_net_1\); iPSEL9_RNO_0 : NOR3B port map(A => \HaddrReg[27]_net_1\, B => N_128, C => \HaddrReg[26]_net_1\, Y => N_77); iPSEL7_RNO_0 : NOR3B port map(A => \HaddrReg[26]_net_1\, B => N_123, C => \HaddrReg[27]_net_1\, Y => N_81); iPSEL4_RNO_0 : NOR3B port map(A => \HaddrReg[26]_net_1\, B => N_124, C => \HaddrReg[27]_net_1\, Y => N_87); iPSEL2 : DFN1E0C0 port map(D => Psel2Mux, CLK => HCLK_c, CLR => HRESETn_c, E => \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(2)); \un1_N_11_mux_i_5_a1_1\ : NOR2B port map(A => \N_398\, B => HTRANS_0_a3_i_a2_4_0, Y => un1_N_11_mux_i_5_a1_1_net_1); iPSEL11_RNO : AO1 port map(A => Psel2Mux_0_a2_0_2, B => Psel9Mux_0_a2_0_1, C => N_73, Y => Psel11Mux); iPSEL0 : DFN1E0C0 port map(D => Psel0Mux, CLK => HCLK_c, CLR => HRESETn_c, E => \NextState[2]\, Q => CoreAPB_0_APBmslave0_PSELx); iHREADYOUT_RNI97C92 : NOR3B port map(A => N_326, B => \CoreAHBLite_0_AHBmslave0_HREADY\, C => N_263, Y => un1_m5_0_a2_5_1); iPSEL3_RNO_0 : NOR3A port map(A => N_123, B => \HaddrReg[27]_net_1\, C => \HaddrReg[26]_net_1\, Y => N_89); \PADDR[3]\ : DFN1E0C0 port map(D => \HaddrMux[3]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_326_0, Q => CoreAPB_0_APBmslave0_PADDR(3)); \CurrentState[6]\ : DFN1C0 port map(D => \CurrentState_RNO[6]_net_1\, CLK => HCLK_c, CLR => HRESETn_c, Q => \CurrentState[6]_net_1\); iPSEL0_RNO : AO1 port map(A => Psel5Mux_m1_e_2, B => Psel0Mux_0_a2_0_1, C => N_95, Y => Psel0Mux); iPSEL10_RNO : AO1 port map(A => Psel2Mux_0_a2_0_2, B => Psel8Mux_0_a2_0_1, C => N_75, Y => Psel10Mux); PWRITE : DFN1E0C0 port map(D => N_55, CLK => HCLK_c, CLR => HRESETn_c, E => N_326_0, Q => CoreAPB_0_APBmslave0_PWRITE); iPSEL2_RNO_0 : NOR3A port map(A => N_127, B => \HaddrReg[27]_net_1\, C => \HaddrReg[26]_net_1\, Y => N_91); \HaddrReg_RNINSQI_0[24]\ : NOR3A port map(A => \HaddrReg[24]_net_1\, B => N_339, C => \HaddrReg[25]_net_1\, Y => N_128); \CurrentState[5]\ : DFN1P0 port map(D => \CurrentState_i[6]\, CLK => HCLK_c, PRE => HRESETn_c, Q => \CurrentState_i_0[5]\); un4_valid_4 : NOR3B port map(A => \un4_valid_4_1\, B => \un4_valid_4_2\, C => N_367, Y => \un4_valid_4\); \HaddrReg[4]\ : DFN1E1C0 port map(D => N_22, CLK => HCLK_c, CLR => HRESETn_c, E => \iHREADYOUT_RNI2L8VN\, Q => \HaddrReg[4]_net_1\); \PWDATA[6]\ : DFN1E1C0 port map(D => CoreAHBLite_0_AHBmslave0_HWDATA(6), CLK => HCLK_c, CLR => HRESETn_c, E => N_55, Q => CoreAPB_0_APBmslave0_PWDATA(6)); \CurrentState_RNO[6]\ : OA1C port map(A => N_37, B => \CurrentState[0]_net_1\, C => \CurrentState_ns_i_0_0[1]\, Y => \CurrentState_RNO[6]_net_1\); \CurrentState[3]\ : DFN1C0 port map(D => \CurrentState_ns[4]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \CurrentState[3]_net_1\); \CurrentState[0]\ : DFN1C0 port map(D => \CurrentState_ns[7]\, CLK => HCLK_c, CLR => HRESETn_c, Q => \CurrentState[0]_net_1\); iPSEL11 : DFN1E0C0 port map(D => Psel11Mux, CLK => HCLK_c, CLR => HRESETn_c, E => \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(11)); iPSEL13_RNO_1 : NOR3C port map(A => \HaddrReg[27]_net_1\, B => \HaddrReg[26]_net_1\, C => N_128, Y => N_69); \PADDR_RNO[4]\ : MX2 port map(A => \HaddrReg[4]_net_1\, B => N_22, S => N_339, Y => \HaddrMux[4]\); Psel3Mux_0_a2_2 : NOR2 port map(A => N_128_0, B => N_124_0, Y => N_117); iHREADYOUT_RNO_8 : NOR3A port map(A => N_397, B => N_330, C => N_171, Y => HreadyNext_m2_e_0); iPSEL5_RNO_0 : NOR3B port map(A => \HaddrReg[26]_net_1\, B => N_128, C => \HaddrReg[27]_net_1\, Y => N_85); iPSEL5 : DFN1E0C0 port map(D => Psel5Mux_N_5_mux_0, CLK => HCLK_c, CLR => HRESETn_c, E => \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(5)); \CurrentState_RNO[4]\ : NOR3B port map(A => \iHREADYOUT_RNIAOEJP1\, B => N_135, C => N_520, Y => N_102); \CurrentState[4]\ : DFN1C0 port map(D => N_102, CLK => HCLK_c, CLR => HRESETn_c, Q => \CurrentState[4]_net_1\); \PADDR[4]\ : DFN1E0C0 port map(D => \HaddrMux[4]\, CLK => HCLK_c, CLR => HRESETn_c, E => N_326_0, Q => CoreAPB_0_APBmslave0_PADDR(4)); iHREADYOUT_RNITE0M3 : OA1A port map(A => un1_m1_e_0_0_net_1, B => N_254, C => un1_m5_0_a2_5_1, Y => un1_m5_0_a2_5_2); \HaddrReg_RNINSQI_2[24]\ : NOR3 port map(A => N_339, B => \HaddrReg[24]_net_1\, C => \HaddrReg[25]_net_1\, Y => N_124); iPSEL15 : DFN1E0C0 port map(D => Psel15Mux, CLK => HCLK_c, CLR => HRESETn_c, E => \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(15)); \CurrentState_RNI8KH2[4]\ : OR2 port map(A => \CurrentState[4]_net_1\, B => \CurrentState[0]_net_1\, Y => N_34); \CurrentState_RNO[5]\ : INV port map(A => \CurrentState[6]_net_1\, Y => \CurrentState_i[6]\); un1_N_11_mux_i_5_a0_1 : NOR2B port map(A => \N_398\, B => N_391, Y => \un1_N_11_mux_i_5_a0_1\); \PADDR_RNO[3]\ : MX2 port map(A => \HaddrReg[3]_net_1\, B => N_20, S => N_339, Y => \HaddrMux[3]\); un1_N_11_mux_i_5_a0_0 : NOR2 port map(A => defSlaveSMCurrentState, B => xhdl1222_0, Y => \N_398\); iPSEL6_RNO : AO1 port map(A => Psel2Mux_0_a2_0_2, B => Psel4Mux_m2_e_0_1, C => N_83, Y => Psel6Mux_N_7_mux); Psel7Mux_0_a2_1 : NOR2A port map(A => N_124_0, B => N_128_0, Y => N_118); \PWDATA[5]\ : DFN1E1C0 port map(D => CoreAHBLite_0_AHBmslave0_HWDATA(5), CLK => HCLK_c, CLR => HRESETn_c, E => N_55, Q => CoreAPB_0_APBmslave0_PWDATA(5)); iPSEL5_RNO : AO1 port map(A => Psel5Mux_m1_e_2, B => Psel5Mux_m1_e_1, C => N_85, Y => Psel5Mux_N_5_mux_0); iPSEL13 : DFN1E0C0 port map(D => Psel13Mux, CLK => HCLK_c, CLR => HRESETn_c, E => \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(13)); \CurrentState_RNIHJQ3[6]\ : OR3 port map(A => \CurrentState[2]_net_1\, B => \CurrentState[3]_net_1\, C => \CurrentState[6]_net_1\, Y => \NextState[2]\); \HaddrReg[25]\ : DFN1E1C0 port map(D => N_120, CLK => HCLK_c, CLR => HRESETn_c, E => \iHREADYOUT_RNI2L8VN\, Q => \HaddrReg[25]_net_1\); un1_m5_0_a2_a1 : OA1A port map(A => N_397, B => N_330, C => un1_m1_e_0_0_net_1, Y => \un1_m5_0_a2_a1\); \CurrentState_RNIF8AB[4]\ : AO1 port map(A => \HwriteReg\, B => \CurrentState[0]_net_1\, C => \CurrentState[4]_net_1\, Y => N_55); \HaddrReg[24]\ : DFN1E1C0 port map(D => arbRegSMCurrentState_RNICAHF7_0, CLK => HCLK_c, CLR => HRESETn_c, E => \iHREADYOUT_RNI2L8VN\, Q => \HaddrReg[24]_net_1\); iPSEL14_RNO : AO1 port map(A => Psel2Mux_0_a2_0_2, B => Psel14Mux_0_a2_0_1, C => N_67, Y => Psel14Mux); iHREADYOUT_RNIQN2S8 : NOR3B port map(A => un1_m5_0_a2_5_2, B => un1_N_5_mux, C => \un1_m5_0_a2_a1\, Y => un1_m5_0_a2_1_0); Psel15Mux_0_a2_2 : NOR2B port map(A => N_128_0, B => N_124_0, Y => N_116); \PWDATA[2]\ : DFN1E1C0 port map(D => CoreAHBLite_0_AHBmslave0_HWDATA(2), CLK => HCLK_c, CLR => HRESETn_c, E => N_55, Q => CoreAPB_0_APBmslave0_PWDATA(2)); Psel11Mux_0_a2_1 : NOR2A port map(A => N_128_0, B => N_124_0, Y => N_119); \CurrentState_RNIJ4KGQ_1[4]\ : NOR3C port map(A => arbRegSMCurrentState_RNICAHF7_0, B => Psel12Mux_0_a2_6_0, C => N_119, Y => Psel9Mux_0_a2_0_1); iPSEL14 : DFN1E0C0 port map(D => Psel14Mux, CLK => HCLK_c, CLR => HRESETn_c, E => \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(14)); \CurrentState_RNO[7]\ : NOR2 port map(A => N_520, B => \iHREADYOUT_RNIAOEJP1\, Y => N_104); iPSEL7 : DFN1E0C0 port map(D => Psel7Mux, CLK => HCLK_c, CLR => HRESETn_c, E => \NextState[2]\, Q => CoreAHB2APB_0_APBmaster_PSELx(7)); \PWDATA[3]\ : DFN1E1C0 port map(D => CoreAHBLite_0_AHBmslave0_HWDATA(3), CLK => HCLK_c, CLR => HRESETn_c, E => N_55, Q => CoreAPB_0_APBmslave0_PWDATA(3)); iHREADYOUT_RNIAOEJP1 : NOR2B port map(A => un4_valid_2, B => \un4_valid_4\, Y => \iHREADYOUT_RNIAOEJP1\); \CurrentState_RNIP7C6[4]\ : NOR2 port map(A => N_34, B => \NextState[2]\, Y => Psel12Mux_0_a2_6_0); un1_N_11_mux_i_a1 : NOR3C port map(A => N_392, B => N_265, C => HTRANS_0_a3_i_a2_3_0, Y => N_366); un4_valid_4_1 : NOR3A port map(A => N_254, B => N_365, C => N_366, Y => \un4_valid_4_1\); iPSEL15_RNO_0 : NOR3C port map(A => \un4_valid_4\, B => masterAddrInProg_i_1_0, C => Psel15Mux_0_a2_0_2, Y => Psel15Mux_0_a2_0_4); end DEF_ARCH; library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity top is port( ADDR : in std_logic_vector(31 downto 0); DATAIN : in std_logic_vector(31 downto 0); HCLK : in std_logic; HRESETn : in std_logic; LREAD : in std_logic; LWRITE : in std_logic; DATAOUT : out std_logic_vector(31 downto 0); RESP_err : out std_logic_vector(1 downto 0); TX : out std_logic; ahb_busy : out std_logic ); end top; architecture DEF_ARCH of top is component OUTBUF port( D : in std_logic := 'U'; PAD : out std_logic ); end component; component AHBMASTER_FIC port( AHBMASTER_FIC_0_AHBmaster_HADDR_0 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_1 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_2 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_22 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_23 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_24 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_25 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_26 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_27 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_28 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HADDR_29 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HRDATA : in std_logic_vector(7 downto 0) := (others => 'U'); DATAOUT_c : out std_logic_vector(7 downto 0); DATAIN_c : in std_logic_vector(7 downto 0) := (others => 'U'); AHBMASTER_FIC_0_AHBmaster_HWDATA : out std_logic_vector(7 downto 0); AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : out std_logic; ADDR_c_29 : in std_logic := 'U'; ADDR_c_23 : in std_logic := 'U'; ADDR_c_26 : in std_logic := 'U'; ADDR_c_22 : in std_logic := 'U'; ADDR_c_24 : in std_logic := 'U'; ADDR_c_25 : in std_logic := 'U'; ADDR_c_27 : in std_logic := 'U'; ADDR_c_1 : in std_logic := 'U'; ADDR_c_0 : in std_logic := 'U'; ADDR_c_28 : in std_logic := 'U'; ADDR_c_2 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HWRITE : out std_logic; HCLK_c : in std_logic := 'U'; ahb_busy_c : out std_logic; HRESETn_c : in std_logic := 'U'; PREVDATASLAVEREADY_iv_i_0_i_o4_0 : in std_logic := 'U'; N_163 : in std_logic := 'U'; LWRITE_c : in std_logic := 'U'; LREAD_c : in std_logic := 'U'; N_398 : in std_logic := 'U'; PREVDATASLAVEREADY_iv_i_0_i_o4_1 : in std_logic := 'U'; N_340 : in std_logic := 'U' ); end component; component INBUF port( PAD : in std_logic := 'U'; Y : out std_logic ); end component; component VCC port( Y : out std_logic ); end component; component COREAPB port( CoreAHB2APB_0_APBmaster_PSELx : in std_logic_vector(15 downto 1) := (others => 'U'); PRDATA_0_sqmuxa_0_a2_13 : out std_logic; CoreAPB_0_APBmslave0_PSELx : in std_logic := 'U'; PRDATA_0_sqmuxa_0_a2_12 : out std_logic ); end component; component CLKBUF port( PAD : in std_logic := 'U'; Y : out std_logic ); end component; component top_CoreAHBLite_0_CoreAHBLite port( AHBMASTER_FIC_0_AHBmaster_HADDR_26 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_27 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_28 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_29 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_0 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_1 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_2 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_22 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_23 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_24 : in std_logic := 'U'; AHBMASTER_FIC_0_AHBmaster_HADDR_25 : in std_logic := 'U'; masterAddrInProg_i_1_0 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HRDATA : out std_logic_vector(7 downto 0); xhdl1222_0 : out std_logic; CoreAPB_0_APBmslave0_PRDATA : in std_logic_vector(7 downto 0) := (others => 'U'); AHBMASTER_FIC_0_AHBmaster_HTRANS_0 : in std_logic := 'U'; arbRegSMCurrentState_RNICAHF7_0 : out std_logic; arbRegSMCurrentState_i_0_3 : out std_logic; arbRegSMCurrentState_i_0_0 : out std_logic; AHBMASTER_FIC_0_AHBmaster_HWDATA : in std_logic_vector(7 downto 0) := (others => 'U'); CoreAHBLite_0_AHBmslave0_HWDATA : out std_logic_vector(7 downto 0); defSlaveSMCurrentState : out std_logic; AHBMASTER_FIC_0_AHBmaster_HWRITE : in std_logic := 'U'; HRESETn_c : in std_logic := 'U'; HCLK_c : in std_logic := 'U'; N_163 : out std_logic; CoreAHBLite_0_AHBmslave0_HREADY : in std_logic := 'U'; N_254 : out std_logic; N_395 : out std_logic; N_265 : out std_logic; N_339_c : out std_logic; PREVDATASLAVEREADY_iv_i_0_i_o4_0 : out std_logic; PREVDATASLAVEREADY_iv_i_0_i_o4_1 : out std_logic; N_392 : out std_logic; N_391 : out std_logic; PRDATA_0_sqmuxa_0_a2_13 : in std_logic := 'U'; PRDATA_0_sqmuxa_0_a2_12 : in std_logic := 'U'; N_327 : out std_logic; N_340 : out std_logic; N_330 : out std_logic; N_397 : out std_logic; N_398 : in std_logic := 'U'; N_171 : out std_logic; N_263 : out std_logic; N_367 : out std_logic; un1_N_11_mux_i_5_a1_1 : in std_logic := 'U'; CoreAHBLite_0_AHBmslave0_HSELx : out std_logic; N_363 : out std_logic; HADDR_24_0_a3_i_out : out std_logic; un4_m5_0_a3_2 : in std_logic := 'U'; N_128 : out std_logic; N_124 : out std_logic; N_120 : out std_logic; N_22 : out std_logic; N_20 : out std_logic; N_135 : out std_logic; N_18 : out std_logic; N_326 : out std_logic; N_323 : out std_logic; HTRANS_0_a3_i_a2_3_0 : out std_logic; HTRANS_0_a3_i_a2_4_0 : out std_logic; N_365 : out std_logic; N_364 : out std_logic; un1_m1_e_0_0 : in std_logic := 'U'; un4_m5_0_a3_1 : in std_logic := 'U' ); end component; component GND port( Y : out std_logic ); end component; component top_CoreUARTapb_0_CoreUARTapb port( CoreAPB_0_APBmslave0_PRDATA : out std_logic_vector(7 downto 0); CoreAPB_0_APBmslave0_PWDATA : in std_logic_vector(7 downto 0) := (others => 'U'); CoreAPB_0_APBmslave0_PADDR : in std_logic_vector(4 downto 2) := (others => 'U'); TX_c : out std_logic; HRESETn_c : in std_logic := 'U'; HCLK_c : in std_logic := 'U'; CoreAPB_0_APBmslave0_PENABLE : in std_logic := 'U'; CoreAPB_0_APBmslave0_PWRITE : in std_logic := 'U'; CoreAPB_0_APBmslave0_PSELx : in std_logic := 'U' ); end component; component CoreAHB2APB port( CoreAHBLite_0_AHBmslave0_HWDATA : in std_logic_vector(7 downto 0) := (others => 'U'); CoreAPB_0_APBmslave0_PWDATA : out std_logic_vector(7 downto 0); CoreAPB_0_APBmslave0_PADDR : out std_logic_vector(4 downto 2); CoreAHB2APB_0_APBmaster_PSELx : out std_logic_vector(15 downto 1); arbRegSMCurrentState_i_0_0 : in std_logic := 'U'; arbRegSMCurrentState_i_0_3 : in std_logic := 'U'; xhdl1222_0 : in std_logic := 'U'; masterAddrInProg_i_1_0 : in std_logic := 'U'; arbRegSMCurrentState_RNICAHF7_0 : in std_logic := 'U'; CoreAPB_0_APBmslave0_PWRITE : out std_logic; CoreAPB_0_APBmslave0_PSELx : out std_logic; HRESETn_c : in std_logic := 'U'; HCLK_c : in std_logic := 'U'; CoreAPB_0_APBmslave0_PENABLE : out std_logic; N_124_0 : in std_logic := 'U'; N_128_0 : in std_logic := 'U'; N_22 : in std_logic := 'U'; N_20 : in std_logic := 'U'; N_18 : in std_logic := 'U'; N_395 : in std_logic := 'U'; N_363 : in std_logic := 'U'; N_364 : in std_logic := 'U'; HTRANS_0_a3_i_a2_3_0 : in std_logic := 'U'; N_265 : in std_logic := 'U'; N_392 : in std_logic := 'U'; N_135 : in std_logic := 'U'; N_367 : in std_logic := 'U'; defSlaveSMCurrentState : in std_logic := 'U'; N_391 : in std_logic := 'U'; HTRANS_0_a3_i_a2_4_0 : in std_logic := 'U'; N_398 : out std_logic; un1_N_11_mux_i_5_a1_1 : out std_logic; N_327 : in std_logic := 'U'; un4_m5_0_a3_1 : out std_logic; un4_m5_0_a3_2 : out std_logic; N_171 : in std_logic := 'U'; N_330 : in std_logic := 'U'; N_397 : in std_logic := 'U'; N_326 : in std_logic := 'U'; un1_m1_e_0_0 : out std_logic; CoreAHBLite_0_AHBmslave0_HREADY : out std_logic; CoreAHBLite_0_AHBmslave0_HSELx : in std_logic := 'U'; HADDR_24_0_a3_i_out : in std_logic := 'U'; N_263 : in std_logic := 'U'; N_323 : in std_logic := 'U'; N_365 : in std_logic := 'U'; N_254 : in std_logic := 'U'; N_120 : in std_logic := 'U' ); end component; signal \AHBMASTER_FIC_0_AHBmaster_HADDR[2]\, \AHBMASTER_FIC_0_AHBmaster_HADDR[3]\, \AHBMASTER_FIC_0_AHBmaster_HADDR[4]\, \AHBMASTER_FIC_0_AHBmaster_HADDR[24]\, \AHBMASTER_FIC_0_AHBmaster_HADDR[25]\, \AHBMASTER_FIC_0_AHBmaster_HADDR[26]\, \AHBMASTER_FIC_0_AHBmaster_HADDR[27]\, \AHBMASTER_FIC_0_AHBmaster_HADDR[28]\, \AHBMASTER_FIC_0_AHBmaster_HADDR[29]\, \AHBMASTER_FIC_0_AHBmaster_HADDR[30]\, \AHBMASTER_FIC_0_AHBmaster_HADDR[31]\, \AHBMASTER_FIC_0_AHBmaster_HTRANS[1]\, AHBMASTER_FIC_0_AHBmaster_HWRITE, \AHBMASTER_FIC_0_AHBmaster_HWDATA[0]\, \AHBMASTER_FIC_0_AHBmaster_HWDATA[1]\, \AHBMASTER_FIC_0_AHBmaster_HWDATA[2]\, \AHBMASTER_FIC_0_AHBmaster_HWDATA[3]\, \AHBMASTER_FIC_0_AHBmaster_HWDATA[4]\, \AHBMASTER_FIC_0_AHBmaster_HWDATA[5]\, \AHBMASTER_FIC_0_AHBmaster_HWDATA[6]\, \AHBMASTER_FIC_0_AHBmaster_HWDATA[7]\, CoreAHBLite_0_AHBmslave0_HREADY, \CoreAPB_0_APBmslave0_PWDATA[0]\, \CoreAPB_0_APBmslave0_PWDATA[1]\, \CoreAPB_0_APBmslave0_PWDATA[2]\, \CoreAPB_0_APBmslave0_PWDATA[3]\, \CoreAPB_0_APBmslave0_PWDATA[4]\, \CoreAPB_0_APBmslave0_PWDATA[5]\, \CoreAPB_0_APBmslave0_PWDATA[6]\, \CoreAPB_0_APBmslave0_PWDATA[7]\, CoreAPB_0_APBmslave0_PENABLE, CoreAPB_0_APBmslave0_PSELx, \CoreAHB2APB_0_APBmaster_PSELx[1]\, \CoreAHB2APB_0_APBmaster_PSELx[2]\, \CoreAHB2APB_0_APBmaster_PSELx[3]\, \CoreAHB2APB_0_APBmaster_PSELx[4]\, \CoreAHB2APB_0_APBmaster_PSELx[5]\, \CoreAHB2APB_0_APBmaster_PSELx[6]\, \CoreAHB2APB_0_APBmaster_PSELx[7]\, \CoreAHB2APB_0_APBmaster_PSELx[8]\, \CoreAHB2APB_0_APBmaster_PSELx[9]\, \CoreAHB2APB_0_APBmaster_PSELx[10]\, \CoreAHB2APB_0_APBmaster_PSELx[11]\, \CoreAHB2APB_0_APBmaster_PSELx[12]\, \CoreAHB2APB_0_APBmaster_PSELx[13]\, \CoreAHB2APB_0_APBmaster_PSELx[14]\, \CoreAHB2APB_0_APBmaster_PSELx[15]\, \CoreAPB_0_APBmslave0_PADDR[2]\, \CoreAPB_0_APBmslave0_PADDR[3]\, \CoreAPB_0_APBmslave0_PADDR[4]\, CoreAPB_0_APBmslave0_PWRITE, \VCC\, \CoreAPB_0_APBmslave0_PRDATA[0]\, \CoreAPB_0_APBmslave0_PRDATA[1]\, \CoreAPB_0_APBmslave0_PRDATA[2]\, \CoreAPB_0_APBmslave0_PRDATA[3]\, \CoreAPB_0_APBmslave0_PRDATA[4]\, \CoreAPB_0_APBmslave0_PRDATA[5]\, \CoreAPB_0_APBmslave0_PRDATA[6]\, \CoreAPB_0_APBmslave0_PRDATA[7]\, \CoreAHBLite_0.matrix4x16.xhdl1222[0]\, \CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMCurrentState\, N_120, N_124, N_128, N_135, N_163, N_254, N_263, N_265, N_340, N_363, N_364, N_365, N_367, N_397, \ADDR_c[2]\, \ADDR_c[3]\, \ADDR_c[4]\, \ADDR_c[24]\, \ADDR_c[25]\, \ADDR_c[26]\, \ADDR_c[27]\, \ADDR_c[28]\, \ADDR_c[29]\, \ADDR_c[30]\, \ADDR_c[31]\, \DATAIN_c[0]\, \DATAIN_c[1]\, \DATAIN_c[2]\, \DATAIN_c[3]\, \DATAIN_c[4]\, \DATAIN_c[5]\, \DATAIN_c[6]\, \DATAIN_c[7]\, HCLK_c, HRESETn_c, LREAD_c, LWRITE_c, \DATAOUT_c[0]\, \DATAOUT_c[1]\, \DATAOUT_c[2]\, \DATAOUT_c[3]\, \DATAOUT_c[4]\, \DATAOUT_c[5]\, \DATAOUT_c[6]\, \DATAOUT_c[7]\, N_339_c, \GND\, TX_c, ahb_busy_c, N_22, N_20, N_18, \CoreAHBLite_0.matrix4x16.slavestage_0.masterAddrInProg_i_1[0]\, CoreAHBLite_0_AHBmslave0_HSELx, N_391, N_326, \CoreAHBLite_0_AHBmslave0_HWDATA[7]\, \CoreAHBLite_0_AHBmslave0_HWDATA[6]\, \CoreAHBLite_0_AHBmslave0_HWDATA[5]\, \CoreAHBLite_0_AHBmslave0_HWDATA[4]\, \CoreAHBLite_0_AHBmslave0_HWDATA[3]\, \CoreAHBLite_0_AHBmslave0_HWDATA[2]\, \CoreAHBLite_0_AHBmslave0_HWDATA[1]\, \CoreAHBLite_0_AHBmslave0_HWDATA[0]\, N_327, N_330, N_323, N_395, N_392, \CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.N_171\, \AHBMASTER_FIC_0_AHBmaster_HRDATA[7]\, \AHBMASTER_FIC_0_AHBmaster_HRDATA[6]\, \AHBMASTER_FIC_0_AHBmaster_HRDATA[5]\, \AHBMASTER_FIC_0_AHBmaster_HRDATA[4]\, \AHBMASTER_FIC_0_AHBmaster_HRDATA[3]\, \AHBMASTER_FIC_0_AHBmaster_HRDATA[2]\, \AHBMASTER_FIC_0_AHBmaster_HRDATA[1]\, \AHBMASTER_FIC_0_AHBmaster_HRDATA[0]\, \CoreAHBLite_0.matrix4x16.slavestage_0.HTRANS_0_a3_i_a2_3_0\, \CoreAHBLite_0.matrix4x16.slavestage_0.HTRANS_0_a3_i_a2_4_0\, \CoreAHBLite_0.matrix4x16.masterstage_0.PREVDATASLAVEREADY_iv_i_0_i_o4_0\, \CoreAHBLite_0.matrix4x16.masterstage_0.PREVDATASLAVEREADY_iv_i_0_i_o4_1\, \CoreAHB2APB_0.un1_m1_e_0_0\, \CoreAHBLite_0.matrix4x16.slavestage_0.HADDR_24_0_a3_i_out\, \arbRegSMCurrentState_RNICAHF7[0]\, \CoreAPB_0.COREAPB_oi0.PRDATA_0_sqmuxa_0_a2_12\, \CoreAPB_0.COREAPB_oi0.PRDATA_0_sqmuxa_0_a2_13\, N_398, \CoreAHB2APB_0.un1_N_11_mux_i_5_a1_1\, \CoreAHB2APB_0.un4_m5_0_a3_1\, \CoreAHB2APB_0.un4_m5_0_a3_2\, \CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_i_0[12]\, \CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_i_0[15]\ : std_logic; for all : AHBMASTER_FIC Use entity work.AHBMASTER_FIC(DEF_ARCH); for all : COREAPB Use entity work.COREAPB(DEF_ARCH); for all : top_CoreAHBLite_0_CoreAHBLite Use entity work.top_CoreAHBLite_0_CoreAHBLite(DEF_ARCH); for all : top_CoreUARTapb_0_CoreUARTapb Use entity work.top_CoreUARTapb_0_CoreUARTapb(DEF_ARCH); for all : CoreAHB2APB Use entity work.CoreAHB2APB(DEF_ARCH); begin \DATAOUT_pad[16]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(16)); AHBMASTER_FIC_0 : AHBMASTER_FIC port map(AHBMASTER_FIC_0_AHBmaster_HADDR_0 => \AHBMASTER_FIC_0_AHBmaster_HADDR[2]\, AHBMASTER_FIC_0_AHBmaster_HADDR_1 => \AHBMASTER_FIC_0_AHBmaster_HADDR[3]\, AHBMASTER_FIC_0_AHBmaster_HADDR_2 => \AHBMASTER_FIC_0_AHBmaster_HADDR[4]\, AHBMASTER_FIC_0_AHBmaster_HADDR_22 => \AHBMASTER_FIC_0_AHBmaster_HADDR[24]\, AHBMASTER_FIC_0_AHBmaster_HADDR_23 => \AHBMASTER_FIC_0_AHBmaster_HADDR[25]\, AHBMASTER_FIC_0_AHBmaster_HADDR_24 => \AHBMASTER_FIC_0_AHBmaster_HADDR[26]\, AHBMASTER_FIC_0_AHBmaster_HADDR_25 => \AHBMASTER_FIC_0_AHBmaster_HADDR[27]\, AHBMASTER_FIC_0_AHBmaster_HADDR_26 => \AHBMASTER_FIC_0_AHBmaster_HADDR[28]\, AHBMASTER_FIC_0_AHBmaster_HADDR_27 => \AHBMASTER_FIC_0_AHBmaster_HADDR[29]\, AHBMASTER_FIC_0_AHBmaster_HADDR_28 => \AHBMASTER_FIC_0_AHBmaster_HADDR[30]\, AHBMASTER_FIC_0_AHBmaster_HADDR_29 => \AHBMASTER_FIC_0_AHBmaster_HADDR[31]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(7) => \AHBMASTER_FIC_0_AHBmaster_HRDATA[7]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(6) => \AHBMASTER_FIC_0_AHBmaster_HRDATA[6]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(5) => \AHBMASTER_FIC_0_AHBmaster_HRDATA[5]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(4) => \AHBMASTER_FIC_0_AHBmaster_HRDATA[4]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(3) => \AHBMASTER_FIC_0_AHBmaster_HRDATA[3]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(2) => \AHBMASTER_FIC_0_AHBmaster_HRDATA[2]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(1) => \AHBMASTER_FIC_0_AHBmaster_HRDATA[1]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(0) => \AHBMASTER_FIC_0_AHBmaster_HRDATA[0]\, DATAOUT_c(7) => \DATAOUT_c[7]\, DATAOUT_c(6) => \DATAOUT_c[6]\, DATAOUT_c(5) => \DATAOUT_c[5]\, DATAOUT_c(4) => \DATAOUT_c[4]\, DATAOUT_c(3) => \DATAOUT_c[3]\, DATAOUT_c(2) => \DATAOUT_c[2]\, DATAOUT_c(1) => \DATAOUT_c[1]\, DATAOUT_c(0) => \DATAOUT_c[0]\, DATAIN_c(7) => \DATAIN_c[7]\, DATAIN_c(6) => \DATAIN_c[6]\, DATAIN_c(5) => \DATAIN_c[5]\, DATAIN_c(4) => \DATAIN_c[4]\, DATAIN_c(3) => \DATAIN_c[3]\, DATAIN_c(2) => \DATAIN_c[2]\, DATAIN_c(1) => \DATAIN_c[1]\, DATAIN_c(0) => \DATAIN_c[0]\, AHBMASTER_FIC_0_AHBmaster_HWDATA(7) => \AHBMASTER_FIC_0_AHBmaster_HWDATA[7]\, AHBMASTER_FIC_0_AHBmaster_HWDATA(6) => \AHBMASTER_FIC_0_AHBmaster_HWDATA[6]\, AHBMASTER_FIC_0_AHBmaster_HWDATA(5) => \AHBMASTER_FIC_0_AHBmaster_HWDATA[5]\, AHBMASTER_FIC_0_AHBmaster_HWDATA(4) => \AHBMASTER_FIC_0_AHBmaster_HWDATA[4]\, AHBMASTER_FIC_0_AHBmaster_HWDATA(3) => \AHBMASTER_FIC_0_AHBmaster_HWDATA[3]\, AHBMASTER_FIC_0_AHBmaster_HWDATA(2) => \AHBMASTER_FIC_0_AHBmaster_HWDATA[2]\, AHBMASTER_FIC_0_AHBmaster_HWDATA(1) => \AHBMASTER_FIC_0_AHBmaster_HWDATA[1]\, AHBMASTER_FIC_0_AHBmaster_HWDATA(0) => \AHBMASTER_FIC_0_AHBmaster_HWDATA[0]\, AHBMASTER_FIC_0_AHBmaster_HTRANS_0 => \AHBMASTER_FIC_0_AHBmaster_HTRANS[1]\, ADDR_c_29 => \ADDR_c[31]\, ADDR_c_23 => \ADDR_c[25]\, ADDR_c_26 => \ADDR_c[28]\, ADDR_c_22 => \ADDR_c[24]\, ADDR_c_24 => \ADDR_c[26]\, ADDR_c_25 => \ADDR_c[27]\, ADDR_c_27 => \ADDR_c[29]\, ADDR_c_1 => \ADDR_c[3]\, ADDR_c_0 => \ADDR_c[2]\, ADDR_c_28 => \ADDR_c[30]\, ADDR_c_2 => \ADDR_c[4]\, AHBMASTER_FIC_0_AHBmaster_HWRITE => AHBMASTER_FIC_0_AHBmaster_HWRITE, HCLK_c => HCLK_c, ahb_busy_c => ahb_busy_c, HRESETn_c => HRESETn_c, PREVDATASLAVEREADY_iv_i_0_i_o4_0 => \CoreAHBLite_0.matrix4x16.masterstage_0.PREVDATASLAVEREADY_iv_i_0_i_o4_0\, N_163 => N_163, LWRITE_c => LWRITE_c, LREAD_c => LREAD_c, N_398 => N_398, PREVDATASLAVEREADY_iv_i_0_i_o4_1 => \CoreAHBLite_0.matrix4x16.masterstage_0.PREVDATASLAVEREADY_iv_i_0_i_o4_1\, N_340 => N_340); \DATAOUT_pad[25]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(25)); \DATAIN_pad[4]\ : INBUF port map(PAD => DATAIN(4), Y => \DATAIN_c[4]\); \DATAIN_pad[5]\ : INBUF port map(PAD => DATAIN(5), Y => \DATAIN_c[5]\); \DATAIN_pad[7]\ : INBUF port map(PAD => DATAIN(7), Y => \DATAIN_c[7]\); \DATAOUT_pad[2]\ : OUTBUF port map(D => \DATAOUT_c[2]\, PAD => DATAOUT(2)); \DATAIN_pad[2]\ : INBUF port map(PAD => DATAIN(2), Y => \DATAIN_c[2]\); \ADDR_pad[28]\ : INBUF port map(PAD => ADDR(28), Y => \ADDR_c[28]\); \DATAOUT_pad[27]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(27)); \DATAOUT_pad[18]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(18)); \DATAOUT_pad[0]\ : OUTBUF port map(D => \DATAOUT_c[0]\, PAD => DATAOUT(0)); VCC_i : VCC port map(Y => \VCC\); CoreAPB_0 : COREAPB port map(CoreAHB2APB_0_APBmaster_PSELx(15) => \CoreAHB2APB_0_APBmaster_PSELx[15]\, CoreAHB2APB_0_APBmaster_PSELx(14) => \CoreAHB2APB_0_APBmaster_PSELx[14]\, CoreAHB2APB_0_APBmaster_PSELx(13) => \CoreAHB2APB_0_APBmaster_PSELx[13]\, CoreAHB2APB_0_APBmaster_PSELx(12) => \CoreAHB2APB_0_APBmaster_PSELx[12]\, CoreAHB2APB_0_APBmaster_PSELx(11) => \CoreAHB2APB_0_APBmaster_PSELx[11]\, CoreAHB2APB_0_APBmaster_PSELx(10) => \CoreAHB2APB_0_APBmaster_PSELx[10]\, CoreAHB2APB_0_APBmaster_PSELx(9) => \CoreAHB2APB_0_APBmaster_PSELx[9]\, CoreAHB2APB_0_APBmaster_PSELx(8) => \CoreAHB2APB_0_APBmaster_PSELx[8]\, CoreAHB2APB_0_APBmaster_PSELx(7) => \CoreAHB2APB_0_APBmaster_PSELx[7]\, CoreAHB2APB_0_APBmaster_PSELx(6) => \CoreAHB2APB_0_APBmaster_PSELx[6]\, CoreAHB2APB_0_APBmaster_PSELx(5) => \CoreAHB2APB_0_APBmaster_PSELx[5]\, CoreAHB2APB_0_APBmaster_PSELx(4) => \CoreAHB2APB_0_APBmaster_PSELx[4]\, CoreAHB2APB_0_APBmaster_PSELx(3) => \CoreAHB2APB_0_APBmaster_PSELx[3]\, CoreAHB2APB_0_APBmaster_PSELx(2) => \CoreAHB2APB_0_APBmaster_PSELx[2]\, CoreAHB2APB_0_APBmaster_PSELx(1) => \CoreAHB2APB_0_APBmaster_PSELx[1]\, PRDATA_0_sqmuxa_0_a2_13 => \CoreAPB_0.COREAPB_oi0.PRDATA_0_sqmuxa_0_a2_13\, CoreAPB_0_APBmslave0_PSELx => CoreAPB_0_APBmslave0_PSELx, PRDATA_0_sqmuxa_0_a2_12 => \CoreAPB_0.COREAPB_oi0.PRDATA_0_sqmuxa_0_a2_12\); \DATAOUT_pad[12]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(12)); \ADDR_pad[2]\ : INBUF port map(PAD => ADDR(2), Y => \ADDR_c[2]\); HCLK_pad : CLKBUF port map(PAD => HCLK, Y => HCLK_c); TX_pad : OUTBUF port map(D => TX_c, PAD => TX); \RESP_err_pad[0]\ : OUTBUF port map(D => N_339_c, PAD => RESP_err(0)); \DATAOUT_pad[8]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(8)); \DATAOUT_pad[13]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(13)); \DATAIN_pad[0]\ : INBUF port map(PAD => DATAIN(0), Y => \DATAIN_c[0]\); CoreAHBLite_0 : top_CoreAHBLite_0_CoreAHBLite port map(AHBMASTER_FIC_0_AHBmaster_HADDR_26 => \AHBMASTER_FIC_0_AHBmaster_HADDR[28]\, AHBMASTER_FIC_0_AHBmaster_HADDR_27 => \AHBMASTER_FIC_0_AHBmaster_HADDR[29]\, AHBMASTER_FIC_0_AHBmaster_HADDR_28 => \AHBMASTER_FIC_0_AHBmaster_HADDR[30]\, AHBMASTER_FIC_0_AHBmaster_HADDR_29 => \AHBMASTER_FIC_0_AHBmaster_HADDR[31]\, AHBMASTER_FIC_0_AHBmaster_HADDR_0 => \AHBMASTER_FIC_0_AHBmaster_HADDR[2]\, AHBMASTER_FIC_0_AHBmaster_HADDR_1 => \AHBMASTER_FIC_0_AHBmaster_HADDR[3]\, AHBMASTER_FIC_0_AHBmaster_HADDR_2 => \AHBMASTER_FIC_0_AHBmaster_HADDR[4]\, AHBMASTER_FIC_0_AHBmaster_HADDR_22 => \AHBMASTER_FIC_0_AHBmaster_HADDR[24]\, AHBMASTER_FIC_0_AHBmaster_HADDR_23 => \AHBMASTER_FIC_0_AHBmaster_HADDR[25]\, AHBMASTER_FIC_0_AHBmaster_HADDR_24 => \AHBMASTER_FIC_0_AHBmaster_HADDR[26]\, AHBMASTER_FIC_0_AHBmaster_HADDR_25 => \AHBMASTER_FIC_0_AHBmaster_HADDR[27]\, masterAddrInProg_i_1_0 => \CoreAHBLite_0.matrix4x16.slavestage_0.masterAddrInProg_i_1[0]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(7) => \AHBMASTER_FIC_0_AHBmaster_HRDATA[7]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(6) => \AHBMASTER_FIC_0_AHBmaster_HRDATA[6]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(5) => \AHBMASTER_FIC_0_AHBmaster_HRDATA[5]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(4) => \AHBMASTER_FIC_0_AHBmaster_HRDATA[4]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(3) => \AHBMASTER_FIC_0_AHBmaster_HRDATA[3]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(2) => \AHBMASTER_FIC_0_AHBmaster_HRDATA[2]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(1) => \AHBMASTER_FIC_0_AHBmaster_HRDATA[1]\, AHBMASTER_FIC_0_AHBmaster_HRDATA(0) => \AHBMASTER_FIC_0_AHBmaster_HRDATA[0]\, xhdl1222_0 => \CoreAHBLite_0.matrix4x16.xhdl1222[0]\, CoreAPB_0_APBmslave0_PRDATA(7) => \CoreAPB_0_APBmslave0_PRDATA[7]\, CoreAPB_0_APBmslave0_PRDATA(6) => \CoreAPB_0_APBmslave0_PRDATA[6]\, CoreAPB_0_APBmslave0_PRDATA(5) => \CoreAPB_0_APBmslave0_PRDATA[5]\, CoreAPB_0_APBmslave0_PRDATA(4) => \CoreAPB_0_APBmslave0_PRDATA[4]\, CoreAPB_0_APBmslave0_PRDATA(3) => \CoreAPB_0_APBmslave0_PRDATA[3]\, CoreAPB_0_APBmslave0_PRDATA(2) => \CoreAPB_0_APBmslave0_PRDATA[2]\, CoreAPB_0_APBmslave0_PRDATA(1) => \CoreAPB_0_APBmslave0_PRDATA[1]\, CoreAPB_0_APBmslave0_PRDATA(0) => \CoreAPB_0_APBmslave0_PRDATA[0]\, AHBMASTER_FIC_0_AHBmaster_HTRANS_0 => \AHBMASTER_FIC_0_AHBmaster_HTRANS[1]\, arbRegSMCurrentState_RNICAHF7_0 => \arbRegSMCurrentState_RNICAHF7[0]\, arbRegSMCurrentState_i_0_3 => \CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_i_0[15]\, arbRegSMCurrentState_i_0_0 => \CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_i_0[12]\, AHBMASTER_FIC_0_AHBmaster_HWDATA(7) => \AHBMASTER_FIC_0_AHBmaster_HWDATA[7]\, AHBMASTER_FIC_0_AHBmaster_HWDATA(6) => \AHBMASTER_FIC_0_AHBmaster_HWDATA[6]\, AHBMASTER_FIC_0_AHBmaster_HWDATA(5) => \AHBMASTER_FIC_0_AHBmaster_HWDATA[5]\, AHBMASTER_FIC_0_AHBmaster_HWDATA(4) => \AHBMASTER_FIC_0_AHBmaster_HWDATA[4]\, AHBMASTER_FIC_0_AHBmaster_HWDATA(3) => \AHBMASTER_FIC_0_AHBmaster_HWDATA[3]\, AHBMASTER_FIC_0_AHBmaster_HWDATA(2) => \AHBMASTER_FIC_0_AHBmaster_HWDATA[2]\, AHBMASTER_FIC_0_AHBmaster_HWDATA(1) => \AHBMASTER_FIC_0_AHBmaster_HWDATA[1]\, AHBMASTER_FIC_0_AHBmaster_HWDATA(0) => \AHBMASTER_FIC_0_AHBmaster_HWDATA[0]\, CoreAHBLite_0_AHBmslave0_HWDATA(7) => \CoreAHBLite_0_AHBmslave0_HWDATA[7]\, CoreAHBLite_0_AHBmslave0_HWDATA(6) => \CoreAHBLite_0_AHBmslave0_HWDATA[6]\, CoreAHBLite_0_AHBmslave0_HWDATA(5) => \CoreAHBLite_0_AHBmslave0_HWDATA[5]\, CoreAHBLite_0_AHBmslave0_HWDATA(4) => \CoreAHBLite_0_AHBmslave0_HWDATA[4]\, CoreAHBLite_0_AHBmslave0_HWDATA(3) => \CoreAHBLite_0_AHBmslave0_HWDATA[3]\, CoreAHBLite_0_AHBmslave0_HWDATA(2) => \CoreAHBLite_0_AHBmslave0_HWDATA[2]\, CoreAHBLite_0_AHBmslave0_HWDATA(1) => \CoreAHBLite_0_AHBmslave0_HWDATA[1]\, CoreAHBLite_0_AHBmslave0_HWDATA(0) => \CoreAHBLite_0_AHBmslave0_HWDATA[0]\, defSlaveSMCurrentState => \CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMCurrentState\, AHBMASTER_FIC_0_AHBmaster_HWRITE => AHBMASTER_FIC_0_AHBmaster_HWRITE, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, N_163 => N_163, CoreAHBLite_0_AHBmslave0_HREADY => CoreAHBLite_0_AHBmslave0_HREADY, N_254 => N_254, N_395 => N_395, N_265 => N_265, N_339_c => N_339_c, PREVDATASLAVEREADY_iv_i_0_i_o4_0 => \CoreAHBLite_0.matrix4x16.masterstage_0.PREVDATASLAVEREADY_iv_i_0_i_o4_0\, PREVDATASLAVEREADY_iv_i_0_i_o4_1 => \CoreAHBLite_0.matrix4x16.masterstage_0.PREVDATASLAVEREADY_iv_i_0_i_o4_1\, N_392 => N_392, N_391 => N_391, PRDATA_0_sqmuxa_0_a2_13 => \CoreAPB_0.COREAPB_oi0.PRDATA_0_sqmuxa_0_a2_13\, PRDATA_0_sqmuxa_0_a2_12 => \CoreAPB_0.COREAPB_oi0.PRDATA_0_sqmuxa_0_a2_12\, N_327 => N_327, N_340 => N_340, N_330 => N_330, N_397 => N_397, N_398 => N_398, N_171 => \CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.N_171\, N_263 => N_263, N_367 => N_367, un1_N_11_mux_i_5_a1_1 => \CoreAHB2APB_0.un1_N_11_mux_i_5_a1_1\, CoreAHBLite_0_AHBmslave0_HSELx => CoreAHBLite_0_AHBmslave0_HSELx, N_363 => N_363, HADDR_24_0_a3_i_out => \CoreAHBLite_0.matrix4x16.slavestage_0.HADDR_24_0_a3_i_out\, un4_m5_0_a3_2 => \CoreAHB2APB_0.un4_m5_0_a3_2\, N_128 => N_128, N_124 => N_124, N_120 => N_120, N_22 => N_22, N_20 => N_20, N_135 => N_135, N_18 => N_18, N_326 => N_326, N_323 => N_323, HTRANS_0_a3_i_a2_3_0 => \CoreAHBLite_0.matrix4x16.slavestage_0.HTRANS_0_a3_i_a2_3_0\, HTRANS_0_a3_i_a2_4_0 => \CoreAHBLite_0.matrix4x16.slavestage_0.HTRANS_0_a3_i_a2_4_0\, N_365 => N_365, N_364 => N_364, un1_m1_e_0_0 => \CoreAHB2APB_0.un1_m1_e_0_0\, un4_m5_0_a3_1 => \CoreAHB2APB_0.un4_m5_0_a3_1\); \ADDR_pad[3]\ : INBUF port map(PAD => ADDR(3), Y => \ADDR_c[3]\); \DATAOUT_pad[7]\ : OUTBUF port map(D => \DATAOUT_c[7]\, PAD => DATAOUT(7)); \DATAOUT_pad[1]\ : OUTBUF port map(D => \DATAOUT_c[1]\, PAD => DATAOUT(1)); \DATAOUT_pad[15]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(15)); \DATAOUT_pad[21]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(21)); \DATAOUT_pad[20]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(20)); GND_i : GND port map(Y => \GND\); \DATAOUT_pad[29]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(29)); \DATAOUT_pad[24]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(24)); \DATAIN_pad[1]\ : INBUF port map(PAD => DATAIN(1), Y => \DATAIN_c[1]\); \DATAOUT_pad[26]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(26)); \DATAOUT_pad[17]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(17)); \ADDR_pad[26]\ : INBUF port map(PAD => ADDR(26), Y => \ADDR_c[26]\); \ADDR_pad[4]\ : INBUF port map(PAD => ADDR(4), Y => \ADDR_c[4]\); LREAD_pad : INBUF port map(PAD => LREAD, Y => LREAD_c); CoreUARTapb_0 : top_CoreUARTapb_0_CoreUARTapb port map(CoreAPB_0_APBmslave0_PRDATA(7) => \CoreAPB_0_APBmslave0_PRDATA[7]\, CoreAPB_0_APBmslave0_PRDATA(6) => \CoreAPB_0_APBmslave0_PRDATA[6]\, CoreAPB_0_APBmslave0_PRDATA(5) => \CoreAPB_0_APBmslave0_PRDATA[5]\, CoreAPB_0_APBmslave0_PRDATA(4) => \CoreAPB_0_APBmslave0_PRDATA[4]\, CoreAPB_0_APBmslave0_PRDATA(3) => \CoreAPB_0_APBmslave0_PRDATA[3]\, CoreAPB_0_APBmslave0_PRDATA(2) => \CoreAPB_0_APBmslave0_PRDATA[2]\, CoreAPB_0_APBmslave0_PRDATA(1) => \CoreAPB_0_APBmslave0_PRDATA[1]\, CoreAPB_0_APBmslave0_PRDATA(0) => \CoreAPB_0_APBmslave0_PRDATA[0]\, CoreAPB_0_APBmslave0_PWDATA(7) => \CoreAPB_0_APBmslave0_PWDATA[7]\, CoreAPB_0_APBmslave0_PWDATA(6) => \CoreAPB_0_APBmslave0_PWDATA[6]\, CoreAPB_0_APBmslave0_PWDATA(5) => \CoreAPB_0_APBmslave0_PWDATA[5]\, CoreAPB_0_APBmslave0_PWDATA(4) => \CoreAPB_0_APBmslave0_PWDATA[4]\, CoreAPB_0_APBmslave0_PWDATA(3) => \CoreAPB_0_APBmslave0_PWDATA[3]\, CoreAPB_0_APBmslave0_PWDATA(2) => \CoreAPB_0_APBmslave0_PWDATA[2]\, CoreAPB_0_APBmslave0_PWDATA(1) => \CoreAPB_0_APBmslave0_PWDATA[1]\, CoreAPB_0_APBmslave0_PWDATA(0) => \CoreAPB_0_APBmslave0_PWDATA[0]\, CoreAPB_0_APBmslave0_PADDR(4) => \CoreAPB_0_APBmslave0_PADDR[4]\, CoreAPB_0_APBmslave0_PADDR(3) => \CoreAPB_0_APBmslave0_PADDR[3]\, CoreAPB_0_APBmslave0_PADDR(2) => \CoreAPB_0_APBmslave0_PADDR[2]\, TX_c => TX_c, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, CoreAPB_0_APBmslave0_PENABLE => CoreAPB_0_APBmslave0_PENABLE, CoreAPB_0_APBmslave0_PWRITE => CoreAPB_0_APBmslave0_PWRITE, CoreAPB_0_APBmslave0_PSELx => CoreAPB_0_APBmslave0_PSELx); \ADDR_pad[29]\ : INBUF port map(PAD => ADDR(29), Y => \ADDR_c[29]\); \DATAIN_pad[6]\ : INBUF port map(PAD => DATAIN(6), Y => \DATAIN_c[6]\); ahb_busy_pad : OUTBUF port map(D => ahb_busy_c, PAD => ahb_busy); \DATAOUT_pad[31]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(31)); \DATAOUT_pad[30]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(30)); \DATAIN_pad[3]\ : INBUF port map(PAD => DATAIN(3), Y => \DATAIN_c[3]\); \ADDR_pad[24]\ : INBUF port map(PAD => ADDR(24), Y => \ADDR_c[24]\); \RESP_err_pad[1]\ : OUTBUF port map(D => \GND\, PAD => RESP_err(1)); \ADDR_pad[25]\ : INBUF port map(PAD => ADDR(25), Y => \ADDR_c[25]\); \DATAOUT_pad[9]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(9)); \DATAOUT_pad[28]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(28)); LWRITE_pad : INBUF port map(PAD => LWRITE, Y => LWRITE_c); \DATAOUT_pad[3]\ : OUTBUF port map(D => \DATAOUT_c[3]\, PAD => DATAOUT(3)); \DATAOUT_pad[22]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(22)); \ADDR_pad[27]\ : INBUF port map(PAD => ADDR(27), Y => \ADDR_c[27]\); \DATAOUT_pad[6]\ : OUTBUF port map(D => \DATAOUT_c[6]\, PAD => DATAOUT(6)); \DATAOUT_pad[11]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(11)); \DATAOUT_pad[10]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(10)); \DATAOUT_pad[4]\ : OUTBUF port map(D => \DATAOUT_c[4]\, PAD => DATAOUT(4)); CoreAHB2APB_0 : CoreAHB2APB port map(CoreAHBLite_0_AHBmslave0_HWDATA(7) => \CoreAHBLite_0_AHBmslave0_HWDATA[7]\, CoreAHBLite_0_AHBmslave0_HWDATA(6) => \CoreAHBLite_0_AHBmslave0_HWDATA[6]\, CoreAHBLite_0_AHBmslave0_HWDATA(5) => \CoreAHBLite_0_AHBmslave0_HWDATA[5]\, CoreAHBLite_0_AHBmslave0_HWDATA(4) => \CoreAHBLite_0_AHBmslave0_HWDATA[4]\, CoreAHBLite_0_AHBmslave0_HWDATA(3) => \CoreAHBLite_0_AHBmslave0_HWDATA[3]\, CoreAHBLite_0_AHBmslave0_HWDATA(2) => \CoreAHBLite_0_AHBmslave0_HWDATA[2]\, CoreAHBLite_0_AHBmslave0_HWDATA(1) => \CoreAHBLite_0_AHBmslave0_HWDATA[1]\, CoreAHBLite_0_AHBmslave0_HWDATA(0) => \CoreAHBLite_0_AHBmslave0_HWDATA[0]\, CoreAPB_0_APBmslave0_PWDATA(7) => \CoreAPB_0_APBmslave0_PWDATA[7]\, CoreAPB_0_APBmslave0_PWDATA(6) => \CoreAPB_0_APBmslave0_PWDATA[6]\, CoreAPB_0_APBmslave0_PWDATA(5) => \CoreAPB_0_APBmslave0_PWDATA[5]\, CoreAPB_0_APBmslave0_PWDATA(4) => \CoreAPB_0_APBmslave0_PWDATA[4]\, CoreAPB_0_APBmslave0_PWDATA(3) => \CoreAPB_0_APBmslave0_PWDATA[3]\, CoreAPB_0_APBmslave0_PWDATA(2) => \CoreAPB_0_APBmslave0_PWDATA[2]\, CoreAPB_0_APBmslave0_PWDATA(1) => \CoreAPB_0_APBmslave0_PWDATA[1]\, CoreAPB_0_APBmslave0_PWDATA(0) => \CoreAPB_0_APBmslave0_PWDATA[0]\, CoreAPB_0_APBmslave0_PADDR(4) => \CoreAPB_0_APBmslave0_PADDR[4]\, CoreAPB_0_APBmslave0_PADDR(3) => \CoreAPB_0_APBmslave0_PADDR[3]\, CoreAPB_0_APBmslave0_PADDR(2) => \CoreAPB_0_APBmslave0_PADDR[2]\, CoreAHB2APB_0_APBmaster_PSELx(15) => \CoreAHB2APB_0_APBmaster_PSELx[15]\, CoreAHB2APB_0_APBmaster_PSELx(14) => \CoreAHB2APB_0_APBmaster_PSELx[14]\, CoreAHB2APB_0_APBmaster_PSELx(13) => \CoreAHB2APB_0_APBmaster_PSELx[13]\, CoreAHB2APB_0_APBmaster_PSELx(12) => \CoreAHB2APB_0_APBmaster_PSELx[12]\, CoreAHB2APB_0_APBmaster_PSELx(11) => \CoreAHB2APB_0_APBmaster_PSELx[11]\, CoreAHB2APB_0_APBmaster_PSELx(10) => \CoreAHB2APB_0_APBmaster_PSELx[10]\, CoreAHB2APB_0_APBmaster_PSELx(9) => \CoreAHB2APB_0_APBmaster_PSELx[9]\, CoreAHB2APB_0_APBmaster_PSELx(8) => \CoreAHB2APB_0_APBmaster_PSELx[8]\, CoreAHB2APB_0_APBmaster_PSELx(7) => \CoreAHB2APB_0_APBmaster_PSELx[7]\, CoreAHB2APB_0_APBmaster_PSELx(6) => \CoreAHB2APB_0_APBmaster_PSELx[6]\, CoreAHB2APB_0_APBmaster_PSELx(5) => \CoreAHB2APB_0_APBmaster_PSELx[5]\, CoreAHB2APB_0_APBmaster_PSELx(4) => \CoreAHB2APB_0_APBmaster_PSELx[4]\, CoreAHB2APB_0_APBmaster_PSELx(3) => \CoreAHB2APB_0_APBmaster_PSELx[3]\, CoreAHB2APB_0_APBmaster_PSELx(2) => \CoreAHB2APB_0_APBmaster_PSELx[2]\, CoreAHB2APB_0_APBmaster_PSELx(1) => \CoreAHB2APB_0_APBmaster_PSELx[1]\, arbRegSMCurrentState_i_0_0 => \CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_i_0[12]\, arbRegSMCurrentState_i_0_3 => \CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_i_0[15]\, xhdl1222_0 => \CoreAHBLite_0.matrix4x16.xhdl1222[0]\, masterAddrInProg_i_1_0 => \CoreAHBLite_0.matrix4x16.slavestage_0.masterAddrInProg_i_1[0]\, arbRegSMCurrentState_RNICAHF7_0 => \arbRegSMCurrentState_RNICAHF7[0]\, CoreAPB_0_APBmslave0_PWRITE => CoreAPB_0_APBmslave0_PWRITE, CoreAPB_0_APBmslave0_PSELx => CoreAPB_0_APBmslave0_PSELx, HRESETn_c => HRESETn_c, HCLK_c => HCLK_c, CoreAPB_0_APBmslave0_PENABLE => CoreAPB_0_APBmslave0_PENABLE, N_124_0 => N_124, N_128_0 => N_128, N_22 => N_22, N_20 => N_20, N_18 => N_18, N_395 => N_395, N_363 => N_363, N_364 => N_364, HTRANS_0_a3_i_a2_3_0 => \CoreAHBLite_0.matrix4x16.slavestage_0.HTRANS_0_a3_i_a2_3_0\, N_265 => N_265, N_392 => N_392, N_135 => N_135, N_367 => N_367, defSlaveSMCurrentState => \CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMCurrentState\, N_391 => N_391, HTRANS_0_a3_i_a2_4_0 => \CoreAHBLite_0.matrix4x16.slavestage_0.HTRANS_0_a3_i_a2_4_0\, N_398 => N_398, un1_N_11_mux_i_5_a1_1 => \CoreAHB2APB_0.un1_N_11_mux_i_5_a1_1\, N_327 => N_327, un4_m5_0_a3_1 => \CoreAHB2APB_0.un4_m5_0_a3_1\, un4_m5_0_a3_2 => \CoreAHB2APB_0.un4_m5_0_a3_2\, N_171 => \CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.N_171\, N_330 => N_330, N_397 => N_397, N_326 => N_326, un1_m1_e_0_0 => \CoreAHB2APB_0.un1_m1_e_0_0\, CoreAHBLite_0_AHBmslave0_HREADY => CoreAHBLite_0_AHBmslave0_HREADY, CoreAHBLite_0_AHBmslave0_HSELx => CoreAHBLite_0_AHBmslave0_HSELx, HADDR_24_0_a3_i_out => \CoreAHBLite_0.matrix4x16.slavestage_0.HADDR_24_0_a3_i_out\, N_263 => N_263, N_323 => N_323, N_365 => N_365, N_254 => N_254, N_120 => N_120); \ADDR_pad[31]\ : INBUF port map(PAD => ADDR(31), Y => \ADDR_c[31]\); \ADDR_pad[30]\ : INBUF port map(PAD => ADDR(30), Y => \ADDR_c[30]\); \DATAOUT_pad[5]\ : OUTBUF port map(D => \DATAOUT_c[5]\, PAD => DATAOUT(5)); \DATAOUT_pad[19]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(19)); HRESETn_pad : CLKBUF port map(PAD => HRESETn, Y => HRESETn_c); \DATAOUT_pad[14]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(14)); \DATAOUT_pad[23]\ : OUTBUF port map(D => \GND\, PAD => DATAOUT(23)); end DEF_ARCH;