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[/] [ahbmaster/] [trunk/] [test79_AHBmaster/] [tooldata/] [AHBMASTER_FIC_tools.xml] - Rev 3

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><toolSetting xmlns="http://actel.com/sweng/afi" component="AHBMASTER_FIC" xmlns:actel-cc="http://www.actel.com/XMLSchema/CoreConsole" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.1"><device VendorTechnology_Die="UM4X4M1N" VendorTechnology_DieVoltage="1.5" VendorTechnology_Family="ProASIC3" VendorTechnology_PART_RANGE="IND" VendorTechnology_Package="vq100" VendorTechnology_Speed="STD"><advancedoptions IO_DEFT_STD="LVTTL" RESERVEMIGRATIONPINS="1" RESTRICTPROBEPINS="1" RESTRICTSPIPINS="0" TARGETDEVICESFORMIGRATION="UM4X4M1N" TEMPR="IND" UNUSED_MSS_IO_RESISTOR_PULL="None" VCCI_1.5_VOLTR="COM" VCCI_1.8_VOLTR="COM" VCCI_2.5_VOLTR="COM" VCCI_3.3_VOLTR="COM" VOLTR="IND"/></device><tool Constraint_Default="true" Simulation_Default="true" Source_Default="true" Stimulus_Default="true" internal_name="VIEWDRAWCONFIGURATOR" library="Tool" name="ViewDraw" state="0" vendor="Actel" version="1.0.100"><configuration/><input_files/><output_files/><report_files/></tool><tool Constraint_Default="true" Simulation_Default="true" Source_Default="true" Stimulus_Default="true" internal_name="SYNTHESIZE_PS" library="Tool" name="Precision" state="0" vendor="Mentor" version="1.0.100"><configuration/><input_files/><output_files/><report_files/></tool><tool Constraint_Default="true" Simulation_Default="true" Source_Default="true" Stimulus_Default="true" internal_name="SYNTHESIZE" library="Tool" name="Synthesize" state="1" vendor="Synopsys" version="1.0.104"><configuration><spirit:hwParameter spirit:name="CLOCK_ASYNC">12</spirit:hwParameter><spirit:hwParameter spirit:name="CLOCK_DATA">5000</spirit:hwParameter><spirit:hwParameter spirit:name="CLOCK_GLOBAL">2</spirit:hwParameter><spirit:hwParameter spirit:name="RAM_OPTIMIZED_FOR_POWER">false</spirit:hwParameter><spirit:hwParameter spirit:name="RETIMING">false</spirit:hwParameter><spirit:hwParameter spirit:name="SYNPLIFY_OPTIONS"/><spirit:hwParameter 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omponents.vhd</path><type>HDL</type><fileset>HDL_FILESET</fileset><local>true</local><used>false</used><selectable>true</selectable><timestamp>1527947388</timestamp><used_for_compile>false</used_for_compile><used_for_synthesis>false</used_for_synthesis><used_for_timing>false</used_for_timing></file><file><path>component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUART.vhd</path><type>HDL</type><fileset>HDL_FILESET</fileset><local>true</local><used>false</used><selectable>true</selectable><timestamp>1527947388</timestamp><used_for_compile>false</used_for_compile><used_for_synthesis>false</used_for_synthesis><used_for_timing>false</used_for_timing></file><file><path>component\work\top\CoreUARTapb_0\rtl\vhdl\core\CoreUARTapb.vhd</path><type>HDL</type><fileset>HDL_FILESET</fileset><local>true</local><used>false</used><selectable>true</selectable><timestamp>1527947388</timestamp><used_for_compile>false</used_for_compile><used_for_synthesis>false</used_for_synthesis><used_for_timing>false</used_for_timing></file><file><path>component\work\top\CoreUARTapb_0\rtl\vhdl\core\coreuart_pkg.vhd</path><type>HDL</type><fileset>HDL_FILESET</fileset><local>true</local><used>false</used><selectable>true</selectable><timestamp>1527947388</timestamp><used_for_compile>false</used_for_compile><used_for_synthesis>false</used_for_synthesis><used_for_timing>false</used_for_timing></file><file><path>component\work\top\CoreUARTapb_0\rtl\vhdl\core\fifo_256x8_pa3.vhd</path><type>HDL</type><fileset>HDL_FILESET</fileset><local>true</local><used>false</used><selectable>true</selectable><timestamp>1527947388</timestamp><used_for_compile>false</used_for_compile><used_for_synthesis>false</used_for_synthesis><used_for_timing>false</used_for_timing></file><file><path>component\work\top\CoreUARTapb_0\rtl\vhdl\core\Rx_async.vhd</path><type>HDL</type><fileset>HDL_FILESET</fileset><local>true</local><used>false</used><selectable>true</selectable><timestamp>1527947388</timestamp><used_for_compile>false</used_for_compile><used_for_synthesis>false</used_for_synthesis><used_for_timing>false</used_for_timing></file><file><path>component\work\top\CoreUARTapb_0\rtl\vhdl\core\Tx_async.vhd</path><type>HDL</type><fileset>HDL_FILESET</fileset><local>true</local><used>false</used><selectable>true</selectable><timestamp>1527947388</timestamp><used_for_compile>false</used_for_compile><used_for_synthesis>false</used_for_synthesis><used_for_timing>false</used_for_timing></file><file><path>component\work\top\top.vhd</path><type>HDL</type><fileset>HDL_FILESET</fileset><local>true</local><used>false</used><selectable>true</selectable><timestamp>1527947388</timestamp><used_for_compile>false</used_for_compile><used_for_synthesis>false</used_for_synthesis><used_for_timing>false</used_for_timing></file><file><path>hdl\AHBMASTER_FIC.vhd</path><type>HDL</type><fileset>HDL_FILESET</fileset><local>true</local><used>true</used><selectable>true</selectable><timestamp>1527947376</timestamp><used_for_compile>false</used_for_compile><used_for_synthesis>false</used_for_synthesis><used_for_timing>false</used_for_timing></file><file><path>smartgen\FlashROM\FlashROM.vhd</path><type>HDL</type><fileset>HDL_FILESET</fileset><local>true</local><used>false</used><selectable>true</selectable><timestamp>1527782108</timestamp><used_for_compile>false</used_for_compile><used_for_synthesis>false</used_for_synthesis><used_for_timing>false</used_for_timing></file><file><path>synthesis\AHBMASTER_FIC_sdc.sdc</path><type>SDC_ROOT</type><fileset>OTHER_SYNTHESIS_FILESET</fileset><local>true</local><used>false</used><selectable>true</selectable><timestamp>1527947400</timestamp><used_for_compile>false</used_for_compile><used_for_synthesis>false</used_for_synthesis><used_for_timing>false</used_for_timing></file></input_files><output_files><file><path>synthesis\AHBMASTER_FIC.edn</path><type>EDN</type><fileset>HDL_FILESET</fileset><local>true</local><used>false</used><selectable>true</selectable><timestamp>1527947400</timestamp><used_for_compile>false</used_for_compile><used_for_synthesis>false</used_for_synthesis><used_for_timing>false</used_for_timing></file></output_files><report_files><file><path>synthesis\synplify.log</path><type>LOG</type><fileset>OTHER_FILESET</fileset><local>true</local><used>false</used><selectable>true</selectable><timestamp>0</timestamp><used_for_compile>false</used_for_compile><used_for_synthesis>false</used_for_synthesis><used_for_timing>false</used_for_timing></file><file><path>synthesis\AHBMASTER_FIC.srr</path><type>LOG</type><fileset>OTHER_FILESET</fileset><local>true</local><used>false</used><selectable>true</selectable><timestamp>0</timestamp><used_for_compile>false</used_for_compile><used_for_synthesis>false</used_for_synthesis><used_for_timing>false</used_for_timing></file><file><path>synthesis\AHBMASTER_FIC.areasrr</path><type>LOG</type><fileset>OTHER_FILESET</fileset><local>true</local><used>false</used><selectable>true</selectable><timestamp>0</timestamp><used_for_compi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