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[/] [alpha_blender/] [trunk/] [alpha_blender/] [full_adder.vhd] - Rev 2
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library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity full_adder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; cout : out STD_LOGIC; sum : out STD_LOGIC); end full_adder; architecture Behavioral of full_adder is begin cout <= (a and b) or (b and cin) or (a and cin); sum <= (a xor b) xor cin; end Behavioral;