Subversion Repositories altor32

//-----------------------------------------------------------------
//                           AltOR32 
//                Alternative Lightweight OpenRisc 
//                            V2.0
//                     Ultra-Embedded.com
//                   Copyright 2011 - 2013
//
//               Email: admin@ultra-embedded.com
//
//                       License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without         
// restriction provided that this copyright statement is not    
// removed from the file and that any derivative work contains  
// the original copyright notice and the associated disclaimer. 
//
// This source file is free software; you can redistribute it   
// and/or modify it under the terms of the GNU Lesser General   
// Public License as published by the Free Software Foundation; 
// either version 2.1 of the License, or (at your option) any   
// later version.
//
// This source is distributed in the hope that it will be       
// useful, but WITHOUT ANY WARRANTY; without even the implied   
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
// PURPOSE.  See the GNU Lesser General Public License for more 
// details.
//
// You should have received a copy of the GNU Lesser General    
// Public License along with this source; if not, write to the 
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
// Boston, MA  02111-1307  USA
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "altor32_defs.v"
 
//-----------------------------------------------------------------
// Module - Cache substitute (used when ICache disabled)
//-----------------------------------------------------------------
module altor32_noicache 
( 
    input                       clk_i /*verilator public*/,
    input                       rst_i /*verilator public*/,
 
    // Processor interface
    input                       rd_i /*verilator public*/,
    input [31:0]                pc_i /*verilator public*/,
    output [31:0]               instruction_o /*verilator public*/,
    output                      valid_o /*verilator public*/,
 
    // Memory interface
    output reg [31:0]           wbm_addr_o /*verilator public*/,
    input [31:0]                wbm_dat_i /*verilator public*/,
    output [2:0]                wbm_cti_o /*verilator public*/,
    output reg                  wbm_cyc_o /*verilator public*/,
    output reg                  wbm_stb_o /*verilator public*/,
    input                       wbm_stall_i/*verilator public*/,
    input                       wbm_ack_i/*verilator public*/
);
 
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
 
// Current state
parameter STATE_CHECK       = 0;
parameter STATE_FETCH       = 1;
reg                        state;
 
reg                        ignore_resp;
 
assign valid_o              = wbm_ack_i & ~ignore_resp & ~rd_i;
assign instruction_o        = wbm_dat_i;
 
//-----------------------------------------------------------------
// Control logic
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
   if (rst_i == 1'b1)
   begin
        wbm_addr_o      <= 32'h00000000;
        wbm_stb_o       <= 1'b0;
        wbm_cyc_o       <= 1'b0;
        ignore_resp     <= 1'b0;
        state           <= STATE_CHECK;   
   end
   else
   begin
 
        if (~wbm_stall_i)
            wbm_stb_o    <= 1'b0;
 
        case (state)
 
            //-----------------------------------------
            // CHECK - check cache for hit or miss
            //-----------------------------------------
            STATE_CHECK :
            begin
                // Start fetch from memory
                wbm_addr_o  <= pc_i;
                wbm_stb_o   <= 1'b1;
                wbm_cyc_o   <= 1'b1;
                ignore_resp <= 1'b0;
                state       <= STATE_FETCH;
            end
            //-----------------------------------------
            // FETCH - Fetch row from memory
            //-----------------------------------------
            STATE_FETCH :
            begin
                // Read whilst waiting for previous response?        
                if (rd_i)
                    ignore_resp <= 1'b1;
 
                // Data ready from memory?
                if (wbm_ack_i)
                begin
                    wbm_cyc_o   <= 1'b0;
                    state       <= STATE_CHECK;
                end
            end
 
            default:
                ;
           endcase
   end
end
 
assign wbm_cti_o        = 3'b111;
 
endmodule