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Subversion Repositories fpz8
[/] [altsyncram0.vhd] - Rev 4
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-- megafunction wizard: %ALTSYNCRAM% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: altsyncram0.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY altsyncram0 IS PORT ( address : IN STD_LOGIC_VECTOR (13 DOWNTO 0); clock : IN STD_LOGIC := '1'; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END altsyncram0; ARCHITECTURE SYN OF altsyncram0 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( clock_enable_input_a : STRING; clock_enable_output_a : STRING; init_file : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; ram_block_type : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( clock0 : IN STD_LOGIC ; address_a : IN STD_LOGIC_VECTOR (13 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", init_file => "FPZ8_test.mif", intended_device_family => "Cyclone II", lpm_hint => "ENABLE_RUNTIME_MOD=NO", lpm_type => "altsyncram", numwords_a => 16384, operation_mode => "ROM", outdata_aclr_a => "NONE", outdata_reg_a => "UNREGISTERED", power_up_uninitialized => "FALSE", ram_block_type => "M4K", widthad_a => 14, width_a => 8, width_byteena_a => 1 ) PORT MAP ( clock0 => clock, address_a => address, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" -- Retrieval info: PRIVATE: CLRdata NUMERIC "0" -- Retrieval info: PRIVATE: CLRq NUMERIC "0" -- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRrren NUMERIC "0" -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRwren NUMERIC "0" -- Retrieval info: PRIVATE: Clock NUMERIC "0" -- Retrieval info: PRIVATE: Clock_A NUMERIC "0" -- Retrieval info: PRIVATE: Clock_B NUMERIC "0" -- Retrieval info: PRIVATE: ECC NUMERIC "0" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" -- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "FPZ8_test.mif" -- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "0" -- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4" -- Retrieval info: PRIVATE: REGdata NUMERIC "1" -- Retrieval info: PRIVATE: REGq NUMERIC "0" -- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" -- Retrieval info: PRIVATE: REGrren NUMERIC "1" -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" -- Retrieval info: PRIVATE: REGwren NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" -- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" -- Retrieval info: PRIVATE: VarWidth NUMERIC "0" -- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" -- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" -- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" -- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" -- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" -- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: enable NUMERIC "0" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INIT_FILE STRING "FPZ8_test.mif" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL address[13..0] -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_wave*.jpg FALSE -- Retrieval info: LIB_FILE: altera_mf
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