URL
https://opencores.org/ocsvn/am9080_cpu_based_on_microcoded_am29xx_bit-slices/am9080_cpu_based_on_microcoded_am29xx_bit-slices/trunk
Subversion Repositories am9080_cpu_based_on_microcoded_am29xx_bit-slices
[/] [am9080_cpu_based_on_microcoded_am29xx_bit-slices/] [trunk/] [ipcore_dir/] [ram4kx8_flist.txt] - Rev 6
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# Output products list for <ram4kx8>
_xmsgs\pn_parser.xmsgs
ram4kx8.asy
ram4kx8.gise
ram4kx8.ngc
ram4kx8.sym
ram4kx8.vhd
ram4kx8.vho
ram4kx8.xco
ram4kx8.xise
ram4kx8\blk_mem_gen_v7_3_readme.txt
ram4kx8\doc\blk_mem_gen_v7_3_vinfo.html
ram4kx8\doc\pg058-blk-mem-gen.pdf
ram4kx8\example_design\ram4kx8_exdes.ucf
ram4kx8\example_design\ram4kx8_exdes.vhd
ram4kx8\example_design\ram4kx8_exdes.xdc
ram4kx8\example_design\ram4kx8_prod.vhd
ram4kx8\implement\implement.bat
ram4kx8\implement\implement.sh
ram4kx8\implement\planAhead_ise.bat
ram4kx8\implement\planAhead_ise.sh
ram4kx8\implement\planAhead_ise.tcl
ram4kx8\implement\xst.prj
ram4kx8\implement\xst.scr
ram4kx8\simulation\addr_gen.vhd
ram4kx8\simulation\bmg_stim_gen.vhd
ram4kx8\simulation\bmg_tb_pkg.vhd
ram4kx8\simulation\checker.vhd
ram4kx8\simulation\data_gen.vhd
ram4kx8\simulation\functional\simcmds.tcl
ram4kx8\simulation\functional\simulate_isim.bat
ram4kx8\simulation\functional\simulate_mti.bat
ram4kx8\simulation\functional\simulate_mti.do
ram4kx8\simulation\functional\simulate_mti.sh
ram4kx8\simulation\functional\simulate_ncsim.sh
ram4kx8\simulation\functional\simulate_vcs.sh
ram4kx8\simulation\functional\ucli_commands.key
ram4kx8\simulation\functional\vcs_session.tcl
ram4kx8\simulation\functional\wave_mti.do
ram4kx8\simulation\functional\wave_ncsim.sv
ram4kx8\simulation\ram4kx8_synth.vhd
ram4kx8\simulation\ram4kx8_tb.vhd
ram4kx8\simulation\random.vhd
ram4kx8\simulation\timing\simcmds.tcl
ram4kx8\simulation\timing\simulate_isim.bat
ram4kx8\simulation\timing\simulate_mti.bat
ram4kx8\simulation\timing\simulate_mti.do
ram4kx8\simulation\timing\simulate_mti.sh
ram4kx8\simulation\timing\simulate_ncsim.sh
ram4kx8\simulation\timing\simulate_vcs.sh
ram4kx8\simulation\timing\ucli_commands.key
ram4kx8\simulation\timing\vcs_session.tcl
ram4kx8\simulation\timing\wave_mti.do
ram4kx8\simulation\timing\wave_ncsim.sv
ram4kx8_flist.txt
ram4kx8_xmdf.tcl
summary.log