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# ----------------------------------------------------------------
#                                                               //
#   Xilinx FPGA synthesis constraints file                      //
#                                                               //
#   This file is part of the Amber project                      //
#   http://www.opencores.org/project,amber                      //
#                                                               //
#   Description                                                 //
#                                                               //
#   Author(s):                                                  //
#       - Conor Santifort, csantifort.amber@gmail.com           //
#                                                               //
#/ ///////////////////////////////////////////////////////////////
#                                                               //
#  Copyright (C) 2010 Authors and OPENCORES.ORG                 //
#                                                               //
#  This source file may be used and distributed without         //
#  restriction provided that this copyright statement is not    //
#  removed from the file and that any derivative work contains  //
#  the original copyright notice and the associated disclaimer. //
#                                                               //
#  This source file is free software; you can redistribute it   //
#  and/or modify it under the terms of the GNU Lesser General   //
#  Public License as published by the Free Software Foundation; //
#  either version 2.1 of the License, or (at your option) any   //
#  later version.                                               //
#                                                               //
#  This source is distributed in the hope that it will be       //
#  useful, but WITHOUT ANY WARRANTY; without even the implied   //
#  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
#  PURPOSE.  See the GNU Lesser General Public License for more //
#  details.                                                     //
#                                                               //
#  You should have received a copy of the GNU Lesser General    //
#  Public License along with this source; if not, download it   //
#  from http://www.opencores.org/lgpl.shtml                     //
#                                                               //
# ----------------------------------------------------------------

############################################################################
# VCC AUX VOLTAGE 
############################################################################
CONFIG VCCAUX=2.5;

############################################################################
## Clock constraints                                                        
############################################################################

# 200MHz board clock that feeds the PLL
NET "u_clocks_resets/brd_clk_ibufg" TNM_NET = "BRD_CLK";
TIMESPEC "TS_PLL_CLK" = PERIOD "BRD_CLK"  5.0  ns HIGH 50 %;

# 25 MHz Ethernet MII transmit clock
NET "mtx_clk_pad_i" TNM_NET = "MTX_CLK";
TIMESPEC "TS_MTX_CLK" = PERIOD "MTX_CLK"  40.0  ns HIGH 50 %;

# 25 MHz Ethernet MII receive clock
NET "mrx_clk_pad_i" TNM_NET = "MRX_CLK";
TIMESPEC "TS_MRX_CLK" = PERIOD "MRX_CLK"  40.0  ns HIGH 50 %;

# False paths between clocks
PIN "u_ddr3/memc3_infrastructure_inst/u_pll_adv.CLKOUT3" TNM = "DDR_CLK";
PIN "u_clocks_resets/u_pll_adv.CLKOUT2" TNM = "CLKOUT2";
TIMESPEC "TS_false2"  = FROM "DDR_CLK" TO "CLKOUT2" TIG;


############################################################################
# DDR2 requires the MCB to operate in Extended performance mode with higher Vccint
# specification to achieve maximum frequency. Therefore, the following CONFIG constraint
# follows the corresponding GUI option setting. However, DDR3 can operate at higher 
# frequencies with any Vcciint value by operating MCB in extended mode. Please do not
# remove/edit the below constraint to avoid false errors.
############################################################################
CONFIG MCB_PERFORMANCE= EXTENDED;


##################################################################################
# Timing Ignore constraints for paths crossing the clock domain 
##################################################################################
NET "u_ddr3/memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "u_ddr3/c?_pll_lock" TIG;
INST "u_ddr3/memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;



############################################################################
## I/O TERMINATION                                                          
############################################################################
NET "ddr3_dq[*]"                                 IN_TERM = UNTUNED_SPLIT_50;
NET "ddr3_dqs_p[*]"                              IN_TERM = UNTUNED_SPLIT_50;
NET "ddr3_dqs_n[*]"                              IN_TERM = UNTUNED_SPLIT_50;

############################################################################
# I/O STANDARDS 
############################################################################

NET  "ddr3_dq[*]"                                IOSTANDARD = SSTL15_II;
NET  "ddr3_addr[*]"                              IOSTANDARD = SSTL15_II;
NET  "ddr3_ba[*]"                                IOSTANDARD = SSTL15_II;
NET  "ddr3_dqs_p[*]"                             IOSTANDARD = DIFF_SSTL15_II;
NET  "ddr3_dqs_n[*]"                             IOSTANDARD = DIFF_SSTL15_II;
NET  "ddr3_ck_p"                                 IOSTANDARD = DIFF_SSTL15_II;
NET  "ddr3_ck_n"                                 IOSTANDARD = DIFF_SSTL15_II;
NET  "ddr3_cke"                                  IOSTANDARD = SSTL15_II;
NET  "ddr3_ras_n"                                IOSTANDARD = SSTL15_II;
NET  "ddr3_cas_n"                                IOSTANDARD = SSTL15_II;
NET  "ddr3_we_n"                                 IOSTANDARD = SSTL15_II;
NET  "ddr3_odt"                                  IOSTANDARD = SSTL15_II;
NET  "ddr3_reset_n"                              IOSTANDARD = SSTL15_II;
NET  "ddr3_dm[*]"                                IOSTANDARD = SSTL15_II;
NET  "mcb3_rzq"                                  IOSTANDARD = SSTL15_II;
#NET  "mcb3_zio"                                  IOSTANDARD = SSTL15_II;
NET  "brd_clk_p"                                 IOSTANDARD = LVDS_25;
NET  "brd_clk_n"                                 IOSTANDARD = LVDS_25;
NET  "brd_rst"                                   IOSTANDARD = LVCMOS15;

NET  "mtx_clk_pad_i"                             IOSTANDARD = LVCMOS25;
NET  "mtxd_pad_o[*]"                             IOSTANDARD = LVCMOS25;
NET  "mtxen_pad_o"                               IOSTANDARD = LVCMOS25;
NET  "mtxerr_pad_o"                              IOSTANDARD = LVCMOS25;
NET  "mrx_clk_pad_i"                             IOSTANDARD = LVCMOS25;
NET  "mrxd_pad_i[*]"                             IOSTANDARD = LVCMOS25;
NET  "mrxdv_pad_i"                               IOSTANDARD = LVCMOS25;
NET  "mrxerr_pad_i"                              IOSTANDARD = LVCMOS25;
NET  "mcoll_pad_i"                               IOSTANDARD = LVCMOS25;
NET  "mcrs_pad_i"                                IOSTANDARD = LVCMOS25;
NET  "md_pad_io"                                 IOSTANDARD = LVCMOS25;
NET  "mdc_pad_o"                                 IOSTANDARD = LVCMOS25;
NET  "phy_reset_n"                               IOSTANDARD = LVCMOS25;
NET  "led[*]"                                    IOSTANDARD = LVCMOS25;


############################################################################
# Pin Location Constraints
############################################################################
NET "brd_rst"                                    LOC = H8;
NET "brd_clk_n"                                  LOC = K22;
NET "brd_clk_p"                                  LOC = K21;
NET "o_uart0_cts"                                LOC = F18;
NET "i_uart0_rts"                                LOC = F19;
NET "o_uart0_rx"                                 LOC = B21;
NET "i_uart0_tx"                                 LOC = H17;
NET "led[0]"                                     LOC = D17;
NET "led[1]"                                     LOC = AB4;
NET "led[2]"                                     LOC = D21;
NET "led[3]"                                     LOC = W15;


############################################################################
# DDR3 Interface pin locations
############################################################################
NET  "ddr3_addr[0]"                              LOC = "K2" ;
NET  "ddr3_addr[10]"                             LOC = "J4" ;
NET  "ddr3_addr[11]"                             LOC = "E1" ;
NET  "ddr3_addr[12]"                             LOC = "F1" ;
NET  "ddr3_addr[1]"                              LOC = "K1" ;
NET  "ddr3_addr[2]"                              LOC = "K5" ;
NET  "ddr3_addr[3]"                              LOC = "M6" ;
NET  "ddr3_addr[4]"                              LOC = "H3" ;
NET  "ddr3_addr[5]"                              LOC = "M3" ;
NET  "ddr3_addr[6]"                              LOC = "L4" ;
NET  "ddr3_addr[7]"                              LOC = "K6" ;
NET  "ddr3_addr[8]"                              LOC = "G3" ;
NET  "ddr3_addr[9]"                              LOC = "G1" ;
NET  "ddr3_ba[0]"                                LOC = "J3" ;
NET  "ddr3_ba[1]"                                LOC = "J1" ;
NET  "ddr3_ba[2]"                                LOC = "H1" ;
NET  "ddr3_cas_n"                                LOC = "M4" ;
NET  "ddr3_ck_p"                                 LOC = "K4" ;
NET  "ddr3_ck_n"                                 LOC = "K3" ;
NET  "ddr3_cke"                                  LOC = "F2" ;
NET  "ddr3_dm[0]"                                LOC = "N4" ;
NET  "ddr3_dq[0]"                                LOC = "R3" ;
NET  "ddr3_dq[10]"                               LOC = "U3" ;
NET  "ddr3_dq[11]"                               LOC = "U1" ;
NET  "ddr3_dq[12]"                               LOC = "W3" ;
NET  "ddr3_dq[13]"                               LOC = "W1" ;
NET  "ddr3_dq[14]"                               LOC = "Y2" ;
NET  "ddr3_dq[15]"                               LOC = "Y1" ;
NET  "ddr3_dq[1]"                                LOC = "R1" ;
NET  "ddr3_dq[2]"                                LOC = "P2" ;
NET  "ddr3_dq[3]"                                LOC = "P1" ;
NET  "ddr3_dq[4]"                                LOC = "L3" ;
NET  "ddr3_dq[5]"                                LOC = "L1" ;
NET  "ddr3_dq[6]"                                LOC = "M2" ;
NET  "ddr3_dq[7]"                                LOC = "M1" ;
NET  "ddr3_dq[8]"                                LOC = "T2" ;
NET  "ddr3_dq[9]"                                LOC = "T1" ;
NET  "ddr3_dqs_p[0]"                             LOC = "N3" ;
NET  "ddr3_dqs_n[0]"                             LOC = "N1" ;
NET  "ddr3_odt"                                  LOC = "L6" ;
NET  "ddr3_ras_n"                                LOC = "M5" ;
NET  "ddr3_reset_n"                              LOC = "E3" ;

NET  "ddr3_dm[1]"                                LOC = "P3" ;
NET  "ddr3_dqs_p[1]"                             LOC = "V2" ;
NET  "ddr3_dqs_n[1]"                             LOC = "V1" ;
NET  "ddr3_we_n"                                 LOC = "H2" ;

# The following pins are available for used as RZQ or ZIO pins#
NET  "mcb3_rzq"                                  LOC = "K7" ;
#NET  "mcb3_zio"                                  LOC = "R7" ;

############################################################################
# Ethernet MII MAC to PHY interface
############################################################################
NET  "mtx_clk_pad_i"                             LOC = "L20" ;
NET  "mtxd_pad_o[0]"                             LOC = "U10" ;
NET  "mtxd_pad_o[1]"                             LOC = "T10" ;
NET  "mtxd_pad_o[2]"                             LOC = "AB8" ;
NET  "mtxd_pad_o[3]"                             LOC = "AA8" ;
NET  "mtxen_pad_o"                               LOC = "T8" ;
NET  "mtxerr_pad_o"                              LOC = "U8" ;
NET  "mrx_clk_pad_i"                             LOC = "P20" ;
NET  "mrxd_pad_i[0]"                             LOC = "P19" ;
NET  "mrxd_pad_i[1]"                             LOC = "Y22" ;
NET  "mrxd_pad_i[2]"                             LOC = "Y21" ;
NET  "mrxd_pad_i[3]"                             LOC = "W22" ;
NET  "mrxdv_pad_i"                               LOC = "T22" ;
NET  "mrxerr_pad_i"                              LOC = "U20" ;
NET  "mcoll_pad_i"                               LOC = "M16" ;
NET  "mcrs_pad_i"                                LOC = "N15" ;
NET  "md_pad_io"                                 LOC = "V20" ;
NET  "mdc_pad_o"                                 LOC = "R19" ;
NET  "phy_reset_n"                               LOC = "J22" ;